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Voltage Source Inverter with Low THD

Ilhami Colak*, Member IEEE, Ersan Kabalci**, Ramazan Bayindir, Member IEEE and Seref Sagiroglu, Member IEEE

Gazi Electrical Machines and Energy Control (GEMEC) Group

* Department of Electrical Education, Faculty of Technical Education, Gazi University, Besevler, Ankara 06500, Turkey

** Department of Technical Programs, Vocational Collage of Haci Bektas, Nevsehir University, Hacibektas, Nevsehir-Turkey

icolak@gazi.edu.tr, ekabalci@gazi.edu.tr, bayindir@gazi.edu.tr, ss@gazi.edu.tr

Abstract-Multilevel inverters have been important devices

developed in recent years, owing to their capability to increase the

voltage and power delivered to the load. Researches done based

on basic inverter topologies show that, multilevel inverters have

many advantages such as low power dissipation on power

switches, low harmonic and low electromagnetic interference

(EMI) outputs. A modified Sinusoidal Pulse Width Modulation

(SPWM) modulator that reduces output harmonics is presented in

this paper. The proposed modulation technique can be easily

applied to any multilevel inverter topology carrying out the

necessary calculations. The most common multilevel inverter

topologies have been studied to define the best topology for

SPWM modulation strategy. It is seen that cascaded H-bridges

are the most convenient solution. The cascaded H-bridge cells

have been constituted by IGBT semiconductors, and switched by

the proposed 24-channel SPWM modulator to obtain 5-level

output at the back-end of the 3-phase voltage source inverter

(VSI). The designed H-bridge cells have a strong switching

bandwidth up to 40 KHz, owing to its robustly designed

modulator block. The proposed VSI in this paper also has a Total

Harmonic Distortion ratio of output current (THDi) around at

0.1% without requiring any filtering circuit. The harmonic

analysis of proposed design has been executed under several

working conditions such as various switching frequencies and

modulation indexes. The detailed comparisons have been

performed to determine the best working conditions of VSI and

presented in this paper.

I.

INTRODUCTION

would be a limitation of complexity and number of clamping

diodes for the diode clamped inverters, when the level exceeds

the three [6]-[9].

Table I summarizes the THD ratio of output voltage, the

required switching elements, clamping diodes, number of DC

bus capacitor. Required total material for a 5-level inverter is

given as an example for three main multilevel topologies. It is

also seen the control disadvantages of diode clamped topology

due to its requirements from the list. In addition to this, diode

clamped inverters THD ratio is higher than other topologies.

The flying capacitor inverters are based on balancing

capacitors on phase buses. This property will cause to increase

number of required capacitor in high level inverter structures

and complexity of considering DC-link balancing. Among the

three types of multilevel inverters, the cascade inverter has the

least components for a given number of levels. Cascade

multilevel inverters consists of a series of H-bridge cells to

synthesize a desired voltage from several separate DC sources

(SDCSs) which may be obtained from batteries or fuel cells.

All these properties of cascade inverters allow using various

pulse width modulation (PWM) strategies to control the

inverter accurately [9]-[14]. Different types of feed-forward

and feed-back PWM control schemes have been developed to

control the Voltage Source Inverters (VSIs).

of medium voltage and high power applications due to their

many advantages, such as low voltage stress on power

semiconductor,

low

harmonic

distortions,

good

electromagnetic compatibility, reduced switching losses and

improved reliability on fault tolerance. Comparing with twolevel inverter topologies at the same power ratings, multilevel

inverters have the advantages that the harmonic components of

line-to-line voltages fed to load are reduced owing to its

switching frequencies. Therefore, the multilevel inverters also

have lower dv/dt ratios to prevent induction or discharge

failures on the loads. The multilevel inverter topologies are

classified into three categories up to now: Diode Clamped

Inverters, Flying Capacitor Inverters, and Cascaded Inverters

[1]-[6].

Based on research on several multilevel inverter topologies,

diode clamped inverters, particularly the three-level structure,

575

TABLE I

COMPARISON OF AN M-LEVEL INVERTER ACCORDING TO TOPOLOGIES

Single Phase Topologies

Half Bridge

Full Bridge

THDV (%)

163

156

Main power

switches per

phase

Clamping

diodes per

phase

DC bus

capacitor

Balancing

capacitor per

phase

Total material

for m=5

Control

Scheme

Applications

Diode

Clamped

36,9

33,1

32,4

2(m-1)

2(m-1)

2(m-1)

(m-1).(m-2)

(m-1)

(m-1)

(m-1)/2

(m-1).(m-2)/2

24

18

10

Regular

PWM

Regular

PWM

SHE-PWM,

SPWM

SPWM, SVM

<

2kV

<

2kV

SHE-PWM,

SPWM,

SVM

Motor drive,

STATCOM

Motor drive.,

STATCOM

PV, Motor

drive,

STATCOM,

Batteries

POWERENG 2009

techniques among the others applied in power switching

inverters. In SPWM, a sinusoidal reference voltage waveform

is compared with a triangular carrier waveform to generate

gate signals for the switches of inverter [15]-[19].

The objective of this paper is to develop a robustly designed

inverter block with mathematical model for SPWM modulator

to minimize THD ratios and compare to other conventional

models. The inverter output values will be discussed for

several switching frequencies and modulation indexes applied

to modulator. The results obtained from simulation of MatlabSimulink shows that the harmonic contents are greatly reduced

by using mathematically well designed SPWM modulator.

output level is the synthesize of cells output. By assuming the

number of inverters DC sources as n, the output levels of

each phase and each line voltage will be as shown in (2) and

(3) respectively [19]-[23].

m=2s+1

l=2m-1

Fig. 2 illustrates the power circuit for three phase of an nlevel inverter with n cells in each phase. The resulting phase

voltages are synthesized by the addition of the voltages

generated by the different cells as in (4)-(6).

INVERTER

A. Basic Principle of Multilevel Inverter and Application to Design

Fig. 1 shows the main H-bridge cell of one inverter used for

implementation of the multilevel inverter. The full bridge

inverter module includes four power switches and four

clamping diodes to form an H-bridge. A multilevel cascade

inverter consists a number of H-bridge cells that connected

series per phase, and each module requires a separate DC

source to generate voltage levels at the output of inverter. The

switching inputs shown as In1..4 in the Fig. 1 will allow

obtaining output voltages of each H-bridge as follows;

+V dc

V out = 0V dc

V

dc

In 1, In 4

In 1, In 3

on

on

In 2, In 3

on

(1)

levels of a cascade multilevel inverter. The considered full

bridge module generates 3-level output voltage itself as seen in

(1). The H-bridge cells are serially connected over AC outputs

(2)

(3)

Vbn = Vbc1+ Vbc2++ Vbcn

Vcn = Vca1+ Vca2++ Vcan

(4)

(5)

(6)

signals, comparing a sinusoidal control voltage with a

triangular carrier signal. SPWM technique has many inherent

advantages including low switching losses and relatively low

harmonics.

B. Modulation Strategy of Multilevel Inverter

All the PWM methods create load voltage harmonics, which

produce current harmonics and additional harmonic losses. To

minimize the harmonic contents of the output voltage of a

cascaded inverter, the switching angle for each H-bridge

inverter needs to be calculated accurately. A traditional five Hbridge cascaded inverter can produce an 11-level output

voltage which can be almost sinusoidal. Each switching angle

(Ssw(t)) of the inverter is calculated by Fourier series to

eliminate selected harmonics as in (7);

S sw (t ) =

a0

+ (an cos(nt ) +bn sin(nt ))

2 n =1

576

(7)

POWERENG 2009

Fourier coefficients a0, an, and bn are given by (8)-(10):

a0 =

an =

bn =

sw

sw

sw

(t )dt

(t ) cos(nt )dt

(t ) sin(n t )dt

(8)

(9)

(10)

Ssw(t) is given by (11);

cn = an + jbn

(11)

sinusoidal modulating signal which relatively has a lower

frequency compared to carrier at 50 Hz. The typically

modulated unipolar SPWM waveform is given in Fig. 3(b).

The unipolar modulation technique has a significant advantage

compared to bipolar equivalent due to preventing harmonic

orders of m2 and 3m2 at the high fundamental voltages. In

addition to this, the unipolar technique allows to decrease

switching losses up to 30% according to optimized PWM

methods. The function of switching algorithm in (7) is used to

find out the switching angles for the inverter cells and then

switching angles are transformed into switching reference

voltages. If any change occurs in the input DC voltage, the

algorithm will take into account the recent values since it is

depended on a0 parameter and adjust the switching reference

voltages to reduce output voltage harmonics [9]-[11],[24]-[26].

It is difficult to accurately control the switching angles of

inverter switches, thus results in the reduction of response

speed and the increase of harmonic contents in traditional

designs. Most of controllers are based on the use of FFT

analysis enabled processors; therefore a complex method is

required to compensate errors by using iterative calculations

and approximations of discrete data.

The main objective of static power inverters is to produce an

AC output waveform from a DC power supply. The obtained

AC type waveforms are appropriate for different applications

such as uninterruptible power supplies (UPS), static var

compensators, active filters, motor drives, flexible AC

transmission systems (FACTS), and voltage compensators. For

sinusoidal AC outputs of inverters, the magnitude, frequency,

and the phase should be controllable.

The proposed VSI design is based on the topology of Fig. 2

which includes dual H-bridge cells as shown in Fig. 1 per

phase to generate a 5-level output voltage. The main

topological calculations which are performed initially indicate

the requirements of modulator and inverter blocks, and allow

obtaining a well prepared modulation algorithm to increase the

performance of inverter. The proposed inverter includes 6 Hbridges and 4 SPWM switching signals to control each bridge

respectively. The modulation algorithm which is based on (8)(10) is performed in SPWM modulator to generate 24 separate

SPWM pulses to H-bridges as shown in Fig. 4.

A. The Designed Model for SPWM Modulator

The most well known SPWM which can be applied to

cascaded multilevel inverters is phase shifted SPWM and is

same as that of the conventional SPWM technique as seen in

Fig. 3. The output voltage level increment of inverter requires

increased modulating signals and moreover, in order to verify

the operation behavior and examine the harmonic content of

the multilevel inverter, these modulating signals are phase

shifted with respect to each other by an angle equal to:

360

(12)

n

where, n is number of switching signal. The additional

important point to be considered in the modulator design is

amplitude distortion. The amplitude distortion is caused by the

input DC voltage source variation and has the most significant

impact on the on-off spectral errors. For a voltage source

SPWM controlled DC-AC inverter, the amplitude distortion of

the PWM waveforms will decline the amplitude of the

fundamental component and introduce unexpected low order

harmonic contents as shown in (13) [21],[24]-[26].

VO (t ) =

2Vdc

maVdc

cos(r t )

2

k =1

2 2

(13)

Jn k .ma

2V

2

sin ( k + l ). cos(k .c t + l.r t )

+ dc

k

k =1 l =1

2

Fig. 3. The SPWM signal representation (a) triangular carrier signal and

sinusoidal modulating patterns and (b) the generated unipolar SPWM

switching signals

577

POWERENG 2009

Fig. 4. The Simulink design of cascaded multilevel inverter containing SPWM modulator and Y-wired RL load

where,

ma= amplitude of modulation ratio,

VDC= dc supply voltage,

r= sinusoidal reference frequency,

c= triangular reference frequency,

J 0 , J n = Bessel function.

The output periodic voltage waveform, V0(t), consists of three

major terms to eliminate possible harmonic contents in

generated AC output. The first term of (13) gives the amplitude

of fundamental component, which is directly proportional to

VDC and the amplitude of modulation ratio, ma, which is

defined as in (14).

ma =

obtain 5-level output at the back-end of the 3-phase voltage

source inverter. The H-bridge cells have 3 different switching

options as shown in (1) and the switching orders form a 5-level

voltage output as seen in Fig. 6(b). The line-to-line voltage

rates of inverter are determined according to modulation

indexes (mi), and working areas are defined as linear

modulation (mi 1) or over-modulation (mi>1) ranges. The

line-to-line voltages are limited to ( 3Vd 2 ) of dc line in linear

modulation range and to (4/).( 3Vd 2 ) in over- modulation

range.

V ref

V tri

(14)

harmonics at the carrier frequency and the multiples of carrier.

The last term indicates the amplitudes of the harmonics in the

sidebands around each multiples of the carrier frequency. The

SPWM modulator in Fig. 4 contains 12 separate phase shifted

sinusoidal modulating signal unit and the second block as

carrier generator and comparator units. The commutation dead

time and switching rise-fall time intervals are designed

according to (7)-(14). The control signals of H-bridge cells are

shown in Fig. 5 as phase shifted as discussed before.

B. H-Bridge Inverter Block

Fig. 6(a) shows the proposed inverter block which consists

of dual H-bridge cells per phase as generating A, B and C

voltage outputs. The cascaded H-bridge cells have been

constituted by IGBT semiconductors as seen in Fig. 1 and

578

POWERENG 2009

Fig. 8 (a) and Fig. 8 (b) respectively. The output current and

voltage values have been increased in over-modulation range

since mi is over 1, but the THD rates have been changed

nonlinearly. The lowest THD for current has been measured as

0.1% during 10 KHz switching frequency and mi= 0.8

conditions. The THD for voltage has been measured as 0.66%

under same conditions as shown in Fig. 8 (b). Fig. 9 (a)

represents a pattern of FFT analyses, which have been

performed to constitute the Fig. 8 (a) and (b), for current THD

at 10 KHz switching frequency. Fig. 9 (b), as another example,

shows the THD for current at 1 KHz switching frequency, and

the modulation index is 1 for both. The lower switching

frequency in linear modulation range has caused to higher

THD for current and voltage at the inverter output.

Fig.1 (b) 5-level line-to-line output voltage of inverter obtained at 1 KHz

switching frequency

The mathematical model of SPWM modulator has been

developed in Simulink and the success on harmonic preventing

has been compared to the conventional models as given in

[4],[5],[8],[9],[12],[15]-[18].

The SPWM modulator has a switching bandwidth between

0- 40 KHz to control H-bridges and Fig. 7 shows the values

which are obtained at 5 KHz switching conditions while mi= 1.

Fig. 7(a) and Fig. 7(b) represent the FFT analysis of the current

THD (THDi) and voltage THD (THDv) ratios in Simulink. The

switching frequency of SPWM modulator has been limited to

1-10 KHz, and modulation indexes are selected in 0.6 mi 1.4

range to analyze the effect of fsw and mi on THD of inverter. It

has been observed by the performed tests that reducing the

THD of current and voltage is depended on increasing the

modulation indexes (a) THD for current in % (b) THD for phase voltages in %

(a)

(b)

Fig. 7. THD analysis of inverter while fsw= 5 KHz and mi=1 (a) THD for

current is 1.34% (b) THD for phase voltage is 23.59%

(a)

(b)

Fig. 9. THD current analysis while mi=1 (a) THD for current is 0.73% at 10

KHz switching (b) THD for current is 9.80 % at 1 KHz switching

579

POWERENG 2009

V. CONCLUSIONS

In this paper, a three-phase 5-level cascaded multilevel

inverter with SPWM control has been presented, achieving

output signals with high quality and very low THD owing to

robustly designed mathematical model of modulator. The

spectral errors, such as switching fall and rise times and the

amplitude distortions of the SPWM waveforms which cause

distortions at output signals have been reduced by using

unipolar SPWM. The switching actions have been modeled in

Simulink by using interpolation processes to obtain properly

queued modulation signals. The phase shift orders of

modulating signals are another important point of design to

reduce THD of line current and voltages due to transferring

switching signals to semiconductors appropriately and also

preventing DC bus short circuit. The inverter block has been

designed by using dual H-bridges per phase. The DC level of

H-bridges has been intended to construct output levels and dual

DC supply at each phases have been constituted 5-level output

voltage as order of +2VDC, 0.VDC and -2VDC. The proposed

model has been tested and compared to its precedent

conventional models for THD rates and switching bandwidth.

The measurement results have presented perfect outcomes on

THD analysis. The modulation indexes in over modulation

range have caused non linear changes in THD values of output

current and voltages but on the other hand, the THD of output

current and voltages have seen extremely low in linear

modulation range according to IEEE 519-1992 (THD<5%). It

is also seen that the switching frequency is directly effective on

THD. The increment in switching frequency has showed its

reducer effect on THD of output current and voltages. In

addition, the measured harmonic contents have seen as

fundamental (50 Hz, 1st), 96th and 98th harmonics in 5 KHz and

10 KHz switching conditions of linear modulation area (mi1).

The harmonic contents of current, which have measured by

using modulation at 2 KHz and over, have seen as lower order

harmonics and magnitudes have measured lower than 0.2 A.

The THD of output voltage has been measured lower than 24%

in linear modulation band, and the most effective harmonic

contents except fundamental wave have seen at 96th and 98th as

in analysis of output current. The accuracy of design will be

verified with the results of continuing experimental studies.

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580

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