K L University

Department of Electronics and Communication Engineering

Course Handout for IVYear B.Tech program
A.Y.2016-17, First Semester
Course Name: DSP PROCESSORS & ARCHITECTURE

1. Course Code
2. Course Coordinator
3. L-T-P
5. Credits
6 .Team Members

:13-EC415
: P SATYANARAYANA
: 3-0-2
:4
: T.Anil Chowdary
: N Srinivasulu

7. Pre-requisite : 13-ES205
Course Objectives:
The objective of the course is to make the students learn how to use digital signal processors such as the
TMS320C54xx to perform real-time DSP on real signals. Due to advances in VLSI technology, programmable DSP devices
are becoming increasingly available and affordable. Therefore, these devices have become popular in the industry for
the design of products. Consequently, a large number of projects are planned and implemented using these devices.
Course Rationale
1. Justify the differences between a DSP processor and general purpose microprocessors.
2. Study the role of programmable devices in the implementation of DSP based systems.
3. Architectural issues of programmable DSP devices and their relationship to the algorithmic requirements.
4. Exposure to Pipeline, parallel execution, Arithmetic Instructions, Logic & Bit manipula-tion instructions, move
instruction, Program flow control instructions.
5. Implementation of basic DSP algorithms including filters, FFT algorithms, Quantization of sinusoidal signals and
Quantization of speech signals.

COURSE OUTCOMES (CO):

CO
No:
1
2
3
4

CO

SO

BTL

Acquire the fundamental concepts of Digital Signal Processing

a
e

1
1

Learn the architecture details of Digital signal processors Architecture

Learn the TMS320C54XX architecture details of Digital signal processors Architecture
Analyse and learn to implement the signal processing algorithms in DSPs.

Apply and Analyze DSP Algorithms through project oriented approach

COURSE OUTCOME INDICATORS (COI):

CO

2
3
4
5

COI-1

COI-2

Acquire the fundamental concepts of DFT,FFT and Acquire the knowledge about computational accuracy
Filter design
and Sources of errors in DSP implementations
Understand Architectural features of DSP Understand Data addressing capabilities of DSP
processors and computation building blocks
processors
Understand TMS320C54XX Architecture and Perceive instruction set of TMS320C54XX
addressing modes
Understand procedure to Implement various DSP Interfacing of Digital Signal processor with peripherals
Algorithms.
Simulation of DSP algorithms
Implementation of DSP algorithms on DSP Processor

SYLLABUS (As approved by BoS):

Course Title : DSP PROCESSORS & ARCHITECTURE
Pre-requisite : 13-ES205
Introduction to Digital Signal Processing: Review of a digital signal-processing system, Discrete Fourier Transform (DFT)
and Fast Fourier Transform (FFT), Linear Time Invariant Systems, Digital filters IIR and FIR, Decimation and interpolation.
Computational Accuracy in DSP Implementations: Number formats for signals and coefficients in DSP systems, Dynamic
range and precision, Sources of error in DSP implementations, ADC and DAC conversion errors, DSP computational
errors, Compensating filter. Architectures for Programmable DSP Devices: Basic Architectural features, DSP
computational building blocks, Bus architecture and memory, Data addressing capabilities, Address generation unit,
Programmability and program execution, Speed issues, Features for external interfacing. Execution Control and
Pipelining: Hardware looping, Interrupts, Stacks, Relative Branch support, Pipelining andPerformance, Pipeline Depth,
Interlocking, Branching effects, Interrupt effects, Pipeline Programmingmodels. Programmable Digital Signal Processors:
Commercial DSP Devices, Data Addressing modes ofTMS320C54XX, DSPs, Data Addressing modes of TMS320C54XX
Processors, Memory space ofTMS320C54XX Processors, Program Control, TMS320C54XX instructions and programming,
On-ChipPeripherals, Interrupts of TMS320C54XX processors, Pipeline operation of TMS320C54XX
Processors.Implementations of Basic DSP Algorithms: The Q-notation, FIR Filters, IIR Filters, Interpolation
Filters,Decimation Filters, PID Controller, Adaptive Filters, 2-D Signal Processing, An FFT Algorithm for DFTComputation,
A Butterfly Computation, Overflow and scaling, Bit-Reversed index generation, An 8-PointFFT implementation on the
TMS320C54XX, Computation of the signal spectrum. Interfacing Memoryand I/O Peripherals to Programmable DSP
Devices: Memory space organization, External businterfacing signals, Memory interface, Parallel I/O interface,
Programmed I/O, Interrupts and I/O, Directmemory access (DMA), A Multichannel buffered serial port (McBSP), McBSP
Programming, a CODECinterface circuit, CODEC programming, A CODEC-DSP interface example.
TEXT BOOKS
1. Signal Processing Avtar Singh and S. Srinivasan, Thomson Publications, 2004..
2.DSP Processor Fundamentals, Architectures & Features - Lapsley et al. S. Chand & Co, 2000.
REFERENCE BOOKS
1.Digital Signal Processors, Architecture, Programming and Applications B. Venkata Ramani and M.
Bhaskar, TMH, 2004.

2.Digital Signal Processing Principles, Algorithms Applications by J.G. Proakis & D.G. Manolokis, PHI,
COURSE DELIVERY PLAN:
Sess.
No.
1.

CO

COI

Topic (s)

2.
3.
4.
5.
6.

1
1
1
1
1

1
1
2
2
2

7.

A digital Signal Processing System, Sampling

Process and Discrete time sequence
Discrete Fourier Transform and Fast Fourier
Transform,
LTI FIR
Sytem
Digital
Filters:
and IIR,Decimation
Number formats for Signals and coefficients in DSP
Source
Sytem of Errors in DSP Implementation
Compensating filters
Basic Architectural features, Multiplier

8.

Shifter ,Barrel Shifter ,

9.

MAC unit and ALU

10.

Bus Architecture and Memoy, On-chip memory

Chalk and Talk,PPT

11.

Chalk and Talk,PPT

12.

13.

Data Addressing Capabilities

Special Addressing Modes, Address generation unit
,Programmability and Program Execution, Speed
issues
Commercial Digital Signal Processing DSP

14.
15.
16.
17.
18.
19.
20.
21.
22.
23.

3
3
3
3
3
4
4
4
4
4

1
1
2
2
2
1
1
1
1
1

TMS320C54XX Architecture, Data

Data
addressing
addressing
ModesModes ,
Memory Space, Program Control
TMS320C54XX Instructions
Onchip Peripherals, Interrupts, Pipeline operation
Q
and IIR implementation
of Notation,FIR
54XX processor
Interpolation and Decimation
PID controller
2D signal Processing
8 point FFT computation

Chalk and Talk,PPT

Chalk and Talk,PPT
Chalk and Talk,PPT
Chalk and Talk,PPT
Chalk and Talk,PPT
Chalk and Talk,PPT
Chalk and Talk,PPT
Chalk and Talk,PPT
Chalk and Talk,PPT
Chalk and Talk,PPT

Test3
Test3
Test3
Test3
Test3
SEE
SEE
SEE
SEE
SEE

24.

Memory Interfacing, DMA ,McBSp

Chalk and Talk,PPT

SEE

25.

CODEC, Programmed I/o,Handling of

interrupts

Chalk and Talk,PPT

Processors,TMS320C54XX Architecture

Teaching-Learning
Methods
Chalk and Talk,PPT

Evaluation
Components

Chalk and Talk,PPT

Chalk and Talk,PPT
Chalk and Talk,PPT
Chalk and Talk,PPT
Chalk and Talk,PPT

Test1
Test1
Test1
Test1
Test1

Chalk and Talk,PPT

Chalk and Talk,PPT

Test2
Test2
Test2

Chalk and Talk,PPT

Chalk and Talk,PPT

Test2
Test2
Test2

Test3

SEE

SESSION : 1
1.
2.

Recall Basics of Digital Signal Processing

Obtain Problem Solving skills on DFT, FFT

Time in
Minutes
5
30
10
30

10
10

Topic
BTL
Recap/Introduction
Introduction to DSP Processing system, Basics of
Sampling Process
Problems on Sampling
Discrete Time Sequence, Discrete Fourier
Transform, Basics of FFT and LTI Systems
Examples on DFT
Conclusion & Summary

Teaching
Method

Learning

Chalk and Talk, PPT

1
1

Group discussion
Chalk and Talk, PPT

Group discussion
Chalk and Talk, PPT

SESSION: 2
1. Understand the Concept of Digital Filters
2. Ability to design Digital Filters in different forms

Time in
Minutes
5
30
10
30
10
10

Topic
BTL
Recap on session 1
Digital Filters, FIR Filters, IIR Filters
Problems on FFT
FIR and IIR Filter Design, Direct form realization of
FIR filter for Interpolation I
Participate
Conclusion & Summary

Teaching
Method

Learning

1
1
1

Chalk and Talk, PPT

Case study
Chalk and Talk, PPT

Case study
Chalk and Talk, PPT

SESSION: 3
1. Understand Basics of Decimation and Interpolation
2. Acquiring Knowledge on Number formats

Time in
Minutes
5
30

Topic
BTL

Teaching
Method

Learning

Recap on session 2
Decimation and Interpolation, Fixed-Point Format

10
30

Participate

10
10

Participate
Conclusion & Summary

Double Precision Fixed Point Format, Floating Point

Format, Block Floating Point Format

Chalk and Talk, PPT

1
1

One Minute Paper

Chalk and Talk, PPT

Group Discussion
Chalk and Talk, PPT

SESSION: 4
1. Understand Dynamic Range and Precision
2. To Know about Sources of error in DSP Implementations

Time in
Minutes
5
30
10
30
10
10

Topic
BTL
Recap on session 3
Dynamic Range and Precision, Sources of Error in
DSP Implementation
Participate
A/D Conversion Errors, DSP Computation Errors, D/A
Conversion Errors
Participate
Conclusion & summary

Teaching
Method

Learning

Chalk and Talk, PPT

1
1

Think-Pair-Share
Chalk and Talk, PPT

Think-Pair-Share
Chalk and Talk, PPT

SESSION: 5
1. Get Insight about Compensating Filters.
2. Able to compare Performance of Filters

Time in
Minutes
5
30
10
30
10
10

Topic
BTL
Recap on session 4
D/A Conversion Errors, Discussion on problems,
Compensating Filters
Participate
Recap of FIR and IIR Filter Design, Advantages and
Disadvantages of Different Filters
Compensating Filter Design
Conclusion & Summary

Teaching
Method

Learning

Chalk and Talk, PPT

1
1

Quiz questions
Chalk and Talk, PPT

Home Assignment
Chalk and Talk, PPT

SESSION: 6
1. Know about Basic Architectural Features of General DSP Processor
2. Understand DSP Computational Building Blocks

Time in
Minutes
5
30

Topic
BTL

Teaching
Method

Learning

Recap of session 5.
Basic Architectural Features, DSP Computational
Building Blocks, Multiplier

Chalk and Talk, PPT

10
30

Participate

1
1

Fish Bowl
Chalk and Talk, PPT

10
10

Participate
Conclusion and Summary

Discussion
Chalk and Talk, PPT

Shifter, Barrel Shifter, MAC , ALU

SESSION: 7
1. Understand Bus Architecture and Memory Organization
2. Know about different addressing capabilities of DSP Processor

Time in
Minutes
5
30
10
30
10
10

Topic
BTL
Recap on session 6
Bus Architecture, Memory
Participate
Data Addressing Capabilities, Address Generation,
Programmability and Program Execution
Participate
Conclusion & Summary

Teaching
Method

Learning

1
1
1

Chalk and Talk, PPT

Demo on CCS
Chalk and Talk, PPT

Demo on CCS
Chalk and Talk, PPT

SESSION: 8
1. Knowledge on Programmability and Program Execution
2. Know about Parallelism and Pipelining.

Time in
Minutes
5
30

Topic
BTL

Teaching
Method

Learning

Recap on session 7
Program control, Program Sequencer, Speed IssuesHardware Architecture

Chalk and Talk, PPT

10
30

Participate

1
1

Quiz
Chalk and Talk, PPT

10
10

Participate
Conclusion & Summary

Group Discussion
Chalk and Talk, PPT

Parallelism, Pipelining, System Level Pipelining,

Features of External Interfacing

SESSION:9
1. Getting Aware of Commercial DSP Processor architectures
2. Know about TMS320C54XX Processor Architecture

Time in
Minutes
5
30

Topic
BTL

Teaching
Method

Learning

Recap on session 8
1

Chalk and Talk, PPT

1
1
1

One minute Paper

Chalk and Talk, PPT
Quiz

Commercial DSP Device architectures

10
30
10
10

Participate
Architecture of TMS320C54XX Processor
Participate
Conclusion & Summary

Chalk and Talk, PPT

SESSION:10
1. Familiarization with Data Addressing Modes of TMS320C54XX Processor
2. Programming with TMS320C54XX Processor

Time in
Minutes
5
30

Topic
BTL

Teaching
Method

Learning

Recap on session 9
Data Addressing modes of TMS320C54XX, Special
Addressing modes, Program Control

10
30

Examples on Addressing Modes

10
10

Participate
Conclusion & Summary

Instructions of TMS320C54XX Processor, Memory

Space of TMS320C54XX,

Chalk and Talk, PPT

1
1

Home Assignment
Chalk and Talk, PPT

Quiz
Chalk and Talk, PPT

SESSION:11
1. Programmability with TMS320C54XX Processor
2. Acquire Knowledge about Peripherals

Time in
Minutes
5
30

Topic
BTL

Teaching
Method

Learning

Recap on session 10
Instructions of TMS320C54XX Processor, On-Chip
Peripherals

10
30

Programming Examples of TMS320C54XX Processor

10
10

Participate
Conclusion & Summary

Hardware Timer, Host Port Interface, Clock

Generator, Serial I/O Ports

Chalk and Talk, PPT

1
1

Demo using CCS

Chalk and Talk, PPT

Quiz
Chalk and Talk, PPT

SESSION: 12
1.
2.

Time in
Minutes
5
30

10
30
10
10

Knowing about Different Interrupts available in TMS320C54XX

Knowledge about Serial Ports

Topic
BTL
Recap on session 11
Software Programmable wait-State Generator,
Programmable bank switching Logic, Buffered serial
ports
Participate
TDM serial ports, Interrupts of TMS320C54XX
Processor, Problem solving
Participate
Conclusion & Summary

Teaching
Method

Learning

Chalk and Talk, PPT

1
1

Fish Bowl
Chalk and Talk, PPT

Discussion
Chalk and Talk, PPT

SESSION: 13
1. Know about Pipeline Operation of TMS320C54XX
2. Program of FIR and IIR using Q-Notation

Time in
Minutes
5
30
10
30
10
10

Topic
BTL

Teaching
Method

Learning

Recap on session 12
Pipeline Operation of TMS320C54XX Processor, QNotation

Chalk and Talk, PPT

Problems on Q-Notation
FIR Implementation using Q-Notation, IIR
Implementation using Q-Notation
Participate
Conclusion & Summary

1
1

Problem solving
Chalk and Talk, PPT

Home Assignment
Chalk and Talk, PPT

SESSION: 14
1. Implement Interpolation and Decimation Filters using Q-Notation
2. Implement PID Controller using Q-Notation

Time in
Minutes
5
30

10
30
10
10

Topic
BTL
Recap on session 13
Interpolation Filter Implementation using QNotation, Decimation Filter Implementation using QNotation
Participate
Decimation Filter Implementation using Q-Notation,
ID Controller Implementation using Q-Notation
Participate
Conclusion & Summary

Teaching
Method

Learning

Chalk and Talk, PPT

1
1

Quiz
Chalk and Talk, PPT

Quiz
Chalk and Talk, PPT

SESSION: 15
1. Implement Adaptive Filters using Q-Notation
2. Knowledge of 2-D Signal Processing

Time in
Minutes
5
30

Topic
BTL

Teaching
Method

Learning

Recap on session 13
Adaptive Filter Implementation using Q-Notation

10
30

Participate

10
10

Participate
Conclusion & Summary

Matrix Multiplication using Q-Notation, 2-D Signal

Processing

Chalk and Talk, PPT

1
1

Quiz test
Chalk and Talk, PPT

Quiz test
Chalk and Talk, PPT

SESSION: 16
1.Compute DFT Computation using FFT
2.Compute DIT and DIF FFT Computation

Time in
Minutes
5
30
10
30
10
10

Topic
Recap on session 15
FFT Algorithm for DFT Computation
Participate
FFT Algorithm for DFT Computation, DIT FFT and DIF
FFT
Participate
Conclusion & Summary

BTL
1
1
1
1

Teaching
Method

Learning

Chalk and Talk, PPT

Discussion
Chalk and Talk, PPT
Student discussion
Chalk and Talk, PPT

Session:17
1. Compute Butterfly for Complex numbers
2. Compute 8-Point FFT on TMS320C54XX Processor

Time in
Minutes
5
30

10
30
10
10

Topic
BTL
Recap on session 16
Zero Padding, Butterfly Computation for Complex
numbers, Overflow and Scaling, Bit-Reversed Index
Generation for DIT FFT
Participate
8- Point FFT Implementation on the TMS320C54XX
Processor
Participate
Conclusion & Summary

Teaching
Method

Learning

Chalk and Talk, PPT

1
1

One Minute Paper

Chalk and Talk, PPT
Problem Solving
Chalk and Talk, PPT

SESSION: 18
1. Know of Overflow and Scaling in FFT Computation
2. Use of Bit-Reversed Addressing mode for FFT Computation

Time in
Minutes
5
30
10
30
10
10

Topic
BTL
Recap on session 17
8- Point FFT Implementation on the TMS320C54XX
Processor
Participate
Problem solving
Participate
Conclusion & Summary

Teaching
Method

Learning

Chalk and Talk, PPT

1
1
1

Brain storming session

Chalk and Talk, PPT
Brain storming discussion
Chalk and Talk, PPT

SESSION: 19
1. Understand about Memory Organization
2. know how to Interface Memory with TMS320C54XX Processor

Time in
Minutes
5
30

Topic
BTL

Teaching
Method

Learning

Recap on session 18
Memory Space Organization of On-chip DARAM in
data memory, Memory Space Organization of Onchip SARAM in data memory

Chalk and Talk, PPT

10
30

Participate

1
1

Focused listening
Chalk and Talk, PPT

10
10

Participate
Conclusion & Summary

Focused listening
Chalk and Talk, PPT

External bus Interfacing signals, Memory Interfacing,

Timing Sequence for External Memory Access

SESSION: 20
1. Know how to Interface Different Memory Devices with TMS320C54XX Processor
2. Know how to Interface SRAMt Memory Devices with TMS320C54XX Processor

Time in
Minutes
5
30
10
30
10
10

Topic
BTL

Teaching
Method

Learning

Recap on session 19
Wait states, No-Decode External Memory Interface,
Flash Memory Interface to TMS320C54XX Processor

Chalk and Talk, PPT

Participate
2KX16 SRAM Memory Interface with TMS320C5416
Participate
Conclusion & Summary

1
1
1

Focused listening
Chalk and Talk, PPT
Quiz session
Chalk and Talk, PPT

SESSION: 21
1. Know Interfacing RAM and ROM with TMS320C5416
2. Understand DMA Operations in TMS320C54XX
Time in
Minutes
5
30

Topic
BTL

Teaching
Method

Learning

Recap on session 20
1

Chalk and Talk, PPT

1
1

Home Assignment
Chalk and Talk, PPT

Quiz
Chalk and Talk, PPT

8KX16 ROM Memory Interface with TMS320C5416

10
30

Participate

10
10

Problem Solving
Conclusion & Summary

Direct Memory Access, DMA Operation

Configuration, Register Sub-addressing

SESSION: 22
1.
2.

Understand about Serial Port Interfacing and McBSP Programming

Understand CODEC Block Diagram and Interface circuit.
Time in
Minutes
5
30
10
30

Topic
BTL

Teaching
Method

Learning

Recap on session 21
Synchronous Serial Interface, Block Diagram of
McBSP of C54XX, McBSP Programming

Chalk and Talk and PPT

Participate

1
1

Quiz session
Chalk and Talk and PPT

Quiz session
Chalk and Talk, PPT

Programming to initialize McBSP2, CODEC Interface

circuit, Block Diagram of PCM3002 CODEC
10
10

Participate
Conclusion & Summary

SESSION: 23
1.
2.

Attain Knowledge about Interfacing PCM3002 with TMS320VC5416

Understand Data Transmission Formats for PCM3002.
Time in
Minutes
5
30

10
30

10
10

Topic
BTL

Teaching
Method

Learning

Recap on session 22
Interfacing PCM3002 with TMS320VC5416, Data
Transmission formats for the PCM3002 CODEC
Participate
Data Transmission formats for the PCM3002 CODEC,
CODEC Programming, Mode control Interface Signal
Timing
Participate
Conclusion & Summary

Chalk and Talk, PPT

1
1

Focused listening
Chalk and Talk, PPT

Focused listening
Chalk and Talk, PPT

Session: 24
1. Understand Registers of CODEC .
2. Understand interfacing of A/D

Time in
Minutes
5
20
10
20

10
10

Topic
BTL
Recap on session 23
Program Registers for the PCM3002 CODEC,
Participate
Programmed I/O, A/D Converter Interface in the
Programmed I/O Mode, Flow chart of the diagram
for software polling
Participate
Conclusion & Summary

Teaching
Method

Learning

1
1
1

Chalk and Talk, PPT

Debate
Chalk and Talk, PPT

Debate
Chalk and Talk, PPT

SESSION: 25

1. To get Acquaintance with Interrupt Handling

2. Revise the concepts of Interfacing peripherals
Time in
Minutes
5
20
10
20
10
10

Topic
BTL
Recap on session 24
Interrupts and I/O, Handling of Interrupts, Flow chart
for Interrupt Handling
Example Problems
Revision
Participate
Conclusion & Summary

Teaching
Method

Learning

Chalk and Talk, PPT

1
1
1

Discussion
Chalk and Talk, PPT
Discussion
Chalk and Talk, PPT

EVALUATION PLAN:
Evaluation
Component

Wieghtage (%)
Marks

Duration
(Min.)

1
1

COI No.
BTL

TEST 1
TEST 2
TEST 3
Active Learning

Attendance
Lab Experiment
Project Review

CO1

Wieghtage 7.5%
Marks 30

90

Wieghtage 7.5%
Marks 30

90

Wieghtage 7.5%
Marks 30

90

Wieghtage (5%)
Marks 25
Weightage 5%
Marks 5
Weightage 5%
Marks 5
Weightage 2.5%
Marks 2.5

20

CO2
2
1

CO3

1
1

2
1

1
1

CONTINUOUS INTERNAL EVALUATION

3.75
3.75
15
15
3.75
3.75
15
15
3.75
15
1.25
1.25
1.25
6.25

6.25

CO4
2
1

1
1

CO5
2
1

1
2

2
2

3.75
15
1.25

6.25

6.25

Equal Wieghtage for all the lecture session (5%)

5
5

60

2.5
2.5

40
SEM END EVALUATION

SE Lab Exam
SE Project Exam
SE Theory Exam

Weightage 5%
Marks 5
Weightage 10%
Marks 10
Weightage 45%
Marks 60

5
5

50

10
10

50
180

4.5
6

4.5
6

4.5
6

4.5
6

4.5
6

4.5
6

9
12

9
12

List of Experiments
1. Solution Of Differential Equations
2. Generation of Sine wave
3. To Verify Linear Convolution
4. To Verify Circular Convolution
5. To Find The FFT of Given 1-D Signal And Plot
6. To Compute Power Density Spectrum Of A Sequence
7. Audio loopback and plotting as Amplitude Vs Time and FFT Magnitude.
8. Sampling rate conversion and analysis of their spectrums.
9. Record of machinery noise like fan or blower or diesel generator and obtaining its spectrum.
MINI PROJECTs
1. FIR Filters Design
2. IIR Filters Design
3. Adaptive Filters Design
4. Synthesis of select dual tone multi frequency (DTMF)
5. Sine wave and Square wave generation using Audio CODEC.
6.

Ramp Generation and Amplitude Modulation.

7. Delayed or echoed or flanged auditory feedback signal

Course Team members, Chamber Consultation Hours and Chamber Venue details:
S.No.

Name of Faculty

Chamber
Consultation
Day(s)
P Satyanarayana
Every day

T Anil Chowdary

Every day

4-5 pm

C204

N.Srinivasulu

Every day

4-5 pm

NI LAB

Signature of COURSE COORDINATOR

Recommended by HEAD OF DEPARTMENT:

Approved By: DEAN-ACADEMICS

Chamber Consultation Chamber

Signature
of
Timings for each day
Consultation Room Course faculty
No:
4-5 pm
C206