SUMMER COURSE ON IC DESIGN

CADENCE TOOL

AND ANALYSIS USING

Course Overview
IC Layout design methodology is used to design the layouts of Physical IP such as Standard
Cells, Memory cells, IOs and analog blocks which are used in a VLSI chip.
This program introduces you to the IC design, analysis and optimization techniques
commonly used in the industry to design layouts for Deep Sub-Micron (DSM) process.
Industry standard EDA tools will be used extensively. Topics such as Device Matching, DFM
(Design for Manufacturing), Latch-up and ESD (Electro Static Discharge) guidelines also will
be covered.
Every participant will get the opportunity to practice concepts taught in the class during the
lab sessions. The course will conclude with a project done under the supervision of faculty
members.

Pre-Requisites
1. Basic understanding of MOS Transistor operation

Contents of the Course

1. Overview of IC design
(i)
Full Custom design, Semi-custom design (1h)
2. Basics of Linux (2h)
3. RC & RLC Circuit Analysis(2h)
4. Basics of MOSFET Device(4h)
(i)
(ii)
(iii)
(iv)
(v)
(vi)
(vii)

Structure & operation of MOS Transistor

Threshold voltage of the MOS Transistor
Current Voltage characteristics & Chanel length Modulation
Sub-threshold conduction
Capacitance in MOS Transistor (Thin-oxide, p-n Junction, overlap
capacitance)
Scaling
Short & Narrow Channel Effects

5. Analysis & Design of Digital Circuits (Schematic Design) using Cadence ADE

(i)
(ii)
(iii)

Analysis of CMOS Inverter (Noise Margin, Delay)(2h)

Logic Gates: NAND, AND, NOR, OR, XOR, XNOR(5h)
Digital Circuits: Different combinational & Sequential Circuits,
Implementation of Boolean Expressions(5h)

6. Analysis & Design of Analog Circuits (Schematic Design) using Cadence ADE
(i)

Current Mirror, Band-gap Reference circuits, Two stage OP-AMP, Differential

Amplifier, VCO(8h)

7. IC Fabrication Technology(3h)
(i)
Overview of IC Fabrication Process
(ii)
Wafer Processing
(iii)
IC Photolithographic Process
(iv)
Oxidation
(v)
Ion Implantation
(vi)
Deposition and Etching
(vii) Fabrication of Active Devices (NMOS, PMOS, CMOS)
(viii) Fabrication of Passive Devices (Capacitors, Resistors, Inductors)
(ix)
Interconnects
8. Layout Design and Post-layout Simulation using CADENCE Virtuoso Layout Editor
(i)
(ii)
(iii)
(iv)
(v)

Stick Diagram(1h)
Micron & Lambda Rule(2h)
Drawing Layouts of Digital & Analog Circuits(5h)
DRC, LVS & RCX(3h)
Post Layout Simulations & Analysis(3h)

9. Signal Integrity (Capacitive Coupling), Electro Static Discharge (ESD), Latch Up (LUP),
Device Matching techniques and PDKs(2h)
10.Placement of Power Ring, Pad-frames in Layout and streaming (GDS-II)(2h)

Notes:
Date 20th June to 30th June
Duration of the course 10 days (50 hours)

Course Coordinator: Prof. Prakash Kumar Rout

Resource Persons:

Prof. Prakash Kumar Rout

Prof. Sushant Kumar Patnaik

Prof. Umakanta Nanda

Prof. Aradhana Raju
Prof. Dhananjaya Tripathy

To
The Director
Silicon Institute of Technology
Bhubaneswar

Sub: Course fee for the summer course on IC DESIGN AND ANALYSIS USING CADENCE
TOOL
Respected Sir,
The course fee has been proposed to be Rs. 5000/- per participant and the breakup of the
expenses is given as below.
Total Expected Students: 30
Sl.
No.
1
2
3
4
5

Particular
Folder and Stationary
Tiffin (for 10 days)
Remuneration for Resource
Persons
Support Staff
Miscellaneous ( Study
Material, Certificates, Last
Day lunch, fuel expenses,
etc)

Unit Cost
(Rs.)
60
35

Total Expenditure on the particulars

(Rs.)
1800
(30+10) x 35 x 10 = 14,000
20 hrs. x 750 = 15,000 (Theory)
30 hrs. x 750 x 2 person =45,000 (Lab)
7500

8000

750

TOTAL EXPENDITURE
Total Amount to be collected from Students@5000
Individual fees for each course
=(Total Amount collected/30)
Fund Generation for Institute & Lab Utilization
(Adv. VLSI Lab)

91,300
1,50,000
5000
58,700

I would like to request you to approve the course fee of Rs. 5000/- for the above mentioned summer course.

With best regards,

Prakash Kumar Rout

(Course Coordinator &
HOD Dept. of AEIE)