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Flash memory

For the neuropsychological concept related to human medical electronics, and so on. In addition to being nonmemory, see Flashbulb memory.
volatile, ash memory oers fast read access times, as
Flash memory is an electronic non-volatile computer fast as dynamic RAM, although not as fast as static RAM
or ROM. Its mechanical shock resistance helps explain
its popularity over hard disks in portable devices, as does
its high durability, being able to withstand high pressure,
temperature, immersion in water, etc.[2]
Although ash memory is technically a type of EEPROM, the term EEPROM is generally used to refer
specically to non-ash EEPROM which is erasable in
small blocks, typically bytes. Because erase cycles are
slow, the large block sizes used in ash memory erasing
give it a signicant speed advantage over non-ash EEPROM when writing large amounts of data. As of 2013,
ash memory costs much less than byte-programmable
EEPROM and has become the dominant memory type
wherever a system requires a signicant amount of nonvolatile, solid-state storage.

A USB ash drive. The chip on the left is the ash memory. The
controller is on the right.

storage medium that can be electrically erased and reprogrammed.

1 History

Introduced by Toshiba in 1984, ash memory was

developed from EEPROM (electrically erasable programmable read-only memory). There are two main
types of ash memory, which are named after the NAND
and NOR logic gates. The individual ash memory cells
exhibit internal characteristics similar to those of the corresponding gates.

Flash memory (both NOR and NAND types) was invented by Dr. Fujio Masuoka while working for Toshiba
circa 1980.[3][4] According to Toshiba, the name ash
was suggested by Masuokas colleague, Shji Ariizumi,
because the erasure process of the memory contents reminded him of the ash of a camera.[5] Masuoka and
colleagues presented the invention at the IEEE 1984 InWhereas EPROMs had to be completely erased before ternational Electron Devices Meeting (IEDM) held in San
being rewritten, NAND type ash memory may be writ- Francisco.[6]
ten and read in blocks (or pages) which are generally
Intel Corporation saw the massive potential of the invenmuch smaller than the entire device. NOR type ash al- tion and introduced the rst commercial NOR type ash
lows a single machine word (byte) to be writtento an
chip in 1988.[7] NOR-based ash has long erase and write
erased locationor read independently.
times, but provides full address and data buses, allowing
The NAND type is primarily used in memory cards, USB
ash drives, solid-state drives (those produced in 2009 or
later), and similar products, for general storage and transfer of data. NAND or NOR ash memory is also often
used to store conguration data in numerous digital products, a task previously made possible by EEPROM or
battery-powered static RAM. One signicant disadvantage of ash memory is the nite number of read/write
cycles in a specic block.[1]

random access to any memory location. This makes it a

suitable replacement for older read-only memory (ROM)
chips, which are used to store program code that rarely
needs to be updated, such as a computers BIOS or the
rmware of set-top boxes. Its endurance may be from as
little as 100 erase cycles for an on-chip ash memory,[8]
to a more typical 10,000 or 100,000 erase cycles, up to
1,000,000 erase cycles.[9] NOR-based ash was the basis of early ash-based removable media; CompactFlash
Example applications of both types of ash memory was originally based on it, though later cards moved to
include personal computers, PDAs, digital audio play- less expensive NAND ash.
ers, digital cameras, mobile phones, synthesizers, video NAND ash has reduced erase and write times, and regames, scientic instrumentation, industrial robotics, quires less chip area per cell, thus allowing greater storage

density and lower cost per bit than NOR ash; it also has
up to ten times the endurance of NOR ash. However, the
I/O interface of NAND ash does not provide a randomaccess external address bus. Rather, data must be read on
a block-wise basis, with typical block sizes of hundreds
to thousands of bits. This makes NAND ash unsuitable
as a drop-in replacement for program ROM, since most
microprocessors and microcontrollers required byte-level
random access. In this regard, NAND ash is similar to
other secondary data storage devices, such as hard disks
and optical media, and is thus very suitable for use in
mass-storage devices, such as memory cards. The rst
NAND-based removable media format was SmartMedia
in 1995, and many others have followed, including:
Secure Digital
Memory Stick, and xD-Picture Card.
A new generation of memory card formats, including RSMMC, miniSD and microSD, and Intelligent Stick, feature extremely small form factors. For example, the microSD card has an area of just over 1.5 cm2 , with a thickness of less than 1 mm. microSD capacities range from
64 MB to 200 GB, as of March 2015.[10]


Bit Line
Word Line
Control Gate


2.1 Floating-gate transistor

In ash memory, each memory cell resembles a standard
MOSFET, except the transistor has two gates instead of
one. On top is the control gate (CG), as in other MOS
transistors, but below this there is a oating gate (FG) insulated all around by an oxide layer. The FG is interposed
between the CG and the MOSFET channel. Because the
FG is electrically isolated by its insulating layer, electrons
placed on it are trapped until they are removed by another
application of electric eld (e.g. Applied voltage or UV as
in EPROM). Counter-intuitively, placing electrons on the
FG sets the transistor to the logical 0 state. Once the FG
is charged, the electrons in it screen (partially cancel) the
electric eld from the CG, thus, increasing the threshold
voltage (VT) of the cell. This means that a higher voltage
must be applied to the CG to make the channel conductive. In order to read a value from the transistor, an intermediate voltage between the threshold voltages (VT &
VT) is applied to the CG. If the channel conducts at this
intermediate voltage, the FG must not be charged (if it
were, we would not get conduction because the intermediate voltage is less than VT), and hence, a logical 1 is
stored in the gate. If the channel does not conduct at the
intermediate voltage, it indicates that the FG is charged,
and hence, a logical 0 is stored in the gate. The presence
of a logical 0 or 1 is sensed by determining whether
there is current owing through the transistor when the
intermediate voltage is asserted on the CG. In a multilevel cell device, which stores more than one bit per cell,
the amount of current ow is sensed (rather than simply
its presence or absence), in order to determine more precisely the level of charge on the FG.

Float Gate

2.1.1 Internal charge pumps

A ash memory cell.

Principles of operation

Flash memory stores information in an array of memory

cells made from oating-gate transistors. In traditional
single-level cell (SLC) devices, each cell stores only one
bit of information. Some newer ash memory, known as
multi-level cell (MLC) devices, including triple-level cell
(TLC) devices, can store more than one bit per cell by
choosing between multiple levels of electrical charge to
apply to the oating gates of its cells.

Despite the need for high programming and erasing voltages, virtually all ash chips today require only a single
supply voltage, and produce the high voltages using onchip charge pumps.
Over half the energy used by a 1.8 V NAND ash chip
is lost in the charge pump itself. Since boost converters are inherently more ecient than charge pumps, researchers developing low-power SSDs have proposed returning to the dual Vcc/Vpp supply voltages used on all
the early ash chips, driving the high Vpp voltage for all
ash chips in a SSD with a single shared external boost

In spacecraft and other high-radiation environments, the

The oating gate may be conductive (typically polysilicon on-chip charge pump is the rst part of the ash chip
in most kinds of ash memory) or non-conductive (as in to fail, although ash memories will continue to work at
SONOS ash memory).[11]
much higher radiation levels when in read-only mode.[20]



NAND ash

NOR ash

Erasure via tunneling

In NOR ash, each cell has one end connected directly

to ground, and the other end connected directly to a bit
line. This arrangement is called NOR ash because it
acts like a NOR gate: when one of the word lines (connected to the cells CG) is brought high, the corresponding storage transistor acts to pull the output bit line low.
NOR ash continues to be the technology of choice for
embedded applications requiring a discrete non-volatile
memory device. The low read latencies characteristic of
NOR devices allow for both direct code execution and
data storage in a single memory product.[21]






12 V

Erasing a NOR memory cell (setting it to logical 1), via quantum

Bit Line

Line 0

Line 1


Line 2

Line 3


Line 4

Line 5


an elevated on-voltage (typically >5 V) is applied to

the CG
the channel is now turned on, so electrons can ow
from the source to the drain (assuming an NMOS

the source-drain current is suciently high to cause

some high energy electrons to jump through the insulating layer onto the FG, via a process called hotelectron injection.

NOR ash memory wiring and structure on silicon

Programming via hot electron injection

2.2.2 Erasing

12 V





12 V

To erase a NOR ash cell (resetting it to the 1 state),

a large voltage of the opposite polarity is applied between the CG and source terminal, pulling the electrons
o the FG through quantum tunneling. Modern NOR
ash memory chips are divided into erase segments (often called blocks or sectors). The erase operation can be
performed only on a block-wise basis; all the cells in an
erase segment must be erased together. Programming of
NOR cells, however, generally can be performed one byte
or word at a time.

2.3 NAND ash

Programming a NOR memory cell (setting it to logical 0), via
hot-electron injection.

NAND ash also uses oating-gate transistors, but they

are connected in a way that resembles a NAND gate: several transistors are connected in series, and the bit line is
pulled low only if all word lines are pulled high (above
2.2.1 Programming
the transistors VT). These groups are then connected via
additional transistors to a NOR-style bit line array
A single-level NOR ash cell in its default state is logically
same way that single transistors are linked in NOR
equivalent to a binary 1 value, because current will ow
through the channel under application of an appropriate
voltage to the control gate, so that the bitline voltage is Compared to NOR ash, replacing single transistors with
pulled down. A NOR ash cell can be programmed, or serial-linked groups adds an extra level of addressing.
set to a binary 0 value, by the following procedure:
Whereas NOR ash might address memory by page then


2.4.1 Structure
Bit Line

Line 0

Line 1

Line 2

Line 3

Line 4

Line 5

Line 6

Bit Line

Line 7

V-NAND uses a charge trap ash geometry (pioneered

in 2002 by AMD) that stores charge on an embedded silicon nitride lm. Such a lm is more robust against point
defects and can be made thicker to hold larger numbers
of electrons. V-NAND wraps a planar charge trap cell
into a cylindrical form.[22]

An individual memory cell is made up of one planar

polysilicon layer containing a hole lled by multiple concentric vertical cylinders. The holes polysilicon surface
acts as the gate electrode. The outermost silicon dioxide
cylinder acts as the gate dielectric, enclosing a silicon nitride cylinder that stores charge, in turn enclosing a silicon
NAND ash memory wiring and structure on silicon
dioxide cylinder as the tunnel dielectric that surrounds a
central rod of conducting polysilicon which acts as the
word, NAND ash might address it by page, word and bit. conducting channel.
Bit-level addressing suits bit-serial applications (such as Memory cells in dierent vertical layers do not interfere
hard disk emulation), which access only one bit at a time. with each other, as the charges cannot move vertically
Execute-in-place applications, on the other hand, require through the silicon nitride storage medium, and the elecevery bit in a word to be accessed simultaneously. This tric elds associated with the gates are closely conned
requires word-level addressing. In any case, both bit and within each layer. The vertical collection is electrically
word addressing modes are possible with either NOR or identical to the serial-linked groups in which conventional
NAND ash.
NAND ash memory is congured.[22]

To read, rst the desired group is selected (in the same

way that a single transistor is selected from a NOR array).
Next, most of the word lines are pulled up above the VT
of a programmed bit, while one of them is pulled up to
just over the VT of an erased bit. The series group will
conduct (and pull the bit line low) if the selected bit has
not been programmed.
Despite the additional transistors, the reduction in ground
wires and bit lines allows a denser layout and greater storage capacity per chip. (The ground wires and bit lines are
actually much wider than the lines in the diagrams.) In
addition, NAND ash is typically permitted to contain a
certain number of faults (NOR ash, as is used for a BIOS
ROM, is expected to be fault-free). Manufacturers try to
maximize the amount of usable storage by shrinking the
size of the transistors.

2.4.2 Construction
Growth of a group of V-NAND cells begins with an alternating stack of conducting (doped) polysilicon layers
and insulating silicon dioxide layers.[22]
The next step is to form a cylindrical hole through these
layers. In practice, a 128 Gibit V-NAND chip with 24
layers of memory cells requires about 2.9 billion such
holes. Next the holes inner surface receives multiple
coatings, rst silicon dioxide, then silicon nitride, then a
second layer of silicon dioxide. Finally, the hole is lled
with conducting (doped) polysilicon.[22]
2.4.3 Performance

As of 2013, V-NAND ash architecture allows read and

write operations twice as fast as conventional NAND and
can last up to 10 times as long, while consuming 50 perNAND ash uses tunnel injection for writing and tunnel cent less power. They oer comparable physical bit denrelease for erasing. NAND ash memory forms the core sity using 10-nm lithography, but may be able to increase
of the removable USB storage devices known as USB bit density by up to two orders of magnitude.[22]
ash drives, as well as most memory card formats and
solid-state drives available today.

Writing and erasing

3 Limitations

Vertical NAND
3.1 Block erasure

Vertical NAND (V-NAND) memory stacks memory

cells vertically and uses a charge trap ash architecture. One limitation of ash memory is that, although it can be
The vertical layers allow larger areal bit densities without read or programmed a byte or a word at a time in a random access fashion, it can only be erased a block at a
requiring smaller individual cells.[22]


Read disturb

time. This generally sets all bits in the block to 1. Starting

with a freshly erased block, any location within that block
can be programmed. However, once a bit has been set to
0, only by erasing the entire block can it be changed back
to 1. In other words, ash memory (specically NOR
ash) oers random-access read and programming operations, but does not oer arbitrary random-access rewrite
or erase operations. A location can, however, be rewritten as long as the new values 0 bits are a superset of the
over-written values. For example, a nibble value may be
erased to 1111, then written as 1110. Successive writes
to that nibble can change it to 1010, then 0010, and nally
0000. Essentially, erasure sets all bits to 1, and programming can only clear bits to 0. File systems designed for
ash devices can make use of this capability, for example
to represent sector metadata.

routers, which are programmed only once or at most a few
times during their lifetimes.

In December 2012, Taiwanese engineers from Macronix

revealed their intention to announce at the 2012 IEEE
International Electron Devices Meeting that it has gured
out how to improve NAND ash storage read/write cycles
from 10,000 to 100 million cycles using a self-healing
process that uses a ash chip with onboard heaters that
could anneal small groups of memory cells.[25] The builtin thermal annealing replaces the usual erase cycle with
a local high temperature process that not only erases the
stored charge, but also repairs the electron-induced stress
in the chip, giving write cycles of at least 100 million.[26]
The result is a chip that can be erased and rewritten over
and over, even when it should theoretically break down.
As promising as Macronixs breakthrough could be for
Although data structures in ash memory cannot be up- the mobile industry, however, there are no plans for a
dated in completely general ways, this allows members commercial product to be released any time in the near
to be removed by marking them as invalid. This tech- future.[27]
nique may need to be modied for multi-level cell devices, where one memory cell holds more than one bit.
Common ash devices such as USB ash drives and memory cards provide only a block-level interface, or ash
translation layer (FTL), which writes to a dierent cell
each time to wear-level the device. This prevents incremental writing within a block; however, it does not help
the device from being prematurely worn out by intensive
write patterns.


Memory wear

Another limitation is that ash memory has a nite number of programerase cycles (typically written as P/E cycles). Most commercially available ash products are
guaranteed to withstand around 100,000 P/E cycles before the wear begins to deteriorate the integrity of the
storage.[23] Micron Technology and Sun Microsystems
announced an SLC NAND ash memory chip rated for
1,000,000 P/E cycles on 17 December 2008.[24]
The guaranteed cycle count may apply only to block zero
(as is the case with TSOP NAND devices), or to all blocks
(as in NOR). This eect is partially oset in some chip
rmware or le system drivers by counting the writes and
dynamically remapping blocks in order to spread write
operations between sectors; this technique is called wear
leveling. Another approach is to perform write verication and remapping to spare sectors in case of write failure, a technique called bad block management (BBM).
For portable consumer devices, these wearout management techniques typically extend the life of the ash
memory beyond the life of the device itself, and some
data loss may be acceptable in these applications. For
high reliability data storage, however, it is not advisable
to use ash memory that would have to go through a large
number of programming cycles. This limitation is meaningless for 'read-only' applications such as thin clients and

3.3 Read disturb

The method used to read NAND ash memory can cause
nearby cells in the same memory block to change over
time (become programmed). This is known as read disturb. The threshold number of reads is generally in the
hundreds of thousands of reads between intervening erase
operations. If reading continually from one cell, that cell
will not fail but rather one of the surrounding cells on a
subsequent read. To avoid the read disturb problem the
ash controller will typically count the total number of
reads to a block since the last erase. When the count
exceeds a target limit, the aected block is copied over
to a new block, erased, then released to the block pool.
The original block is as good as new after the erase. If
the ash controller does not intervene in time, however,
a read disturb error will occur with possible data loss
if the errors are too numerous to correct with an errorcorrecting code.[28][29]

3.4 X-ray eects

Most ash ICs come in ball grid array (BGA) packages,
and even the ones that do not are often mounted on a
PCB next to other BGA packages. After PCB Assembly, boards with BGA packages are often X-rayed to see
if the balls are making proper connections to the proper
pad, or if the BGA needs rework. These X-rays can erase
programmed bits in a ash chip (convert programmed 0
bits into erased 1 bits). Erased bits (1 bits) are not affected by X rays.[30][31]


Low-level access

The low-level interface to ash memory chips diers

from those of other memory types such as DRAM, ROM,
and EEPROM, which support bit-alterability (both zero
to one and one to zero) and random access via externally
accessible address buses.

4.2 NAND memories

NAND ash architecture was introduced by Toshiba in
1989.[33] These memories are accessed much like block
devices, such as hard disks. Each block consists of a number of pages. The pages are typically 512[34] or 2,048 or
4,096 bytes in size. Associated with each page are a few
bytes (typically 1/32 of the data size) that can be used for
storage of an error correcting code (ECC) checksum.

NOR memory has an external address bus for reading and

programming. For NOR memory, reading and program- Typical block sizes include:
ming are random-access, and unlocking and erasing are
block-wise. For NAND memory, reading and program 32 pages of 512+16 bytes each for a block size of
ming are page-wise, and unlocking and erasing are block16 KiB
64 pages of 2,048+64 bytes each for a block size of
128 KiB[35]
64 pages of 4,096+128 bytes each for a block size
of 256 KiB[36]


NOR memories

Reading from NOR ash is similar to reading from

random-access memory, provided the address and data
bus are mapped correctly. Because of this, most microprocessors can use NOR ash memory as execute in place
(XIP) memory, meaning that programs stored in NOR
ash can be executed directly from the NOR ash without
needing to be copied into RAM rst. NOR ash may be
programmed in a random-access manner similar to reading. Programming changes bits from a logical one to a
zero. Bits that are already zero are left unchanged. Erasure must happen a block at a time, and resets all the bits
in the erased block back to one. Typical block sizes are
64, 128, or 256 KiB.

128 pages of 4,096+128 bytes each for a block size

of 512 KiB.
While reading and programming is performed on a page
basis, erasure can only be performed on a block basis.[37]

NAND devices also require bad block management by

the device driver software, or by a separate controller
chip. SD cards, for example, include controller circuitry
to perform bad block management and wear leveling.
When a logical block is accessed by high-level software, it
is mapped to a physical block by the device driver or controller. A number of blocks on the ash chip may be set
aside for storing mapping tables to deal with bad blocks,
or the system may simply check each block at power-up
to create a bad block map in RAM. The overall memory
capacity gradually shrinks as more blocks are marked as
Bad block management is a relatively new feature in NOR bad.
chips. In older NOR devices not supporting bad block NAND relies on ECC to compensate for bits that may
management, the software or device driver controlling the spontaneously fail during normal device operation. A
memory chip must correct for blocks that wear out, or the typical ECC will correct a one-bit error in each 2048 bits
device will cease to work reliably.
(256 bytes) using 22 bits of ECC code, or a one-bit error in each 4096 bits (512 bytes) using 24 bits of ECC
code.[38] If the ECC cannot correct the error during read,
it may still detect the error. When doing erase or program operations, the device can detect blocks that fail to
program or erase and mark them bad. The data is then
written to a dierent, good block, and the bad block map
Besides its use as random-access ROM, NOR ash can is updated.
also be used as a storage device, by taking advantage of Hamming codes are the most commonly used ECC for
random-access programming. Some devices oer read- SLC NAND ash. Reed-Solomon codes and Bosewhile-write functionality so that code continues to exe- Chaudhuri-Hocquenghem codes are commonly used
cute even while a program or erase operation is occur- ECC for MLC NAND ash. Some MLC NAND ash
ring in the background. For sequential data writes, NOR chips internally generate the appropriate BCH error corash chips typically have slow write speeds, compared rection codes. [32]
with NAND ash.
Most NAND devices are shipped from the factory with
The specic commands used to lock, unlock, program,
or erase NOR memories dier for each manufacturer.
To avoid needing unique driver software for every device
made, special Common Flash Memory Interface (CFI)
commands allow the device to identify itself and its critical operating parameters.

Typical NOR ash does not need an error correcting some bad blocks. These are typically marked according
to a specied bad block marking strategy. By allowing

some bad blocks, the manufacturers achieve far higher interfaces for nonvolatile memory subsystems, including
yields than would be possible if all blocks had to be ver- the ash cache device connected to the PCI Express
ied good. This signicantly reduces NAND ash costs bus.
and only slightly decreases the storage capacity of the
When executing software from NAND memories, virtual 5 Distinction between NOR and
memory strategies are often used: memory contents must
NAND ash
rst be paged or copied into memory-mapped RAM and
executed there (leading to the common combination of
NOR and NAND ash dier in two important ways:
NAND + RAM). A memory management unit (MMU)
in the system is helpful, but this can also be accomplished
the connections of the individual memory cells are
with overlays. For this reason, some systems will use
a combination of NOR and NAND memories, where a
smaller NOR memory is used as software ROM and a
the interface provided for reading and writing the
larger NAND memory is partitioned with a le system
memory is dierent (NOR allows random-access for
for use as a non-volatile data storage area.
reading, NAND allows only page access)
NAND sacrices the random-access and execute-inplace advantages of NOR. NAND is best suited to sys- These two are linked by the design choices made in the
tems requiring high capacity data storage. It oers higher development of NAND ash. A goal of NAND ash dedensities, larger capacities, and lower cost. It has faster velopment was to reduce the chip area required to impleerases, sequential writes, and sequential reads.
ment a given capacity of ash memory, and thereby to
reduce cost per bit and increase maximum chip capacity
so that ash memory could compete with magnetic stor4.3 Standardization
age devices like hard disks.
NOR and NAND ash get their names from the structure of the interconnections between memory cells.[43]
In NOR ash, cells are connected in parallel to the bit
lines, allowing cells to be read and programmed individually. The parallel connection of cells resembles the parallel connection of transistors in a CMOS NOR gate. In
NAND ash, cells are connected in series, resembling a
NAND gate. The series connections consume less space
a standard physical interface (pinout) for NAND than parallel ones, reducing the cost of NAND ash. It
ash in TSOP48, WSOP-48, LGA52, and does not, by itself, prevent NAND cells from being read
BGA63 packages
and programmed individually.

A group called the Open NAND Flash Interface Working

Group (ONFI) has developed a standardized low-level interface for NAND ash chips. This allows interoperability between conforming NAND devices from dierent
vendors. The ONFI specication version 1.0[39] was released on 28 December 2006. It species:

a standard command set for reading, writing, and Each NOR ash cell is larger than a NAND ash cell
erasing NAND ash chips
10 F2 vs 4 F2 even when using exactly the same
semiconductor device fabrication and so each transistor,
a mechanism for self-identication (comparable to contact, etc. is exactly the same sizebecause NOR ash
the serial presence detection feature of SDRAM cells require a separate metal contact for each cell.[44]
memory modules)
When NOR ash was developed, it was envisioned as a
more economical and conveniently rewritable ROM than
The ONFI group is supported by major NAND ash contemporary EPROM and EEPROM memories. Thus
manufacturers, including Hynix, Intel, Micron Technol- random-access reading circuitry was necessary. Howogy, and Numonyx, as well as by major manufacturers of ever, it was expected that NOR ash ROM would be read
devices incorporating NAND ash chips.[40]
much more often than written, so the write circuitry inOne major ash device manufacturer, Toshiba, has cho- cluded was fairly slow and could only erase in a blocksen to use an interface of their own design known as Tog- wise fashion. On the other hand, applications that use
gle Mode (and now Toggle V2.0). This interface isn't ash as a replacement for disk drives do not require worddirectly, pin for pin compatible with the ONFI speci- level write address, which would only add to the complexcation. The result is a product designed for one vendors ity and cost unnecessarily.
devices, can't use other vendors devices.[41]
Because of the series connection and removal of wordA group of vendors, including Intel, Dell, and Microsoft,
formed a Non-Volatile Memory Host Controller Interface
(NVMHCI) Working Group.[42] The goal of the group is
to provide standard software and hardware programming

line contacts, a large grid of NAND ash memory cells

will occupy perhaps only 60% of the area of equivalent
NOR cells[45] (assuming the same CMOS process resolution, for example, 130 nm, 90 nm, or 65 nm). NAND

ashs designers realized that the area of a NAND chip,

and thus the cost, could be further reduced by removing
the external address and data bus circuitry. Instead, external devices could communicate with NAND ash via
sequential-accessed command and data registers, which
would internally retrieve and output the necessary data.
This design choice made random-access of NAND ash
memory impossible, but the goal of NAND ash was to
replace mechanical hard disks, not to replace ROMs.


Because of the particular characteristics of ash memory,

it is best used with either a controller to perform wear
leveling and error correction or specically designed ash
le systems, which spread writes over the media and deal
with the long erase times of NOR ash blocks. The basic
concept behind ash le systems is the following: when
the ash store is to be updated, the le system will write
a new copy of the changed data to a fresh block, remap
the le pointers, then erase the old block later when it has

In practice, ash le systems are only used for memory

technology devices (MTDs), which are embedded ash
memories that do not have a controller. Removable ash
The write endurance of SLC oating-gate NOR ash is
memory cards and USB ash drives have built-in contypically equal to or greater than that of NAND ash,
trollers to perform wear leveling and error correction so
while MLC NOR and NAND ash have similar enuse of a specic ash le system does not add any benet.
durance capabilities. Example Endurance cycle ratings
listed in datasheets for NAND and NOR ash are provided.


Write endurance

7 Capacity

SLC NAND ash is typically rated at about

chips are often arrayed to achieve higher
100,000 erases per block (Samsung OneNAND Multiple [48]
for use in consumer electronic devices such
as multimedia players or GPSs. The capacity of ash
MLC NAND ash is typically rated at about 5000 chips generally follows Moores Law because they are
10000 erases per block for medium-capacity appli- manufactured with many of the same integrated circuits
cations (Samsung K9G8G08U0M) and 10003000 techniques and equipment.
erases per block for high-capacity applications
Consumer ash storage devices typically are advertised
TLC NAND ash is typically rated at about 1000
erases per block (Samsung 840)
SLC oating-gate NOR ash has typical endurance
rating of 100,000 to 1,000,000 erases per block
(100,000 for Numonyx M58BW; 1,000,000 for
Spansion S29CD016J)

with usable sizes expressed as a small integer power of

two (2, 4, 8, etc.) and a designation of megabytes (MB) or
gigabytes (GB); e.g., 512 MB, 8 GB. This includes SSDs
marketed as hard drive replacements, in accordance with
traditional hard drives, which use decimal prexes.[49]
Thus, an SSD marked as 64 GB" is at least 64 1,0003
bytes (64 GB). Most users will have slightly less capacity
than this available for their les, due to the space taken
by le system metadata.

MLC oating-gate NOR ash has typical endurance

rating of 100,000 erases per block (Numonyx J3
The ash memory chips inside them are sized in strict biash)
nary multiples, but the actual total capacity of the chips is
not usable at the drive interface. It is considerably larger
However, by applying certain algorithms and design than the advertised capacity in order to allow for distribuparadigms such as wear leveling and memory over- tion of writes (wear leveling), for sparing, for error corprovisioning, the endurance of a storage system can be rection codes, and for other metadata needed by the detuned to serve specic requirements.[46]
vices internal rmware.
Computation of NAND ash memory endurance is a In 2005, Toshiba and SanDisk developed a NAND ash
challenging subject that depends on SLC/MLC/TLC chip capable of storing 1 GB of data using multi-level
memory type as well as use pattern. In order to com- cell (MLC) technology, capable of storing two bits of
pute the longevity of the NAND ash, one must use data per cell. In September 2005, Samsung Electronics
the size of the memory chip, the type of memory (e.g. announced that it had developed the worlds rst 2 GB
SLC/MLC/TLC), and use pattern. The life of the ash chip.[50]
can last from a few days to several hundred years.[47]
In March 2006, Samsung announced ash hard drives
with a capacity of 4 GB, essentially the same order of
magnitude as smaller laptop hard drives, and in Septem6 Flash le systems
ber 2006, Samsung announced an 8 GB chip produced using a 40 nm manufacturing process.[51] In January 2008,
Main article: Flash le system
SanDisk announced availability of their 16 GB MicroSDHC and 32 GB SDHC Plus cards.[52][53]


Flash memory as a replacement for hard drives

More recent ash drives (as of 2012) have much greater There are two major SPI ash types. The rst type is
capacities, holding 64, 128, and 256 GB.[54]
characterized by small pages and one or more internal
A joint development at Intel and Micron will allow the SRAM page buers allowing a complete page to be read
production of 32 layer 3.5 terabyte (TB) NAND ash to the buer, partially modied, and then written back
sticks and 10 TB standard-sized SSDs. The device in- (for example, the Atmel AT45 DataFlash or the Micron
cludes 5 packages of 16 x 48 GB TLC dies, using a oat- Technology Page Erase NOR Flash). The second type
has larger sectors. The smallest sectors typically found
ing gate cell design.[55]
in an SPI ash are 4 kB, but they can be as large as 64
Flash chips continue to be manufactured with capacities kB. Since the SPI ash lacks an internal SRAM buer,
under or around 1 MB, e.g., for BIOS-ROMs and embed- the complete page must be read out and modied before
ded applications.
being written back, making it slow to manage. SPI ash
is cheaper than DataFlash and is therefore a good choice
when the application is code shadowing.

Transfer rates

The two types are not easily exchangeable, since they do

not have the same pinout, and the command sets are inNAND ash memory cards are much faster at reading compatible.
than writing.
Performance also depends on the quality of memory con9.1.1 Firmware storage
trollers. Even when the only change to manufacturing is
die-shrink, the absence of an appropriate controller can
With the increasing speed of modern CPUs, parallel ash
result in degraded speeds.[56]
devices are often much slower than the memory bus of
the computer they are connected to. Conversely, modern SRAM oers access times below 10 ns, while DDR2
9 Applications
SDRAM oers access times below 20 ns. Because of
this, it is often desirable to shadow code stored in ash
into RAM; that is, the code is copied from ash into RAM
9.1 Serial ash
before execution, so that the CPU may access it at full
Serial ash is a small, low-power ash memory that uses a speed. Device rmware may be stored in a serial ash deserial interface, typically Serial Peripheral Interface Bus vice, and then copied into SDRAM or SRAM when the
Using an external serial ash
(SPI), for sequential data access. When incorporated into device is powered-up.
an embedded system, serial ash requires fewer wires on device rather than on-chip ash removes the need for
the PCB than parallel ash memories, since it transmits signicant process compromise (a process that is good
and receives data one bit at a time. This may permit a for high-speed logic is generally not good for ash and
reduction in board space, power consumption, and total vice versa). Once it is decided to read the rmware in
as one big block it is common to add compression to alsystem cost.
low a smaller ash chip to be used. Typical applications
There are several reasons why a serial device, with fewer for serial ash include storing rmware for hard drives,
external pins than a parallel device, can signicantly re- Ethernet controllers, DSL modems, wireless network deduce overall cost:
vices, etc.
Many ASICs are pad-limited, meaning that the size
of the die is constrained by the number of wire 9.2 Flash memory as a replacement for
bond pads, rather than the complexity and number
hard drives
of gates used for the device logic. Eliminating bond
pads thus permits a more compact integrated circuit, Main article: Solid-state drive
on a smaller die; this increases the number of dies
that may be fabricated on a wafer, and thus reduces
One more recent application for ash memory is as a rethe cost per die.
placement for hard disks. Flash memory does not have
Reducing the number of external pins also reduces the mechanical limitations and latencies of hard drives,
assembly and packaging costs. A serial device may so a solid-state drive (SSD) is attractive when considering
be packaged in a smaller and simpler package than speed, noise, power consumption, and reliability. Flash
a parallel device.
drives are gaining traction as mobile device secondary
storage devices; they are also used as substitutes for hard
Smaller and lower pin-count packages occupy less drives in high-performance desktop computers and some
PCB area.
servers with RAID and SAN architectures.
Lower pin-count devices simplify PCB routing.

There remain some aspects of ash-based SSDs that




make them unattractive. The cost per gigabyte of ash

memory remains signicantly higher than that of hard
disks.[58] Also ash memory has a nite number of P/E
cycles, but this seems to be currently under control since
warranties on ash-based SSDs are approaching those of
current hard drives.[59]
For relational databases or other systems that require
ACID transactions, even a modest amount of ash storage
can oer vast speedups over arrays of disk drives.[60][61]
In June 2006, Samsung Electronics released the rst
ash-memory based PCs, the Q1-SSD and Q30-SSD, The aggressive trend of the shrinking process design rule or techboth of which used 32 GB SSDs, and were at least ini- nology node in NAND ash memory technology eectively accelerates Moores Law.
tially available only in South Korea.[62]
A solid-state drive was oered as an option with the rst
Macbook Air introduced in 2008, and from 2010 on- 11 Flash scalability
wards, all Macbook Air laptops shipped with an SSD.
Starting in late 2011, as part of Intel's Ultrabook initia- Due to its relatively simple structure and high demand for
tive, an increasing number of ultra thin laptops are being higher capacity, NAND ash memory is the most aggresshipped with SSDs standard.
sively scaled technology among electronic devices. The
There are also hybrid techniques such as hybrid drive and heavy competition among the top few manufacturers only
in shrinking the design rule or
ReadyBoost that attempt to combine the advantages of adds to the aggressiveness[29]
While the expected shrink
both technologies, using ash as a high-speed non-volatile
three years per original
cache for les on the disk that are often referenced, but
been accelerated
rarely modied, such as application and operating system
two every two
executable les.
As the feature size of ash memory cells reaches the
minimum limit, further ash density increases will be
driven by greater levels of MLC, possibly 3-D stacking
9.3 Flash memory as RAM
of transistors, and improvements to the manufacturing
As of 2012, there are attempts to use ash memory as the process. The decrease in endurance and increase in uncorrectable bit error rates that accompany feature size
main computer memory, DRAM.[63]
shrinking can be compensated by improved error correction mechanisms.[68] Even with these advances, it may
be impossible to economically scale ash to smaller and
smaller dimensions as the number of electron holding ca9.4 Archival or long-term storage
pacity reduces. Many promising new technologies (such
as FeRAM, MRAM, PMC, PCM, ReRAM, and others)
It is unclear how long ash memory will persist under are under investigation and development as possible more
archival conditionsi.e., benign temperature and humid- scalable replacements for ash.[69]
ity with infrequent access with or without prophylactic
rewrite. Anecdotal evidence suggests that the technology
is reasonably robust on the scale of years.

12 See also

List of ash le systems



microSDXC (up to 2 TB).

Secure USB drive

One source states that, in 2008, the ash memory industry includes about US$9.1 billion in production and sales.
Other sources put the ash memory market at a size of
more than US$20 billion in 2006, accounting for more
than eight percent of the overall semiconductor market
and more than 34 percent of the total semiconductor
memory market.[64] In 2012, the market was estimated
at $26.8 billion.[65]

Open NAND Flash Interface Working Group

Write amplication

13 References
[1] A Flash Storage Technical and Economic Primer. ash-

11 30 March 2015.

[2] Owners of QM2 seabed camera found. BBC News. 11
February 2010.
[3] Fulford, Benjamin (24 June 2002).
Forbes. Retrieved 18 March 2008.

Unsung hero.

[4] US 4531203 Fujio Masuoka

[5] NAND Flash Memory: 25 Years of Invention, Development - Data Storage - News & Reviews -
[6] Masuoka, F.; Momodomi, M.; Iwata, Y.; Shirota, R.
(1987). New ultra high density EPROM and ash EEPROM with NAND structure cell. Electron Devices Meeting, 1987 International. IEEE. Retrieved 4 January 2013.
[7] Tal, Arie (February 2002). NAND vs. NOR ash technology: The designer should weigh the options when using
ash memory. Retrieved 31 July 2010.
[8] H8S/2357 Group, H8S/2357F-ZTATTM, H8S/2398FZTATTM Hardware Manual, Section 19.6.1 (PDF). Renesas. October 2004. Retrieved 23 January 2012. The
ash memory can be reprogrammed up to 100 times.
[9] AMD DL160 and DL320 Series Flash: New Densities,
New Features (PDF). AMD. 2003-07-00. Retrieved 13
November 2014. The devices oer single-power-supply
operation (2.7 V to 3.6 V), sector architecture, Embedded Algorithms, high performance, and a 1,000,000 program/erase cycle endurance guarantee.
[10] SanDisk Unveils the Worlds Highest Capacity microSD Card (200GB)". Sandisk. 1 March 2015. Retrieved 1 April 2015.
[11] Basinger, Matt (18 January 2007), PSoC Designer Device
Selection Guide (PDF), AN2209, The PSoC ... utilizes a
unique Flash process: SONOS
[12] Yasufuku, Tadashi; Ishida, Koichi; Miyamoto, Shinji;
Nakai, Hiroto; Takamiya, Makoto; Sakurai, Takayasu;
Takeuchi, Ken (2009), Inductor design of 20-V boost converter for low power 3D solid state drive with NAND ash
memories, pp. 8792 (abstract).
[13] Micheloni, Rino; Marelli, Alessia; Eshghi, Kam (2012),
Inside Solid State Drives (SSDs)
[14] Micheloni, Rino; Crippa, Luca (2010), Inside NAND
Flash Memories In particular, pp 515-536: K. Takeuchi.
Low power 3D-integrated SSD
[15] Mozel, Tracey (2009), CMOSET Fall 2009 Circuits and
Memories Track Presentation Slides
[16] Tadashi Yasufuku et al., Inductor and TSV Design of 20V Boost Converter for Low Power 3D Solid State Drive
with NAND Flash Memories. 2010.
[17] Hatanaka, T. and Takeuchi, K. 4-times faster rising
VPASS (10V), 15% lower power VPGM (20V), wide output voltage range voltage generator system for 4-times
faster 3D-integrated solid-state drives. 2011.

[18] Takeuchi, K., Low power 3D-integrated Solid-State

Drive (SSD) with adaptive voltage generator. 2010.
[19] Ishida, K. et al., 1.8 V Low-Transient-Energy Adaptive
Program-Voltage Generator Based on Boost Converter for
3D-Integrated NAND Flash SSD. 2011.
[20] A. H. Johnston, Space Radiation Eects in Advanced
Flash Memories. NASA Electronic Parts and Packaging Program (NEPP). 2001. "... internal transistors used
for the charge pump and erase/write control have much
thicker oxides because of the requirement for high voltage. This causes ash devices to be considerably more
sensitive to total dose damage compared to other ULSI
technologies. It also implies that write and erase functions
will be the rst parameters to fail from total dose. ... Flash
memories will work at much higher radiation levels in the
read mode. ... The charge pumps that are required to generate the high voltage for erasing and writing are usually
the most sensitive circuit functions, usually failing below
10 krad(SI).
[21] Zitlaw, Cli. The Future of NOR Flash Memory. Memory Designline. UBM Media. Retrieved 3 May 2011.
[22] Samsung moves into mass production of 3D ash memory. Retrieved 2013-08-27.
[23] Jonathan Thatcher, Fusion-io; Tom Coughlin, Coughlin
Associates; Jim Handy, Objective-Analysis; Neal Ekker,
Texas Memory Systems (April 2009). NAND Flash
Solid State Storage for the Enterprise, An In-depth Look
at Reliability (PDF). Solid State Storage Initiative (SSSI)
of the Storage Network Industry Association (SNIA). Retrieved 6 December 2011.
[24] Micron Collaborates with Sun Microsystems to Extend
Lifespan of Flash-Based Storage, Achieves One Million
Write Cycles (Press release). Micron Technology, Inc.
17 December 2008.
[25] Taiwan engineers defeat limits of ash memory.
[26] Flash memory made immortal by ery heat.
[27] Flash memory breakthrough could lead to even more reliable data storage.
[28] TN-29-17 NAND Flash Design and Use Considerations
Introduction (PDF). Micron. April 2010. Retrieved 29
July 2011.
[29] Kawamatus, Tatsuya. TECHNOLOGY FOR MANAGING NAND FLASH (PDF). Hagiwara sys-com co.,
LTD. Retrieved 1 August 2011.
[30] Richard Blish. Dose Minimization During X-ray Inspection of Surface-Mounted Flash ICs. p. 1.
[31] Richard Blish. Impact of X-Ray Inspection on Spansion
Flash Memory.
[32] Spansion. What Types of ECC Should Be Used on Flash
Memory?". 2011.





MONOLITHIC NAND. 2002-04-23. Retrieved 2013-08-27.

[52] SanDisk Media Center.

[34] Kim, Jesung; Kim, John Min; Noh, Sam H.; Min, Sang
Lyul; Cho, Yookun (May 2002). A Space-Ecient Flash
Translation Layer for CompactFlash Systems (PDF).
Proceedings of the IEEE 48 (2). pp. 366375. Retrieved

kingston-outs-the-first-256gb-flash-drive/ 20 July 2009,
Kingston DataTraveler 300 is 256 GB.

[35] TN-29-07: Small-Block vs. Large-Block NAND ash

Devices Explains 512+16 and 2048+64-byte blocks

[55] Borghino, Dario (March 31, 2015). 3D ash technology

moves forward with 10 TB SSDs and the rst 48-layer
memory cells. Gizmag. Retrieved March 2015.

[36] AN10860 LPC313x NAND ash data and bad block

management Explains 4096+128-byte blocks.
[37] Thatcher, Jonathan (18 August 2009). NAND Flash
Solid State Storage Performance and Capability an Indepth Look (PDF). SNIA. Retrieved 2012-08-28.
[38] Samsung ECC algorithm (PDF). Samsung. June 2008.
Retrieved 15 August 2008.
[39] Open NAND Flash Interface Specication (PDF).
Open NAND Flash Interface. 28 December 2006. Retrieved 31 July 2010.
[40] A list of ONFi members is available at
[41] Toshiba Introduces Double Data Rate Toggle Mode
NAND In MLC And SLC Congurations.
[42] Dell, Intel And Microsoft Join Forces To Increase Adoption Of NAND-Based Flash Memory In PC Platforms.
REDMOND, Wash: Microsoft. 30 May 2007. Retrieved
12 August 2014.

[53] SanDisk Media Center.

[56] DailyTech - Samsung Conrms 32nm Flash Problems,

Working on New SSD Controller.
[57] Many serial ash devices implement a bulk read mode and
incorporate an internal address counter, so that it is trivial
to congure them to transfer their entire contents to RAM
on power-up. When clocked at 50 MHz, for example, a
serial ash could transfer a 64 Mbit rmware image in less
than two seconds.
[58] Lyth0s (17 March 2011). SSD vs. HDD. Retrieved 11 July 2011.
[59] Flash Solid State Disks Inferior Technology or Closet
Superstar?". STORAGEsearch. Retrieved 30 November
[60] Vadim Tkachenko. Intel SSD 910 vs HDD RAID in
tpcc-mysql benchmark. MySQL Performance Blog.
[61] Matsunobu, Yoshinori. SSD Deployment Strategies for
MySQL. Sun Microsystems, 15 April 2010.

[43] See pages 57 of Toshibas NAND Applications Design

Guide under External links.

[62] Samsung Electronics Launches the Worlds First PCs

with NAND Flash-based Solid State Disk. Press Release.
Samsung. 24 May 2006. Retrieved 30 November 2008.

[44] NAND Flash 101: An Introduction to NAND Flash and

How to Design It In to Your Next Product (PDF), Micron,
pp. 23, TN-29-19

[63] Douglas Perry (2012) Princeton: Replacing RAM with

Flash Can Save Massive Power.

[45] Pavan, Paolo; Bez, Roberto; Olivo, Piero; Zononi, Enrico

(1997). Flash Memory Cells An Overview (PDF).
Proceedings of the IEEE 85 (8) (August 1997). pp. 1248
1271. doi:10.1109/5.622505. Retrieved 15 August 2008.
[46] NAND Evolution and its Eects on Solid State Drive
Useable Life (PDF). Western Digital. 2009. Retrieved
22 April 2012.
[48] Flash vs DRAM follow-up: chip stacking. The Daily
Circuit. 22 April 2012. Retrieved 22 April 2012.
[50] Shilov, Anton (12 September 2005). Samsung Unveils
2GB Flash Memory Chip. X-bit labs. Retrieved 30
November 2008.
[51] Gruener, Wolfgang (11 September 2006). Samsung announces 40 nm Flash, predicts 20 nm devices. TG Daily.
Retrieved 30 November 2008.

[64] Yinug, Christopher Falan (July 2007). The Rise of the

Flash Memory Market: Its Impact on Firm Behavior and
Global Semiconductor Trade Patterns (PDF). Journal of
International Commerce and Economics. Archived from
the original (PDF) on 29 May 2008. Retrieved 19 April
[65] NAND memory market rockets, April 17, 2013, Nermin
Hajdarbegovic, TG Daily, retrieved at 18 April 2013
[66] Technology Roadmap for NAND Flash Memory.
techinsights. April 2013. Retrieved 9 January 2015.
[67] Technology Roadmap for NAND Flash Memory.
techinsights. April 2014. Retrieved 9 January 2015.
[68] Lal Shimpi, Anand (2 December 2010). Microns ClearNAND: 25nm + ECC, Combats Increasing Error Rates.
Anandtech. Retrieved 2 December 2010.
[69] Kim, Kinam; Koh, Gwan-Hyeob (16 May 2004). Future
Memory Technology including Emerging New Memories
(PDF). Serbia and Montenegro: Proceedings of the 24th
International Conference on Microelectronics. pp. 377
384. Retrieved 2008-08-15.



External links

New Pulse Measurement System For Semiconductor Device Characterization

Semiconductor Characterization System has diverse
NAND Flash Applications Design Guide by
Toshiba, April 2003 v. 1.0
Understanding and selecting higher performance
NAND architectures
How ash storage works presentation by David
Woodhouse from Intel
Flash endurance testing





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Flash memory Source: Contributors: Damian Yerrick, AxelBoldt, Perry

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