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Cedar Park TX, 78613

Mob: (281) 948-9997


EDA Tools & Simulators
VCS, Verdi, DVE, Cadence Virtuoso Layout Schematic & Analog Mixed Signal suite,
Encounter RTL Compiler, HSpice, Xilinx ISE.
Assembly, C/C++, Perl, Shell, Make
Verilog, VHDL
Computer Software & OS
Linux, Windows
Version Control Systems
Git, Clearcase
Six Sigma Tools
Lean, 5S, Pareto, FMEA, Cause & Effect, Root Cause & Fish Bone Analysis.

MS Electrical Engineering, The University of Texas at San Antonio
B.E Electronics, Mehran University of Engineering & Technology, Pakistan.
Electronics Department.

Aug 2011- May 2013

Mar 2009

84.38%, 5th Position in


Design Automation | Design Verification Engineer - Intel Corp, Austin TX

Graduate Technical Intern - Intel Corp, Austin TX

Summer Internship-Data Communication & Control Pvt. Ltd, Pakistan

June 2012- July 2012

Modeling and Simulation of a high tech IT City to be made in Karachi, Pakistan by Government of Sindh. The Urban Design
simulator used was Any Logic Software and back end coding was done in Java.
Modeled the different parameters of the IT City with respect to Utilities, Employment, Demographics and Transportation. The
software calculates parameters based on inputs provided and simulates the values into future, resulting from city expansion and
business growth.
Utilities model includes entire Electricity, Gas and Sewage consumption parameters of the IT City. Alternate Energy sources
such as Solar power are also incorporated. Employment and Demographics model takes inputs such as the number, type, nature
and Floor Area Ratio (FAR) of buildings in the IT city and returns the potential number of Employment opportunities created.
Transportation model includes simulation of traffic flow within and from outside the city, congestion control, alternate routes,
collisions and other scenarios.

Instruments & Control Systems Engg- Engro Fertilizers Limited, Pakistan

4 Sep 2012 - 18 Dec 2012

Part of Post-Si group developing test and automation software and debugging of Intels ATOM based SoCs.

6 June 2013- Present

Working in Front End Design Automation (CAD) group supporting tools, flow, methodology and functional verification issues
for Intel Mobile SoCs and ATOM Core.
Owner for functional verification tools including Synopsys VCS, Verdi, DVE, Coverage. Debug simulation failures and tool
bugs during full chip and IP level testing and integration, carry out version migrations, provide continuous support to RTL and
Validation teams on simulation and tool bugs and test new technologies for compile and run time improvement i.e partition
compile, precompiled IP.
Get timing feedback and incorporate necessary changes in RTL.
Emulation model bring up tends to be a time consuming process in project lifetime and exposes new bugs in the RTL which are
undiscovered at simulation time. I solve this by trailblazing and introducing new technology into the project called Congruence
, at simulation time, which makes the RTL model behave as if it were running on emulator and catches emulation bugs early on
in the project lifecycle , saving months of time and $$$.
Led Front End RTL Model migration from Red Hat to SLES11 machines for Intel Mobile SoC project.
In depth knowledge of x86 processor.
Experience in functional verification and verification methodologies i.e OVM

Aug 2009-Aug 2010

Ammonia, Urea and Utilities Plant

Worked on Control Systems e.g. Experion, TDC 3000; Turbine C.S i.e. Mark V; Wood Words 505 Speed Control System;
Bailey C.S.
Excellent knowledge of Field Instruments like Flow, Pressure, Level and Temperature Transmitters, Pipelines, Control Valves,
Systems and circuits. Scheduling Preventive and Corrective Maintenance plans of Instruments.
Maintenance and Safety of heavy machines i.e. Compressors, Boilers, Furnace, and Turbines etc.
Reviewing and updating Engineering Drawings.
PLC Programming in RS Logix and communication to Remote Terminals via Modbus.
Perform root cause analysis upon malfunction of heavy equipment e.g. Synthesis and Refrigeration Compressors.

Carried out Software and Hardware modification in Reverse Osmosis Plant.

Project Management: Planning and supervising all activities related to Instrument Installation and Cabling.
Follow-ups and Co-ordination with other interfaces to ensure project deadlines, QA/QC and Safety of operation.
Computer Architecture, Superscaler Microprocessor, VLSI Design, Low power VLSI, Low Power FPGAs, Analog IC Design,
Digital Signal Processing, Advance Sensor Design, Neural Network and Fuzzy Logic, Digital Logic Design.

Implementation of Memory Management in IA 32

Implemented Virtual Memory using 32 bit IA in OS. Used Bochs as hardware emulator.

Implemented paging structures i.e: page Directory and page table for virtual to physical address translation, tested its
functionality using a test stub, illustrated sequence of steps occurring on a page fault.

Design, Synthesis, Verification and Layout of a 16 bit CLA adder and Ripple Carry Adder
Designed a 16 bit Carry Look Ahead Adder and a 16 bit Ripple Carry Adder in Verilog HDL and simulated in Xilinx ISE.
Designed a test bench with random pattern generator to generate stimulus to verify the design.
Synthesized the code to generate the netlist using Cadence RTL Compiler.
Generated Schematic and GDS2 Layout of the design using Cadence Encounter tool.

Designed a high gain CMOS Operational Amplifier using Cadence Virtuoso tool
Obtained a differential mode Voltage gain of 95.6dB.
Implemented the design in two stages: The first stage was an active load differential Amplifier, the second stage was a
Common Source stage.
Biasing was done using Current Mirror Circuit.

Designed a Fully Differential Amplifier with a Common Mode Feedback Circuit

Obtained a Differential Mode gain of 96.5dB.
Differential Mode Phase Margin was 45 degrees.
Stability was provided using Common Mode Feedback Circuit.

Designed a 32x32 bit Multiplier in HSpice and Verilog HDL

Designed the 32 bit Multiplier using two Approaches: Cascaded and Pipelined.
Evaluated the circuit at 130nm, 90nm, 65nm, 40nm technology using TSMC High Vt, Regular Vt and Low Vt Libraries.
Evaluated the Delay and Power at each technology using RTL Compiler.
Optimized the design for Performance and Power.

Low Power FPGA

Designed a Multiplier Circuit in FPGAs using Xilinx Spartan 6 FPGA module in TSMC 65nm library.
Implemented Clock Gating to reduce Power. Obtained a 25% reduction in Power as compared to traditional Spartan 6 FPGA.
Did an Independent study on Low Power FPGAs and their power optimization techniques.

Analog IC Design: Designed numerous Analog circuits including Operational Amplifier, High Gain Differential Op
Amp, Inverting Amp, Feedback Amplifier, Cascade Amp and Two Stage Amplifier using Cadence Simulator.

Intelligent ECG Recognition System using Neural Network: Undergrad Senior Project. Trained Artificial Neural
Network models to distinguish between normal and diseased ECG Patterns. Employed Signal Processing, Image
Recognition, Noise Filtering, Base line wandering and ANN Learning Algorithms. The simulation tool was MATLAB.


6 recognitions at Intel from project team and leadership during 2 years for contributions towards project milestones.
Aga Khan Foundation Scholar 2011-2013.
Valero Competitive Research Award 2011-12 and Alvarez Masters Award 2012-13
Ranked among Top 5% students throughout undergrad Electronic Engg: batch.
Aga Khan Youth & Sports Board Green Awards 2003 & 2005 for Distinction in Secondary and High School Board Exams.
STAR Girl Award 1994 in Education by South Asia Publications.

US Permanent Resident