Physica E 74 (2015) 6570

Contents lists available at ScienceDirect

Physica E
journal homepage: www.elsevier.com/locate/physe

A novel nanoscale n eld effect transistor by amended channel: Investigation and fundamental physics
Fa. Karimi, Ali A. Orouji n
Electrical and Computer Engineering Department, Semnan University, Semnan, Iran

H I G H L I G H T S

G R A P H I C A L

Proposal of a novel FinFET including

an amended channel.

Suppression of the short channel
effects.

Considerable improvement of the
critical electrical and thermal
characteristics.

We propose a novel reliable FinFET with an amended channel, where the lower part of the n has a
rounded shape and the upper part is cubic.

art ic l e i nf o

a b s t r a c t

Article history:
Received 2 April 2015
Received in revised form
8 June 2015
Accepted 9 June 2015
Available online 17 June 2015

The present paper proposes a new Fin Field Effect Transistor (FinFET) with an amended Channel (AC).
The n region consists of two sections; the lower part which has a rounded shape and the upper part of
n as conventional FinFETs, is cubic. The AC-FinFET devices are proven to have a lower threshold voltage
roll-off, reduced DIBL, better subthreshold slope characteristics, and a better gate capacitance in comparison with the C-FinFET. Moreover, the simulation result with three-dimensional and two-carrier
device simulator demonstrates an improved output characteristic of the proposed structure due to reduction of self-heating effect. Due to the rounded shape of the lower n region and decreasing corner
effects there, the heat can ow easily, and the device temperature will decrease. Also the gate control
over the channel increases due to the narrow upper part of the n. The paper, thus, attempts to show the
advantages of higher performance AC-FinFET device over the conventional one, and its effect on the
operation of nanoscale devices.
& 2015 Elsevier B.V. All rights reserved.

Keywords:
Short channel effect (SCE)
Drain-induced barrier lowering (DIBL)
Self-heating effects
FinFET
Three dimensional simulations

A B S T R A C T

AC-FinFET

1. Introduction
With the continuous scaling of semiconductor devices into the
nanometer regime, non-ideal effects such as quantum effect and
short channel effect (SCE) have been considered as crucial issues
severely degrading the performance of CMOS devices. In order to
suppress these challenges, the Silicon-On-Insulator Multigate Field

Corresponding author. Fax: 98 233365123

E-mail address: aliaorouji@semnan.ac.ir (A.A. Orouji).

http://dx.doi.org/10.1016/j.physe.2015.06.008
1386-9477/& 2015 Elsevier B.V. All rights reserved.

Effect Transistors (SOI MuFETs) are proved to be one of the promising structures in nanoscale CMOS technology [1]. Among these
structures, n-shaped FETs (FinFETs) have absorbed a lot of attraction since their fabrication is fully compatible to standard
CMOS process [2,3]. The fact that SOI multigate FETs possess
multiple channels, they have a better controllability, higher SCE
immunity, higher current drive, improved subthreshold slope and
potential circuit exibility [4,5]. Despite having aforementioned
advantages, SOI multigate FETs have disadvantages, such as corner
effect. In the FinFETs, the n regions have a signicant role in
determining the mentioned advantages [6]. The width of ns is

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Fa. Karimi, A.A. Orouji / Physica E 74 (2015) 6570

one of the most critical parameters in FinFET devices. As the n

width decreases, the gate control over the channel improves and
SCE decreases. However, many disadvantages degrade the performance of FinFET [79]. For instance, by decreasing the n width,
parasitic source/drain (S/D) resistance will enhance, which degrade the drive current and the transconductance in the devices.
Another grave problem in narrow FinFET is the corner effect in
relation to the multiple-gate structure, which results in gathering
of current in the corner in crowded manner, and producing much
heat leading to self-heating. In narrow ns, the heat cannot ow
easily and, therefore, the device temperature increases. In the
previous efforts, novel structures of FinFET have been disgusted in
order to solve these problems [1012].
To enhance the immunity against the short-channel effects and
therefore improve the device reliability in high performance circuit applications, a new structure of FinFET in which the lower
part of the n has a rounded shape is proposed to control the selfheating effect. In order to decrease the short channel effects the
upper part of n is similar to a conventional FinFET (C-FinFET) and
is cubic. Therefore, we call the proposed structure Amended
Channel FinFET (AC-FinFET). Beside, the exact values of each section of the proposed structure are simulated to have the excellent
characteristics in thermal aspect. The simulation with 3-D ATLAS
simulator [13] indicates that the proposed structure has the best
behavior in terms of subthreshold slope, DIBL, off current, hot
electron effects, self-heating effects and gate capacitance in comparison with the C-FinFET.

2. Device structure and simulations

As the schematic of the AC-FinFET is shown in Fig. 1, the n
regions consist of two parts, the part with rounded shape which is
located at the tail end of the n is called round part, while the
upper part with narrower width located in the top region of the
n, is named the at part. In order to determine the main parameters used in the proposed structure, the cross sections of the
AC-FinFET and C-FinFET are shown in Fig. 2(a) and (b), along with
cut line AA (vertical axis of the structure) located in the n region,
respectively. As shown in this gure, the widths of round and at
parts in the AC-FinFET are called WR and WF, respectively. Also, the
height of round part is labeled as HR and the at part is named HF.
With the aim of the best characteristics in the AC-FinFET structure,
the optimum values of each part are obtained and discussed in the

Fig. 1. A schematic of the AC-FinFET structure implemented in ATLAS simulator.

Fig. 2. Schematic cross section of the n region in (a) AC-FinFET and (b) C-FinFET.

following section. Moreover, we dened the sum of the heights of

at and round parts as the n height. In addition, the maximum
n width of the AC-FinFET structure (WRmax) is equal to the width
of the C-FinFET structure.
Comparisons between the structures have been accomplished
utilizing the three-dimensional ATLAS simulator. Moreover, for
mobility model the full energy balance model has been selected in
which the electron temperature is fed back into the continuity
equation and the impact ionization is again computed as a postprocessing stage. It is worth mentioning that conventional threedimensional (3D) simulation of semiconductor devices is based on
the Thermal Equilibrium Approximation (TEA) in which the carrier
temperature is the same as the lattice temperature. In nanoscale
devices, under the high electric eld, the carrier temperature can
be much higher than the ambient temperature. Therefore, conventional drift models are not sufcient to describe the drain
current characteristics and the energy balance equation needs to
be applied for improved prediction of the nanoscale device behavior [1416]. Moreover, it should be noted that a ground substrate contact in the AC-FinFET device have been used and the heat
transferring through the metal interconnect has been neglected in
this study. The temperatures of substrate, source and drain electrodes are xed at 300 K, As well. In addition, the quantum-mechanical transport simulation is performed by solving a set of 3D
density-gradient equations coupled with the Poisson equation, as
well as electronhole current continuity equations [17]. The ACFinFET parameters used in the present simulation are shown in
Table 1. All the device parameters of the new structure are
equivalent to those of the C-FinFET unless mentioned.
As the next step, the 3-D simulator has been calibrated with
experimental data in the nanoscale regime [18]. The n width has
been set to a value of 15 nm with 20 nm gate length and 3 nm gate
oxide thickness in the C-FinFET as measured on the fabricated
devices [18]. The output characteristics extracted from experimentally measured have been compared with those extracted
from ATLAS simulation in Fig. 3, at VG  Vt 0.6 V. In order to make
a realistic comparison between this structure and the conventional

Fa. Karimi, A.A. Orouji / Physica E 74 (2015) 6570

Table 1
Required characteristics for designing the AC-FinFET structure.

Thermal Resistance

Gate length (LG)

Extended n length (LFin)
Gate oxide thickness (tOX)
Buried oxide thickness (tBOX)
Width of round part (WR)
Width of at part (WF)
Height of round part (HR)
Height of at part (HF)
Fin Height (HFin)
Channel doping concentration (NA)
Source/drain doping concentration
(ND)
Gate work-function

30 nm
40 nm
1.2 nm
30 nm
24 nm
14 nm
10 nm
20 nm
30 nm
1015 cm  3
1020 cm  3

30 nm
40 nm
1.2 nm
30 nm
24 nm
Not dened
Not dened
Not dened
30 nm
1015 cm  3
1020 cm  3

AC-FinFET(LG= 30 nm)

350

VDS=0.5 V
310
12

14

16

18

20

22

24

300
200
100
0
1.1 1.2

Drain Voltage (V)

Fig. 3. The output characteristic of simulated C-FinFET has been compared with
experimental results at LG 20 nm, tOX 3 nm and VG  Vt 0.6 V.

planer device, it is necessary to normalize the current using the

total width controlled by the gate. Hence, the total current is divided to twice the Fin height plus the Fin width [18]. It can be
observed from Fig. 3 that an acceptable agreement between experimental data and 3-D simulation results is achieved. So, the
benet of high performance AC-FinFET provides an incentive for
future experimental exploration.

3. Design considerations of the AC-FinFET

In the present section, the optimization of AC-FinFET parameters (WF, WR, HF, and HR) is investigated to design the desired
AC-FinFET structure. To determine the optimum value of the WF,
we have investigated variations of the thermal resistance and
lattice temperature versus the width of the channels at part (WF)
using the 3-D ATLAS simulator. All through the present study, the
maximum n width of round part is the same as the n width of
C-FinFET structure and is set to 24 nm. The thermal resistance and
maximum lattice temperature versus WF are shown in Fig. 4. As
the gure demonstrates, the thermal resistance of AC-FinFET increases when the width of at part decreases. According to Eq. (1),
the thermal resistance increases by decreasing the total n width
[19].

(1)

Where W is the device width, tbox and tsi are the thicknesses of the
BOX and Si body and Kbox and Kd are the thermal conductivities of
the BOX and Si layers, respectively. On the other hand, by decreasing the width of at part, the radius of the round part

Electron Temperature
3300

350

Maximum Lattice Temperature

3250

340

3200

330

3150

320

AC-FinFET(LG= 30 nm)
VDS=1.2 V

3100

Maximum Lattice
Temperature (K)

400

increases and provides more space to ow the heat. In addition, by

decreasing the WF, the corner effect decreases due to the rounded
shape of the round part. So, the maximum lattice temperature
decreases by reducing the WF as shown in Fig. 4. In nanoscale
devices the critical electric eld and electron temperature are
important parameters to determine the device reliability. Therefore, the effect of WF on the electron temperature and lattice
temperature in high drain voltage is investigated as in Fig. 5. The
gure shows that by decreasing the width of at part, and thus
increasing the radius of round parts width, the electron temperature and maximum lattice temperature improves due to the
reduction of the corner effects. Therefore, to control the thermal
resistance and also lower the lattice temperature, the optimum
width of at part, WF 14 nm is chosen according to stated
evidences above. It is important to note that the extracted value
for WF 24 nm, is related to the C-FinFET. In Fig. 6, the maximum
lattice temperature and electron temperature of the AC-FinFET
versus the height of at part (HF) are plotted. As can be seen from
the gure, the maximum temperature decreases a little when the
height of at part increases, leading to lower self-heating effects.
Indeed, the lattice temperature versus the at parts height is
plotted in two different buried oxide thicknesses in the small
curve inside Fig. 6. The gure shows the self-heating effect
increases by increments of the buried oxide thickness for all
values of HF. It is important to note that the best cooling capability
occurs if the ratio of the surface of vertical heat ux to the volume
of the active region increases. To get the optimum length of at
part the off and on state current values are investigated. Fig. 7,
shows the transconductance characteristics of the AC-FinFET for
different values of the height of the at part at a drain voltage of
0.5 V and a channel length of 30 nm. As the gure shows, the

Electron
Temperature (k)

Drain Current (uA/um)

Experimental Data [18]

500

tbox
1
1
(
)2
2W k box k d tsi

400

Width of Flat Part (nm)

600

R th =

315

450

Fig. 4. Maximum lattice temperature and thermal resistance versus the width of
the at part in the AC-FinFET (WF) at HF 20 nm, VGS 0.9 V and VDS 0.5 V.

ATLAS Simulation

500

10

4.6 eV

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

550

300

700

320

Max Lattice Temperature

Maximum Lattice
Temperature (K)

Value in AC-FinFET Value in C-FinFET

Thermal Resistance
(Kum/mW)

600

Parameter

4.6 eV

67

310
10

12

14

16

18

20

22

24

Width of Flat Part (nm)

Fig. 5. Maximum electron temperature and lattice temperature versus the width of
the at part of the n in the AC-FinFET (WF) at HF 20 nm, VGS 0.9 V and
VDS 1.2 V.

Fa. Karimi, A.A. Orouji / Physica E 74 (2015) 6570

330

4. Results and discussion

3200

Electron Temperature
329

3180

328

3160

327

3140

326

3120

325

Electron Temperature (K)

Maximum Lattice Temperature (K)

Max Lattice Temperature

3100

14

16

18

20

22

24

Height of Flat Part (nm)

Fig. 6. Maximum electron temperature and lattice temperature versus the height
of the at part of the AC-FinFET (HF) at LG 30 nm, WF 14 nm, VGS 0.9 V and
VDS 1.2 V.

1.40E-05

Drain Current (A)

1.20E-05
1.00E-05
8.00E-06
6.00E-06
4.00E-06
2.00E-06
0.00E+00
0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Gate Voltage (V)

Fig. 7. Transfer characteristics of the AC-FinFET at WF 14 nm, LG 30 nm, and
VDS 0.5 V.

Off Current (A)

1.14E+06
1.05E+06

3.16E-11

1.11E+06

1.01E+06

2.80E-11

1.80E-11

1.60E+06

On / Off Current Ratio

3.80E-11

1.10E+06

6.00E+05

5.09E+05
1.194E-11
1.07E-11

1.28E-11

1.09E-11

8.00E-12

On Current/Off Current Ratio

Off Current

1.00E+05

16

18

20

22

Height of Flat Part (nm)

Fig. 8. Off current and on to off current ratio versus the height of the at part (HF)
at VDS 0.5 V.

higher on state current is achieved in shorter value of HF. On the

other hand, the control of gate improves and the off current
decreases by increasing the HF. The off current and switching
speed of the AC-FinFET versus the height of the at part is shown
in Fig. 8. Therefore, to get better control over the channel, lower
self-heating effect, and also better on to off current ratio, the
height of the channels at part, the HF 20 nm is chosen.

In this section the proposed device and conventional one will

be compared in order to determine the benets of AC-FinFET. In
nanoscale devices, threshold voltage and subthreshold slope are
signicant parameters for the best exhibition of the device. The
subthreshold slope is based on the inverse slope of semi-logarithmic ID VG curve (S (dVG/d log(ID))) [20]. In Fig. 9, the variations
of threshold voltages versus temperature have been shown for ACFinFET and C-FinFET structures. The variation of threshold voltage
with temperature is related to the height and width of ns [6,21].
Narrower ns lead to higher threshold voltage [6,22]. In the ACFinFET, the at part of the n has narrower width; so, the
threshold voltage becomes higher in relation to the C-FinFET. In
another point of view, the threshold voltage decreases if the
temperature increases. The threshold voltage of C-FinFET structure
is reduced more in comparison with the AC-FinFET in 250 C. In
addition, the behavior of subthreshold slope at high temperature is
due to the n width [6]. It is clear from Fig. 10 that the subthershold slope improves in all temperatures due to the narrower part
of the AC-FinFET compared with the C-FinFET. In both gures, the
round part improves the variation of threshold voltage versus
temperature due to heat dissipating by the round edges of the n.
In Fig. 11, the subthreshold swings of the AC-FinFET and the
C-FinFET are compared as a function of gate length. According to
the gure, the degradation of the AC-FinFET structure is smaller
when the channel length is reduced. Moreover, the subthreshold
swing of the proposed structure has smaller value in all channel
lengths in comparison with the C-FinFET structure and it is related
to higher gate controllability.
Drain induced barrier lowering (DIBL) is one of the short
channel effects that occurs in both the bulk and SOI MOSFETs
[23,24]. The DIBL and SCE effects have been shown in Figs. 12 and
13, for both the AC-FinFET and C-FinFET in different effective gate
lengths. The DIBL is dened as the difference between the
threshold voltages at VDS 0.5 V and VDS 0.05 V. The threshold
voltage roll-off or SCE is extracted as the threshold voltage measured at VDS 0.05 V in all gate lengths minus the threshold voltage at LG 80 nm. As Fig. 12 shows, the DIBL is effectively suppressed in the AC-FinFET structure in comparison with the
C-FinFET. This reduction is due to the narrow width of the at part
of the AC-FinFET structure. Similarly, the threshold voltage roll-off
or SCE is decreased in the proposed structure and has an excellent
behavior with respect to the C-FinFET as shown in Fig. 13.
In order to emphasize the impact of the at and round parts of
AC-FinFET, the gate capacitance versus the gate voltage of the ACFinFET and C-FinFET are also investigated. As can be seen from

0.25

Threshold Voltage (V)

68

0.2
0.15
0.1

C-FinFET
AC-FinFET

0.05
0
0

50

100

150

200

250

Temperature (C)
Fig. 9. Threshold voltage variation with temperature for both the AC-FinFET and
C-FinFET.

Threshold Voltage Roll Off (mV)

Fa. Karimi, A.A. Orouji / Physica E 74 (2015) 6570

Subthreshold Slope (mV/dec)

130
120
110
100
90
80
70

C-FinFET

60

AC-FinFET

50
0

50

100

150

200

20

69

18

C-FinFET
13

15

AC-FinFET

16
8.5

10

11
5
7

30

40

50
60
Gate Length (nm)

Temperature (C)

70

80

Fig. 13. The threshold voltage roll-off for AC-FinFET and C-FinFET structures at
VDS 0.05 V.

60

64

Gate Capacitance (x10E-18 F)

65

Subthreshold Swing (mV/dec)

250

Fig. 10. Variation of the subthreshold slope with temperature for both the ACFinFET and C-FinFET.

2
4

C-FinFET
AC-FinFET

63
62
61
60
59
0

30

40

50

60

70

80

Gate Length (nm)

C-FinFET

50

AC-FinFET
40
30
20
10
0
-0.3

-0.1

0.1

0.3

0.5

0.7

0.9

1.1

Gate Voltage (V)

Fig. 11. Sub-threshold characteristics versus gate length of AC-FinFET and C-FinFET.
Fig. 14. Gate capacitance versus gate voltage for AC-FinFET and C-FinFET structures.

300
280

C-FinFET

250

DIBL (mV)

AC-FinFET
204

200
189

150
130
89

100

110
58
80

50

43

60
43

0
0

30

40

50
60
Gate Length (nm)

70

35

80

Fig. 12. DIBL effect versus gate length for AC-FinFET and C-FinFET structures.

Fig. 14, the gate capacitance improves in the proposed structure in

14 nm width of at part. This betterment is due to the reduced
sidewall area in the channel region using a narrower part in the
at part of the n. Therefore, the total gate capacitance reduces in
comparison with the C-FinFET.

5. Conclusion
In order to improve the short channel effects and also prevent
from the heat accumulation, a novel reliable nanoscale SOI FinFET
called the amended channel FinFET (AC-FinFET) was proposed. In
the proposed structure the n regions are separated into two
sections, each with different width and height. Also, the optimum

values of each part are determined. The round part of ns improves the corner effect by using the rounded shape and therefore
the heat can ow easily and eventuate to control the self-heating
effect. The at part of the ns has the narrower width and improves the gate controllability; therefore, eventuate to decline the
short channel effects. In addition, the results illustrate that the
threshold voltage variation, subthreshold slope, and off current at
different temperatures and different channel lengths are the most
important improved parameters in the proposed structure in
comparison with a conventional FinFET. An inclusive comparison
between the AC-FinFET and the C-FinFET shows the superiority of
the structure to the conventional one. As a result, the AC-FinFET
device can be regarded as a useful substitute for the C-FinFET in
nanoscale devices by reducing the short channel effects and also
preventing the heat accumulation.

References
[1] J.P. Colinge, Silicon-on-insulator Technology: Materials to VLSI, Kluwer Academic Publishers, 2004.
[2] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, Member, L. Chang, J. Kedzierski,
E. Anderson, H. Takeuchi, Y.-K. Choi, K. Asano, V. Subramanian, T.-J. King,
J. Bokor, C. Hu, IEEE Trans. Electron Devices 48 (2001) 880.
[3] J.P. Colinge, Solid-State Electron. (2004) 897.
[4] D. Hisamoto, W.C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson,
T.J. King, J. Bokor, C. Hu, IEEE Trans. Electron Devices 47 (2000) 2320.
[5] B. Yu, L. Chang, S. Ahmad, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, T. King Liu,
J. Bokor, M. Lin, D. Kyser, IEDM Tech. Dig. (2002) 251.
[6] V. Kilchytska, N. Collaert, M. Jurczak, D. Flandre, Solid-State Electronics 51
(2007) 1185.
[7] V. Kilchytska, N. Collaert, R. Rooyackers, D. Lederer, J.-P. Raskin, D. Flandre, Eur.

70

Fa. Karimi, A.A. Orouji / Physica E 74 (2015) 6570

Solid State Device Res. Conf. 48 (2004) 65.

[8] A. Dixit, A. Kottantharayil, N. Collaert, M. Goodwin, M. Jurczak, K. De Meyer,
IEEE Trans. Electron Devices 52 (2005) 1132.
[9] D. Lederer, B. Parvais, A. Mercha, N. Collaert, M. Jurczak, J.-P. Raskin, S. Decoutere, in: Proceedings of the 6th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2006, p. 8.
[10] M. Mehrad, A.A. Orouji, IEEE Trans. Device Mater. Reliab. 10 (2010) 271.
[11] A.A. Orouji, M. Mehrad, Jpn. J. Appl. Phys. 50 (2011) 124303.
[12] M. Mehrad, A.A. Orouji, Physica E 44 (2011) 654.
[13] ATLAS Users Manual: 3-D Device Simulator, SILVACO International, 2012.
[14] T.H. Ning, P.W. Cook, R.H. Dennard, C.M. Schuster, H.N. Yu, IEEE Trans. Electron
Devices 26 (1979) 346.
[15] H. Gesch, J.P. Leburton, G.E. Dorda, IEEE Trans. Electron Devices 29 (1982) 913.
[16] K.K. Ng, G.W. Taylor, IEEE Trans. Electron Devices 30 (1983) 871.
[17] C. Riddet, A.R. Brown, C.L. Alexander, J.R. Watling, S. Roy, A. Asenov, IEEE Trans.

Nanotechnol. 6 (2007) 48.

[18] J. Kretz, L. Dreeskornfeld, R. Schroter, E. Landgraf, F. Hofmann, W. Ro sner, Solid
State Microelectron. Eng. 73 (2004) 803.
[19] A. ONeill, et al., Appl. Surf. Sci. 254 (2008) 6182.
[20] J.P. Colinge, C.A. Colinge, Physics of Semiconductor Devices, Kluwer Academic
Publishers, USA, 2002.
[21] P. Francis, A. Terao, F. Van de Wiele, IEEE Trans. Electron Devices 41 (1994) 715.
[22] V. Subramanian, A. Mercha, B. Parvais, J. Loo, C. Gustin, M. Dehan, N. Collaert,
M. Jurczak, G. Groeseneken, W. Sansen, S. Decoutere, Solid-State Electron. 51
(2007) 551.
[23] S. Cristoloveanu, S.S. Li, Electrical Characterization of SOI Materials and Devices, Kluwer, Norwell, MA, 1995.
[24] J.H. Huang, Z.H. Liu, M.C. Jeng, P.K. Ko, C. Hu, IEDM Tech. Dig. (1992) 569.