Beruflich Dokumente
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LOGICAL
DESIGN
UNIVERSITY OF
ENGINEERING AND
TECHNOLOGY TAXILA
Presented By:
MOHSIN ZUBAIR: 15-EE110
TALHA AAMIR: 15-EE-158
HAMZA SULAIMAN: 15EE-14
SUBMITTED TO:
DEPARTMENT
OF ELECTRICAL
ENGINEERING
MAM
ZUNAIRA
HUMA
TABLE OF CONTENTS_______________
Page
VEDIC MULTIPLIER
8X8 VEDIC BUILDING
CONCLUSION..16
LESSON LEARNT...16
PROBLEM FACED..16
Vedic Multiplier
A digital multiplier which is used for simple and easy multiplication of binary numbers based
on the Indian system of Urdhva Triyakbhyam (Vertically and Cross wise). Developed
in ancient times this method uses 16 different sutras or word formulae. In our
project we have made 8x8 Vedic Multiplier which will take two 8 bit binary numbers and
multiply them. In order for us to better understand the 8x8 we first have to understand the
basic building blocks of the multiplier. To do this we start by making 2x2 and 4x4 multipliers
and combining them to make the 8x8 Vedic multiplier.
8x8 Vedic Building
In our project we have implemented 8x8 Vedic by using four 4x4 Vedic Multipliers and three
adders.
Following adders were used:
4 bit
6 bit
8 bit
12 bit
6 and gates
2 xor gates
*usage of 2 half adders could also have made our 2x2 multiplier
Implementation of the 4x4 Vedic required four 2x2 Vedic and three adders which were:
4 bit
6 bit
6 bit
It can also be implemented using 4 and gates and two half adders but we have used only
gates.
Block Diagrams for 8x8, 4x4 and 2x2 Vedic Multipliers are given below:
Block Diagram
DEPARTMENT OF ELECTRICAL ENGINEERING |
Verilog Code
// 2x2 Vedic multiplier setup
module vedic2x2 (q,a,b);
input [1:0] a,b;
output [3:0] q;
wire [3:0] w;
// It includes 8 gates that can be implemented individually or we can also use two half adder
// 6 "and" gates and 2 "xor" gates
and g1 (q[0],a[0],b[0]);
DEPARTMENT OF ELECTRICAL ENGINEERING |
and g2 (w[0],a[1],b[0]);
and g3 (w[1],a[0],b[1]);
and g4 (w[3],a[1],b[1]);
xor g5 (q[1],w[0],w[1]);
and g6 (w[2],w[0],w[1]);
xor g7 (q[2],w[2],w[3]);
and g8 (q[3],w[2],w[3]);
endmodule
// Test bench of 2x2 Vedic
module testbench_vedic2x2 ();
reg [1:0] a,b;
wire [3:0] q;
vedic2x2 tb0 (q,a,b);
initial
begin
a=2'b10; b=2'b11;
end
endmodule
// Setup for 4x4 Vedic Multiplier
// A 4x4 bit Vedic is implemented by using "4" 2x2 Vedic and "3" adders, one adder is 4 bit
and two are 6 bit
// Basic Full Adder
// A Full adder can be implemented by using 2 "and" 2 "xor" and 1 "or" gate
module FA (carry,sum,A,B,C);
input A,B,C;
output carry,sum;
wire m0,m1,m2;
xor g9 (m0,A,B);
and g10 (m1,A,B);
DEPARTMENT OF ELECTRICAL ENGINEERING |
FA ad8 (C4,S[3],A[3],B[3],C3);
FA ad9 (C5,S[4],A[4],B[4],C4);
FA ad10 (cout,S[5],A[5],B[5],C5);
endmodule
// 4x4 Vedic Multiplier code
module vedic4x4 (Q,a,b);
// 4 bit inputs
input [3:0] a,b;
// 8 bit output
output [7:0] Q;
// wire used inside 4x4 Vedic
// 4 bit wires
wire [3:0] q1,q0,q2,q3,q4;
// 6 bit wire
wire [5:0] q5;
// carry in and carry out which are not used in the circuit
wire cin,cout;
// carry in and carry out of all adders always remain zero
assign cin=0;
assign cout=0;
// First two bits of first 2x2 Vedic goes directly to main output of 4x4 Vedic
assign Q[1:0]=q0[1:0];
// 4 2x2 Vedic and 3 Adders
// First two bits of "a" & "b" inputs are multiplied by first Vedic
vedic2x2 v1 (q0[3:0],a[1:0],b[1:0]);
// Second Vedic multiplies last two bits of input "a" and first two bits of "b"
vedic2x2 v2 (q1[3:0],a[3:2],b[1:0]);
// Third Vedic multiplies first two bits of input "a" and last two bits of input "b"
vedic2x2 v3 (q2[3:0],a[1:0],b[3:2]);
DEPARTMENT OF ELECTRICAL ENGINEERING |
// Forth Vedic multiplies last two bits of both inputs "a" & "b"
vedic2x2 v4 (q3[3:0],a[3:2],b[3:2]);
// 4 bit adder
// Last two bits from output of First Vedic goes into first input of First "4" bit adder.
// This input fills two bits remaining two bits are fixed "0"
// 4 bit output from second Vedic goes into second input of "4" bit adder
FA4b ad11 (cout,q4[3:0],{2'b00,q0[3:2]},q1[3:0],cin);
// 6 bit adders
// 4 bit output from third Vedic goes into first input of second adder which is 6 bit adder
// 4 bits are filled remaining last two bits are fixed "0"
// Similarly from forth Vedic output goes into last 4 bits of second input of adder
// Last 4 bits are filled remaining first two bits are fixed "0"
FA6b ad12 (cout,q5[5:0],{2'b00,q2[3:0]},{q3[3:0],2'b00},cin);
// 4 bit output from first adder goes into input of third adder which is also 6 bit,
// first 4 bits are filled remaining last two bits are fixed "0"
// 6 bit output from second adder goes into second input of third adder
// 6 bit output of this adder goes to main output
FA6b ad13 (cout,Q[7:2],{2'b00,q4[3:0]},q5[5:0],cin);
endmodule
// Test bench for 4x4 Vedic
module testbench_vedic4x4 ();
reg [3:0] a,b;
wire [7:0] Q;
vedic4x4 tb1 (Q,a,b);
initial
begin
a=4'b1011;
b=4'b1101;
end
DEPARTMENT OF ELECTRICAL ENGINEERING |
endmodule
// 8x8 Vedic Multiplier setup
// 8 bit Adder using "8" Full adders which are connected in series
// It can add any two 8 bit numbers
module FA8b (cout,S,A,B,cin);
input [7:0] A,B;
input cin;
output [7:0] S;
output cout;
wire [6:0] C;
FA ad14 (C[0],S[0],A[0],B[0],cin);
FA ad15 (C[1],S[1],A[1],B[1],C[0]);
FA ad16 (C[2],S[2],A[2],B[2],C[1]);
FA ad17 (C[3],S[3],A[3],B[3],C[2]);
FA ad18 (C[4],S[4],A[4],B[4],C[3]);
FA ad19 (C[5],S[5],A[5],B[5],C[4]);
FA ad20 (C[6],S[6],A[6],B[6],C[5]);
FA ad21 (cout,S[7],A[7],B[7],C[6]);
endmodule
//12 bit Full Adder using "12" Full adders which are all connected in series to form 12 bit
adder
// Can add any two 12 bit numbers
module FA12b (cout,S,A,B,cin);
input [11:0] A,B;
input cin;
output [11:0] S;
output cout;
wire [10:0] C;
FA ad22 (C[0],S[0],A[0],B[0],cin);
DEPARTMENT OF ELECTRICAL ENGINEERING |
FA ad23 (C[1],S[1],A[1],B[1],C[0]);
FA ad24 (C[2],S[2],A[2],B[2],C[1]);
FA ad25 (C[3],S[3],A[3],B[3],C[2]);
FA ad26 (C[4],S[4],A[4],B[4],C[3]);
FA ad27 (C[5],S[5],A[5],B[5],C[4]);
FA ad28 (C[6],S[6],A[6],B[6],C[5]);
FA ad29 (C[7],S[7],A[7],B[7],C[6]);
FA ad30 (C[8],S[8],A[8],B[8],C[7]);
FA ad31 (C[9],S[9],A[9],B[9],C[8]);
FA ad32 (C[10],S[10],A[10],B[10],C[9]);
FA ad33 (cout,S[11],A[11],B[11],C[10]);
endmodule
// 8x8 Vedic Multiplier code
module vedic8x8 (Q,a,b);
// 8 bit inputs
input [7:0] a,b;
// 16 bit output
output [15:0] Q;
// wires used in circuit
// 8 bit wires
wire [7:0] q0,q1,q2,q3,q4;
// 12 bit wire
wire [11:0] q5;
// carry in and carry out are not used in the circuit
wire cin,cout;
// carry in and carry out always remain zero
assign cin=0;
assign cout=0;
// First 4 bits of first 4x4 Vedic goes directly at main output
DEPARTMENT OF ELECTRICAL ENGINEERING |
assign Q[3:0]=q0[3:0];
// Four 4x4 Vedic
// First 4 bits of "a" & "b" inputs are multiplied by first Vedic
vedic4x4 v5 (q0[7:0],a[3:0],b[3:0]);
// Second Vedic multiplies last 4 bits of input "a" and first 4 bits of input "b"
vedic4x4 v6 (q1[7:0],a[7:4],b[3:0]);
// Third Vedic multiplies first 4 bits of input "a" and last 4 bits of input "b"
vedic4x4 v7 (q2[7:0],a[3:0],b[7:4]);
// Forth Vedic multiplies last 4 bits of both inputs "a" & "b"
vedic4x4 v8 (q3[7:0],a[7:4],b[7:4]);
// Three Full adders
// 8 bit adder
// Last 4 bits from output of First Vedic goes into first input of First "8" bit adder
// This input fills 4 bits remaining 4 bits are fixed "0"
// 8 bit output from second Vedic goes into second input of "8" bit adder
FA8b ad34 (cout,q4[7:0],{4'b0000,q0[7:4]},q1[7:0],cin);
// Two 12 bit adders
// 8 bit output from third Vedic goes into first input of second adder which is 12 bit adder
// 8 bits are filled remaining last 4 bits are fixed "0"
// similarly from forth Vedic output goes into last 8 bits of second input of adder
// Last 8 bits are filled remaining first 8 bits are fixed "0"
FA12b ad35 (cout,q5[11:0],{4'b0000,q2[7:0]},{q3[7:0],4'b0000},cin);
// 8 bit output from first adder goes into input of third adder which is also 12 bit
// first 8 bits are filled remaining last 4 bits are fixed "0"
// 12 bit output from second adder goes into second input of third adder
// 12 bit output of this adder goes to main output
FA12b ad36 (cout,Q[15:4],{4'b0000,q4[7:0]},q5[11:0],cin);
endmodule
// Test bench for 8x8 Vedic
DEPARTMENT OF ELECTRICAL ENGINEERING |
Simulation
2x2 Vedic Multiplier
In our simulation of 2x2 Vedic Multiplier we used two bit numbers which are 2 & 3
whose binary values are following respectively
10
11
There multiplication yields 4 bit number 6 whose binary value is following
0110
Simulation of 2x2 Vedic is given below
In our simulation of 4x4 Vedic Multiplier we used four bit numbers which are 11 & 13
whose binary values are following respectively
1011
1101
There multiplication yields 8 bit number 143 whose binary value is following
1000111
Simulation of 4x4 Vedic is given below:
DEPARTMENT OF ELECTRICAL ENGINEERING |
10110110
11010100
There multiplication yields 16 bit number 38584 whose binary value is following
1001011010111000
Simulation of 8x8 Vedic is given below:
Conclusion
We concluded following points from our project
Vedic is an easy efficient and time saving way of multiplying binary numbers.
We can make 2x2 Vedic by using 6 and & 2 xor gates.
We can also make 2x2 Vedic by using 4 and & 2 half adders.
4x4 Vedic can be implemented by using 4 2x2 Vedic and three adders.
Similarly 8x8 Vedic can be implemented by using 4 4x4 Vedic and three adders.
Lesson Learnt
Problem Faced
During our project we faced following problems
In 4x4 Vedic multiplier we faced with the problem of selecting and assigning bits to
wires.
We also faced problem during calling of adder in 4x4 Vedic multiplier as we did not
understand where the initial carry came from or where the final carry went.
Same problems were faced during 8x8 Vedic but as we already faced and solved these
problems in 4x4 Vedic we easily overcome them in our 8x8 code
No further problems were faced