DSD - Lab Observation PDF

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE
DEPARTMENT OF COMPUTE SCIENCE AND ENGINEERING

[JUNE 2016 NOVEMBER 2016]
CS P33
DIGITAL SYSTEM DESIGN LABORATORY
II YEAR/III SEMESTER
LAB OBSERVATION
Name of the student : ________________________________

Register Number
: ________________________________
Section
: ________________________________
Batch
:A
P a g e |1 DIGITAL DESIGN LAB
DEPARTMENT OF CSE

Subject
Subject Name
Code
CS P33
Lectures
Tutorial
Practical
(Periods)
(Periods)
(Periods)
DIGITAL DESIGN LABORATORY
LIST OF EXPERIMENTS
1. Study of logic gates
2. Verification of DeMorgans theorems using basic logic gates.
3. Design and implementation of adders and subtractors.
4. Design and implementation of Carry Look-Ahead Adders.

5. Design and implementation of Parity Generator/Checkers.
6. Design and implementation of Priority encoders using logic gates.
7. Design and implementation of simplified Boolean expressions using Multiplexers.
8. Design and implementation of simplified Boolean expressions using Decoders.
9. Design and implementation of Magnitude Comparators.
10. Study of clocked RS, D, and JK Flip-Flops.
11. Design and implementation of Serial Input Parallel Output (SIPO) and Parallel
Input Serial Output (PISO) Shift Registers.
12. Design and implementation of ripple and synchronous counters.
13. Simulation of a combinational logic using HDL.
14. Simulation of a sequential logic using HDL.
15. Implementation of given Boolean expressions using multioutput PAL/PLA
realization.
16. Implementation of a sequential circuit using PAL/PLA realization.
DEPARTMENT OF CSE

FIRST CYCLE EXPERIMENTS
1. Study of logic gates.
2. Verification of DeMorgans theorems using basic logic gates.
3. Study and implementation of adders and subtractors.
4. Design and implementation of code converters
a. BINARY to GRAY
b. GRAY to BINARY
5. Design and implementation of code converters
a. BINARY to EXCESS 3
b. EXCESS 3 to BINARY
6. Implementation of Boolean Functions using NAND / NOR Logic gates.
7. Design of Parity Generator
8. Design and implementation of simplified Boolean expressions using Multiplexers.
9. Design and implementation of simplified Boolean expressions using Decoders.
SECOND CYCLE EXPERIMENTS

10. Design and implementation of magnitude comparator
11. Study of Flip Flops (RS, JK and D-types)
12. Study of Shift Registers in various Mode of operation
13. Design and implementation of Ring and Johnson Counters
14. Construction and Verification of 4 bit Ripple Counter.
15. Simulation of combinational logic using HDL.
16. Simulation of sequential logic using HDL.
DEPARTMENT OF CSE

INDEX
EX.NO.
DATE
NAME OF THE EXPERIMENT
PAGE
NO.
MARKS
SIGNATURE
CYCLE I
1
Study of logic gates
Verification of DeMorgans theorems

using basic logic gates.
Study and implementation of adders and

subtractors using logic gates.
Design and implementation of code converters

I using logic gates.
a. BINARY to GRAY
b. GRAY to BINARY
6
7
8
9
Design and implementation of code converters

II using logic gates.
a. BINARY to EXCESS 3
b. EXCESS 3 to BINARY
Implementation of Boolean Functions using
NAND / NOR Logic gates.
Design of Parity Generator

Design and implementation of simplified
Boolean expressions using Multiplexers.
Design and implementation of simplified
Boolean expressions using Decoders.
CYCLE II
10
Design and implementation of magnitude

comparator
11
Study of Flip Flops (RS, JK and

D-types)
12
Study of Shift Registers in various Mode of

operation
13
Design and implementation of Ring and

Johnson Counters
14
Construction and Verification of 4 bit Ripple

Counter.
15
Simulation of a combinational logic using

HDL
16
Simulation of a Sequential logic using HDL
DEPARTMENT OF CSE

EXP NO.
DATE
:1
:
STUDY OF LOGIC GATES
AIM:
To study about logic gates and verify their truth tables.
APPARATUS REQUIRED:
Sl.No.
COMPONENT
SPECIFICATION
QTY
1.
Quad 2 input AND gate
IC 7408
2.
Quad 2 input OR gate
IC 7432
3.
NOT gate
IC 7404
4.
Quad 2 input NAND gate
IC 7400
5.
Quad 2 input NOR gate
IC 7402
6.
Quad 2 input X-OR gate
IC 7486
7.
3 input NAND gate
IC 7410
8.
IC Trainer kit
9.
Patch Cord
As required
THEORY:
Circuit that takes the logical decision and the process are called logic gates. Each gate has
one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal
gates. Basic gates form these gates.
AND GATE:
The AND gate performs a logical multiplication commonly known as AND function. The
output is high when both the inputs are high. The output is low level when any one of the inputs
is low.
OR GATE:
The OR gate performs a logical addition commonly known as OR function. The output is
high when any one of the inputs is high. The output is low level when both the inputs are low.
DEPARTMENT OF CSE

NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low. The
output is low when the input is high.
NAND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both inputs are
low and any one of the input is low .The output is low level when both inputs are high.
NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low.
The output is low when one or both inputs are high.
X-OR GATE:
The output is high when any one of the inputs is high. The output is low when both the
inputs are low and both the inputs are high.
AND GATE:
SYMBOL:
PIN DIAGRAM:
DEPARTMENT OF CSE

OR GATE:
SYMBOL:
PIN DIAGRAM:
NOT GATE:
SYMBOL:
PIN DIAGRAM:
DEPARTMENT OF CSE

XOR GATE :
SYMBOL :
PIN DIAGRAM :
2-INPUT NAND GATE:

SYMBOL:
PIN DIAGRAM:
DEPARTMENT OF CSE

3-INPUT NAND GATE
SYMBOL:
PIN DIAGRAM:
NOR GATE:
SYMBOL:
PIN DIAGRAM:
DEPARTMENT OF CSE

PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION& OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the functions of all logic gates are studies and verified.
DEPARTMENT OF CSE

EXP NO.
DATE
:2
:
VERIFICATION OF DEMORGANS THEOREM
AIM:
To study and verification of DeMorgans theorems using basic logic gates.
APPARATUS REQUIRED:
Sl.No.
COMPONENT
SPECIFICATION
QTY
1.
IC 7408
2.
IC 7432
3.
NOT gate
IC 7404
4.
IC Trainer kit
5.
Patch Cord
As required
THEORY:
DeMorgans suggested tow theorems that form an important part of Boolean
algebra. In the equation form, they are:

1) AB = A + B
The complement of a product is equal to the sum of the complements.

2) A+B = A.B
The complement of a sum is equal to the product of the complements.
DEPARTMENT OF CSE

CIRCUIT DIAGRAM:
Truth Table
1) AB = A + B
2) A+B = A.B
DEPARTMENT OF CSE

PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the Demorgans Theorem is designed and implemented and the output
is verified.
DEPARTMENT OF CSE

EXP NO.
:3
DATE
:
STUDY OF ADDERS AND SUBTRACTORS
AIM:
To study by design and construct half adder, full adder, half subtractors and full
subtractors circuits and verify their truth tables using logic gates.
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
4.
3.
4.
COMPONENT
Hex 1 input NOT gate
IC Trainer kit
Patch Cords
SPECIFICATION
IC 7408
IC 7486
IC 7404
IC 7432
-
QTY.
1
1
1
1
1
As required
THEORY:
HALF ADDER:
A half adder is a combinational circuit needs two binary inputs and two binary outputs.
The input variables designate the augend and addend bits, the output variables produce the sum
and carry. The half-adder can be implemented with an exclusive OR and an AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it consists
of three inputs and two outputs. A full adder is useful to add three bits at a time. In full adder
sum output will be taken from X-OR Gate, carry output will be taken from OR Gate.
HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half subtractor has
two input and two outputs. The outputs are difference and borrow. The difference can be applied
using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter.
DEPARTMENT OF CSE
FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor
the logic circuit should have three inputs and two outputs. The two half subtractor put together
gives a full subtractor .The first half subtractor will be C and A B. The output will be difference
output of full subtractor. The expression AB assembles the borrow output of the half subtractor
and the second term is the inverted difference output of first X-OR.
HALF ADDER
TRUTH TABLE:
K-Map for SUM:
SUM = AB + AB
=
K-Map for CARRY:
CARRY = AB
DEPARTMENT OF CSE
LOGIC DIAGRAM:
FULL ADDER
FULL ADDER USING TWO HALF ADDER:
TRUTH TABLE:
K-Map for SUM:
K-Map for CARRY:
DEPARTMENT OF CSE

SUM = ABC + ABC + ABC + ABC
= C(AB+AB) + C(AB+AB)
=
CARRY = AB + BC + AC
LOGIC DIAGRAM:
HALF SUBTRACTOR
TRUTH TABLE:
K-Map for DIFFERENCE:
DIFFERENCE = AB + AB
=
K-Map for BORROW:
BORROW = AB
DEPARTMENT OF CSE

LOGIC DIAGRAM:
FULL SUBTRACTOR
TRUTH TABLE:
K-Map for Difference:
Difference = ABC + ABC + ABC + ABC

= A (BC+BC) +A (BC+BC)
K-Map for Borrow:
Borrow = AB + BC + AC
DEPARTMENT OF CSE

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:
PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the Combinational circuit for Adder/Subtractor is designed and

implemented and the output is verified.
DEPARTMENT OF CSE

EXP NO.
:4
DATE
:
DESIGN AND IMPLEMENTATION OF CODE CONVERTOR I
AIM:
To design and implement 4-bit
(i)
Binary to gray code converter
(ii)
Gray to binary code converter
APPARATUS REQUIRED:
Sl.No
COMPONENT
1.
2.
IC trainer kit
3.
Patch Cords
SPECIFICATION
IC 7486
-
QTY.
1
1
As required
THEORY:
Code is a symbolic representation of discrete information. Codes are of different types.
Gray Code is one of the most important codes. It is a non-weighted code which belongs to a
class of codes called minimum change codes. In this codes while traversing from one step to
another step only one bit in the code group, changes. In case of Gray Codetwo adjacent code
numbers differs from each other by only one bit. The idea of it can be cleared from the table
given below. As this code it is not applicable in any types of arithmetical operations but it has
some applications in analog to digital converters and in some input/output devices.
Binary to gray code conversion
Binary to gray code conversion is a very simple process. There are several steps to do this
types of conversions. Steps given below elaborate on the idea on this type of conversion.
(1) The M.S.B. of the gray code will be exactly equal to the first bit of the given binary number.
(2) Now the second bit of the code will be exclusive-or of the first and second bit of the given
binary number, i.e if both the bits are same the result will be 0 and if they are different the result
will be 1.
(3)The third bit of gray code will be equal to the exclusive-or of the second and third bit of the
given binary number. Thus the Binary to gray code conversion goes on.
Gray code to binary conversion
Gray code to binary conversion is again very simple and easy process. Following steps can make
your idea clear on this type of conversions.
(1) The M.S.B of the binary number will be equal to the M.S.B of the given gray code.
DEPARTMENT OF CSE

(2) Now if the second gray bit is 0 the second binary bit will be same as the previous or the first
bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0 and if it was 0 it will
be 1.
(3) This step is continued for all the bits to do Gray code to binary conversion.
BINARY TO GRAY CODE CONVERTOR
TRUTH TABLE:
DEPARTMENT OF CSE

K-Map for G3:
K-Map for G2:
G3 = B3
K-Map for G1:
G1= B2B1+ B2B1
K-Map for G0:
G0= B1B0+B1B0
DEPARTMENT OF CSE

LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR

TRUTH TABLE:
DEPARTMENT OF CSE

K-Map for B3:
B3 = G3
K-Map for B1:
B1 = G3 G2 G1
K-Map for B2:
B2= G3G2+G3G2
K-Map for B0:
B0 = G3 G2 G1 G0
DEPARTMENT OF CSE
LOGIC DIAGRAM:
PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the Combinational circuit for Code Converter-I is designed and

DEPARTMENT OF CSE

EXP NO.
:5
DATE
:
DESIGN AND IMPLEMENTATION OF CODE CONVERTOR -II
AIM:
To design and implement 4-bit
i)
BCD to excess-3 code converter
ii)
Excess-3 to BCD code converter
APPARATUS REQUIRED:
Sl.No
COMPONENT
1.
2.
3.
4.
Hex 1 input NOT gate
5.
IC trainer kit
6.
Patch ords
SPECIFICATION
IC 7486
IC 7408
IC 7432
IC 7404
-
QTY.
1
1
1
1
1
As required
THEORY:
Binary Coded Decimal (8-4-2-1):
BCD is an abbreviation for binary-coded-decimal. BCD is a numeric code in which each digit of
a decimal number is represented by a separate group of bits. The most common BCD code is 84-2-1 BCD, in which each decimal digit is represented by a 4-bit binary number. It is called 8-42-1 BCD because the weights associated with 4-bits are 8-4-2-1 from left to right. This means
that, bit 3 has weight 8, bit 2 has weight 4, bit 1 has weight 2 and bit 0 has weight 1.
In multi digit coding, each decimal digit is individually coded with 8-4-2-1BCD code.
For example, 58 in decimal can be encoded in 8-4-2-1 BCD as:
Decimal: 58
8-4-2-1 BCD:
0101
1000
When we represent the same number (58) in binary:1110102, we require only 6

digits. This means that, for representing numbers 8-4-2-1 BCD is less efficient than pure binary
number system. The advantage of a BCD code is that it is easy to convert between it and
decimal. The principle disadvantage of a BCD, besides its low efficiency, is that arithmetic
operations are more complex than they are in pure binary.
DEPARTMENT OF CSE

Excess-3 code:
Excess-3 code is a modified form of a BCD number. The excess-3 can be derived from the
natural BCD code by adding 3 to each coded number. For example, decimal 12 can be
represented in BCD as 0001 0010. Now adding 3 to each digit we get Excess-3 code as 0100
0101 (12 in decimal)
TRUTH TABLE:
BCD TO EXCESS-3 CONVERTOR
DEPARTMENT OF CSE

K-Map for E3:
K-Map for E2:
E3 = B3 + B2 (B0 + B1)
K-Map for E1:
K-Map for E0:
DEPARTMENT OF CSE

LOGIC DIAGRAM:
TRUTH TABLE:
Excess-3 to BCD
DEPARTMENT OF CSE

K-Map for A:
K-Map for B:
A = X1 X2 + X3 X4 X1
K-Map for C:
K-Map for D:
DEPARTMENT OF CSE
LOGIC DIAGRAM:
PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the Combinational circuit for Code Converter-II is designed and

DEPARTMENT OF CSE
EXP NO.
DATE :
:6
IMPLEMENTATION OF BOOLEAN FUNTIONS USING NAND/NOR LOGIC
AIM:
To simplify the Boolean expressions and implement the circuit using
Logic Gates & Universal Logic Gates.
APPARATUS REQUIRED:
Sl No. COMPONENT
SPECIFICATION QTY
Quad 2 input NAND gate
IC 7400
Quad 2 input NOR gate
IC 7402
IC Trainer kit
Patch Cord
As required
THEORY:
NAND-NAND implementation
The rules for obtaining the NAND-NAND logic diagram from a Boolean function as follows:
(1) Simplify the given Boolean function and express it in sum of product form(SOP form)
(2) Draw a NAND gate for each product term of the function that has two or more literals. The
inputs to each NAND gate are the literals of the term. This constitutes a group of first level gates.
(3) If Boolean function includes any single literal or literals draw NAND gate for each single
literal and connect corresponding literal as an input to the NAND gate.
(4) Draw a single NAND gate in the second level, with input coming from outputs of first level
gates.
NOR-NOR implementation
The rules for obtaining the NOR-NOR logic diagram from a Boolean function as follows:
(1) Simplify the given Boolean function and express it in product of sum form(POS form)
(2) Draw a NOR gate for each product term of the function that has two or more literals. The
inputs to each NOR gate are the literals of the term. This constitutes a group of first level gates.
DEPARTMENT OF CSE

(3) If Boolean function includes any single literal or literals draw NOR gate for each single
literal and connect corresponding literal as an input to the NOR gate.
(4) Draw a single NOR gate in the second level, with input coming from outputs of first level
gates.
LOGIC DIAGRAM OF NAND NAND IMPLEMENATION:
Y = ABC + DE + F
AND OR
NAND Bubbled OR
NAND NAND
LOGIC DIAGRAM OF NOR - NOR IMPLEMENATION:
F= (A + B)C
DEPARTMENT OF CSE
PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the Boolean expressions and implement the circuit using Logic Gates & Universal
Logic Gates are studies and verified.
DEPARTMENT OF CSE

EXP NO.
DATE :
:7
DESIGN AND IMPLEMENTATION OF PARITY GENERATOR AND CHECKER

AIM:
To design and verify a combinational logic circuits of a 3 bit parity generator and checker.
APPARATUS REQUIRED :
Sl No. COMPONENT
SPECIFICATION QTY
IC 7486
IC trainer kit
Patch cord
As required
THEORY:
Parity is used for purpose of detecting errors and transmission of binary information. A
parity bit is an extra bit included with a binary message to make the number of 1s either odd or
even. The message including the parity bit is transmitted and then checked out the receiving end
for errors. An errors is detected if the checked parity does not correspond with the one
transmitted. The circuit generator the parity bit in the transmitted is called a parity generator.
The digital information is in binary form. If it is transmitted from one digital system to
another system an error may occur due to transients, noise and other disturbances. This means a
signal corresponding to a may change to 1 or vice versa. To catch these errors, a parity bit(0 or1)
is usually transmitted along with the original bits. The circuit used for generating parity bit is
called parity generator.
TRUTH TABLE:
Inputs
A
Outputs
C
ODD PARITY(PO)
EVEN PARITY(PE)
DEPARTMENT OF CSE
K- MAP FOR EVEN PARITY
PE=
K- MAP FOR ODD PARITY
PO=
DEPARTMENT OF CSE

LOGIC DIAGRAM:
PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the Combinational circuit for Parity checker and generator is designed
and implemented and the output is verified.
DEPARTMENT OF CSE

EXP NO.
:8
DATE :
DESIGN AND IMPLEMENTATION OF SIMPLIFIED BOOLEAN EXPRESSION
USING MULTIPLEXER
AIM:
To study, design and implementation of multiplexer using logic gates.
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
2.
3.
COMPONENT
3 input AND gate
OR gate
NOT gate
IC trainer kit
Patch cords
SPECIFICATION
IC 7411
IC 7432
IC 7404
-
QTY.
2
1
1
1
As required
THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally there are 2 n input line and
n selection lines whose bit combination determine which input is selected.
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:
DEPARTMENT OF CSE
FUNCTION TABLE:
Select inputs
S1
S0
Data inputs
D0
D1
D2
Output
D3
Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0
CIRCUIT DIAGRAM FOR MULTIPLEXER:
DEPARTMENT OF CSE

TRUTH TABLE:
INPUTS
Y1
Y2
Y3
Y4
OUTPUTS
Y5
Y6
Y7
PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the Combinational circuit for Multiplexer is designed and

DEPARTMENT OF CSE

EXP NO.
:9
DATE :
DESIGN AND IMPLEMENTATION OF SIMPLIFED BOOLEAN EXPRESSIONS
USING DECODERS
AIM:
To study, design and implement decoder using logic gates.
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
2.
3.
COMPONENT
3 input NAND gate
OR gate
NOT gate
IC trainer kit
Patch cords
SPECIFICATION
IC 7410
IC 7432
IC 7404
-
QTY.
2
3
1
1
As required
THEORY:
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded input
into coded output where input and output codes are different. The input code generally has fewer
bits than the output code. Each input code word produces a different output code word i.e there is
one to one mapping can be expressed in truth table. In the block diagram of decoder circuit the
encoded information is present as n input producing 2n possible outputs. 2n output values are
from 0 through out 2n 1.
TRUTH TABLE:
INPUT
E
OUTPUT
B
D0
D1
D2
D3
DEPARTMENT OF CSE
LOGIC DIAGRAM FOR DECODER:
PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the design and implementation of simplified Boolean expressions using decoders
are studies and verified.
DEPARTMENT OF CSE

EXP. NO: 10
DATE :
DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR
AIM:
To design and implement
(i)
2 bit magnitude comparator using basic gates.
(ii)
8 bit magnitude comparator using IC 7485.
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
4.
5.
6.
7.
COMPONENT
AND gate
X-OR gate
OR gate
NOT gate
4-bit magnitude
comparator
IC trainer kit
Patch cords
SPECIFICATION
IC 7408
IC 7486
IC 7432
IC 7404
IC 7485
QTY.
2
1
1
1
2
1
As required
THEORY:
The comparison of two numbers in an operation that determines if one number is greater
that, less than or equal to the other number. A magnitude comparator is combinational circuits
that compares the two number A and B, and determine their relative magnitudes. The outcome of
the comparison is specified by three binary variables that indicate whether A>B, A=B or A<B.
The circuit for comparing two n-bit numbers has 2n entries in the truth table and becomes
other hand as one may suspect a comparator circuit possess a certain amount of regularity.
Digital functions which possess on inheriting well defined regularity can usually are designed by
mean of an algorithmic procedure if one is found to exist.
An algorithm is a procedure that specifies a finite set of steps which if followed give the
solution to the problem. The algorithm is a direct application of the procedure a person uses to
compare the relative magnitude of the two numbers. Consider two number A and B. Write the
co-efficient of the number with descending significance as follows:
DEPARTMENT OF CSE

A = A1A0
B = B1B0
The two numbers are equal i.e., if A1 = B1 and A0 = B0. The equality of the two
numbers a and B is displayed in a combinational circuit by an output binary variable which we
designate is equal to 1. If the input numbers, A and B are equal and its equal to 0 otherwise. For
equality conditions to exist, all xi variables must be equal to 1.
Xi = AiBi +AiBi[I = 0,1]. If the two digit are equal we compare the next lower
siginificant pair of digits. This comparison continues until a pair of unequal digits is reached.
If the corresponding digit of A is 1 and B is 0, we conclude that A>B. if the
corresponding digit of A is 0 and Bis 1.
(A>B) = A1B1+A0B1B0 + A1A0B0
(A<B) = A1B1 + A1B0A0 + A0A1B0
TRUTH TABLE:
A1
Inputs
A0 B1
B0
A>B
Outputs
A=B
A<B
DEPARTMENT OF CSE

PIN DIAGRAM FOR IC 7485:
LOGIC DIAGRAM:
8-BIT MAGNITUDE COMPARATOR:
DEPARTMENT OF CSE

TRUTH TABLE:
A
0000 0000
0001 0001
0000 0000
B
0000
0000
0001
A>B
A=B
A<B
0000
0000
0001
PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the design and implementation Magnitude comparator is studied and verified
DEPARTMENT OF CSE

EXP. NO: 11
DATE :
STUDY OF FLIP-FLOPS
AIM:
To verify the characteristic table of RS, JK and D Flip flops.
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
4.
6.
COMPONENT
Digital IC trainer kit
D-Flipflop
JK-Flipflop
NAND gate
Connecting wires
SPECIFICATION
QTY.
1
1
1
1
As required
IC 7474
IC 7476
IC 7400
THEORY:
A Flip Flop is a sequential device that samples its input signals and changes its output
states only at times determined by clocking signal. Flip Flops may vary in the number of inputs
they possess and the manner in which the inputs affect the binary states.
RS FLIP FLOP:
The clocked RS flip flop consists of NAND gates and the output changes its state with respect to
the input on application of clock pulse. When the clock pulse is high the S and R inputs reach
the second level NAND gates in their complementary form. The Flip Flop is reset when the R
input is high and S input is low. The Flip Flop is set when the S input is high and R input is
low. When both the inputs are high the output is in an indeterminate state.
D FLIP FLOP:
To eliminate the undesirable condition of indeterminate state in the SR Flip Flop when both
inputs are high at the same time, in the D Flip Flop the inputs are never made equal at the same
time. This is obtained by making the two inputs complement of each other.
DEPARTMENT OF CSE

JK FLIP FLOP:
The indeterminate state in the SR Flip-Flop is defined in the JK Flip Flop. JK inputs behave like
S and R inputs to set and reset the Flip Flop. The output Q is ANDed with K input and the clock
pulse, similarly the output Q is ANDed with J input and the Clock pulse. When the clock pulse
is zero both the AND gates are disabled and the Q and Q output retain their previous
values. When the clock pulse is high, the J and K inputs reach the NOR gates. When both the
inputs are high the output toggles continuously. This is called Race around condition and this
must be avoided.
RS FLIP FLOP
LOGIC SYMBOL:
CIRCUIT DIAGRAM:
DEPARTMENT OF CSE

CHARACTERISTIC TABLE:
CLOCK
PULSE
1
2
3
4
5
6
7
8
INPUT
S
PRESENT
STATE (Q)
NEXT
STATE(Q+1)
D FLIP FLOP
PIN DIAGRAM:
DEPARTMENT OF CSE

CLOCK
PULSE
INPUT (D)
OUTPUT (Q)
JK FLIP FLOP
PIN DIAGRAM:
DEPARTMENT OF CSE

CLOCK
PULSE
0
0
0
0
1
1
1
1
INPUTS
J
OUTPUT(Q)
K
PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the function of all the flip-flops is studies and verified.
DEPARTMENT OF CSE

EXP. NO: 12
DATE :
DESIGN AND IMPLEMENATION OF Serial Input Parallel Output (SIPO) and Parallel
Input Serial Output (PISO) Shift Register.
AIM:
To study and implement shift register in various modes of operation
(i)
(ii)
Serial in parallel out (SIPO)

Parallel in serial out (PISO
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
4.
COMPONENT
D flip flop
OR gate
IC Trainer kit
Patch cords
SPECIFICATION
IC 7474
IC 7432
-
QTY.
2
1
1
As required
THEORY:
SHIFT REGISTER:
The Shift Register is another type of sequential logic circuit that is used for the storage or
transfer of data in the form of binary numbers and then "shifts" the data out once every clock
cycle, hence the name "shift register". It basically consists of several single bit "D-Type Data
Latches", one for each bit (0 or 1) connected together in a serial or daisy-chain arrangement so
that the output from one data latch becomes the input of the next latch and so on.
The data bits may be fed in or out of the register serially, i.e. one after the other from
either the left or the right direction, or in parallel, i.e. all together. The number of individual data
latches required to make up a single Shift Register is determined by the number of bits to be
stored with the most common being 8-bits (one byte) wide, i.e. eight individual data latches. The
individual data latches that make up a single shift register are all driven by a common clock
(Clk) signal making them synchronous devices.
DEPARTMENT OF CSE

Shift register IC's are generally provided with a clearor reset connection so that they
can be "SET" or "RESET" as required. Generally, shift registers operate in one of four different
modes with the basic movement of data through a shift register being:
Serial-in to Parallel-out (SIPO):

The register is loaded with serial data, one bit at a time, with the stored data being
available in parallel form.
Parallel-in to Serial-out (PISO):

The parallel data is loaded into the register simultaneously and is shifted out of the
register serially one bit at a time under clock control.
PIN DIAGRAM:
DEPARTMENT OF CSE

LOGIC DIAGRAM:
SERIAL IN PARALLEL OUT:
TRUTH TABLE:
Parallel Outputs
CLK
Serial
QA
QB
QC
QD
inputs
DEPARTMENT OF CSE

LOGIC DIAGRAM:
PARALLEL IN SERIAL OUT:
TRUTH TABLE:
Parallel Inputs
CLK
Q3
Q2
Q1
Serial
Q0
Output
DEPARTMENT OF CSE

PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the function of sequential circuits for SIPO & PISO are studied and verified by
truth table.
DEPARTMENT OF CSE

EXP. NO: 13
DATE :
DESIGN AND IMPLEMENTATION OF RING AND JOHNSON COUNTERS
AIM:
To design and implement Ring and Johnson counters.
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
COMPONENT
D-Flip-flop
IC Trainer Kit
Patch Cords
SPECIFICATION
IC 7474
-
QTY.
4
1
As required
THEORY:
COUNTERS:
A shift register counter is basically a shift register with the serial output connected back to the
serial input to produce special sequences. These devices are often classified as counters because
they exhibit a specified sequence of states. Two of the most common types of shift register
counters, the Johnson counter and the ring counter.
RING COUNTERS:
A ring counter is basically a circulating shift register in which the output of the most significant
stage is fed back to the input of the least significant stage. The 4-bit ring counter is constructed
from D flip-flops. The output of each stage is shifted into the next stage on the positive edge of a
clock pulse. If the CLEAR signal is high, all the flip-flops except the first one FF0 are reset to
0. FF0 is preset to 1 instead.
Since the count sequence has 4 distinct states, the counter can be considered as a mod-4
counter. Only 4 of the maximum 16 states are used, making ring counters very inefficient in
terms of state usage. But the major advantage of a ring counter over a binary counter is that it is
self-decoding. No extra decoding circuit is needed to determine what state the counter is in.
DEPARTMENT OF CSE

JOHNSON COUNTERS:
Johnson counters are a variation of standard ring counters, with the inverted output of the last
stage fed back to the input of the first stage. They are also known as twisted ring
counters. An n-stage Johnson counter yields a count sequence of length 2n, so it may be
considered to be a mod-2ncounter.
LOGIC DIAGRAM:
RING COUNTER:
TRUTH TABLE:
Clock Pulse
Q0
Q1
Q2
Q3
DEPARTMENT OF CSE

LOGIC DIAGRAM:
JOHNSON COUNTER:
TRUTH TABLE:
Clock Pulse
Q0
Q1
Q2
Q3
DEPARTMENT OF CSE

PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the sequential circuit for Johnson and Ring counters are studied and verified by
truth table.
DEPARTMENT OF CSE

EXP. NO: 14
DATE :
CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER
AIM:
To design and verify 4 bit ripple counter.
APPARATUS REQUIRED:
Sl.No.
1.
2.
3.
4.
COMPONENT
JK flip flop
NAND gate
IC trainer kit
Patch cords
SPECIFICATION
IC 7476
IC 7400
-
QTY.
2
1
1
As required
THEORY:
A counter is a register capable of counting number of clock pulse arriving at its clock
input. Counter represents the number of clock pulses arrived. A specified sequence of states
appears as counter output. This is the main difference between a register and a counter. There are
two types of counter, synchronous and asynchronous. In synchronous common clock is given to
all flip flop and in asynchronous first flip flop is clocked by external pulse and then each
successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second
stage is triggered by output of first stage. Because of inherent propagation delay time all flip
flops are not activated at same time which results in asynchronous operation.
DEPARTMENT OF CSE
PIN DIAGRAM FOR IC 7476:
LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:
DEPARTMENT OF CSE

TRUTH TABLE:
4 BIT RIPPLE COUNTER:
CLK
QA
QB
QC
QD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DEPARTMENT OF CSE

PROCEDURE:
1.
2.
3.
4.
5.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the above experiment is studied and verified by truth table.
DEPARTMENT OF CSE

EXP. NO: 15
DATE :
SIMULATION OF COMBINATIONAL LOGIC USING HDL
AIM:
To write Verilog code to describe the functions of a full adder.
TOOLS REQUIRED:
SL No.
COMPONENT
1.
Desktop PC with
2.
Altera Quartus EDA tool
SPECIFICATION
QTY
P IV processor, 1GB RAM with good

configuration
Version above 7.0
TRUTH TABLE:
A
CARRY SUM
Verilog code for Full adder
DEPARTMENT OF CSE
SIMULATED TIMING WAVEFORM:
PROCEDURE:
1.
2.
3.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
The full adder has been realized and simulated using Verilog codes.
DEPARTMENT OF CSE

EXPT NO: 16
DATE :
SIMULATION OF SEQUENTIAL LOGIC USING HDL
AIM:
To develop the Verilog codes for the following flip-flops: D, J-K, T Flip-Flops.
TOOLS REQUIRED:
SL No.
1.
2.
COMPONENT
Desktop PC with
Altera Quartus EDA tool
SPECIFICATION
QTY
P IV processor, 1GB RAM with good

configuration
Version above 7.0
TRUTH TABLE:
D-FLIP FLOP:
DEPARTMENT OF CSE

J-K FLIP FLOP:
T FLIP FLOP:
Verilog code for JK flip flop
DEPARTMENT OF CSE
DEPARTMENT OF CSE

Verilog code for D flip flop:
Verilog code for T flip flop:
DEPARTMENT OF CSE
PROCEDURE:
1.
2.
3.
MAX MARKS
AIM & PROCEDURE
DIAGRAMS &
MARKS OBTAINED
5
5
TRUTH TABLES
CONNECTION & OUTPUT
VIVA
5
TOTAL
20
RESULT:
Thus the D, J-K, T-Flip Flop has been implemented and realized using Verilog codes.
DEPARTMENT OF CSE

DSD - Lab Observation PDF

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SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

DEPARTMENT OF COMPUTE SCIENCE AND ENGINEERING

Name of the student : ________________________________

P a g e |1 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

DIGITAL DESIGN LABORATORY

4. Design and implementation of Carry Look-Ahead Adders.

P a g e |2 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

SECOND CYCLE EXPERIMENTS

P a g e |3 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

NAME OF THE EXPERIMENT

Study of logic gates

Verification of DeMorgans theorems

Study and implementation of adders and

Design and implementation of code converters

Design and implementation of code converters

Design of Parity Generator

Design and implementation of magnitude

Study of Flip Flops (RS, JK and

Study of Shift Registers in various Mode of

Design and implementation of Ring and

Construction and Verification of 4 bit Ripple

Simulation of a combinational logic using

Simulation of a Sequential logic using HDL

P a g e |4 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

Quad 2 input AND gate

Quad 2 input OR gate

Quad 2 input NAND gate

Quad 2 input NOR gate

Quad 2 input X-OR gate

3 input NAND gate

P a g e |5 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

P a g e |6 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

P a g e |7 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

2-INPUT NAND GATE:

P a g e |8 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

P a g e |9 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

P a g e |10 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

VERIFICATION OF DEMORGANS THEOREM

Quad 2 input AND gate

Quad 2 input OR gate

algebra. In the equation form, they are:

The complement of a product is equal to the sum of the complements.

The complement of a sum is equal to the product of the complements.

P a g e |11 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

P a g e |12 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

P a g e |13 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

P a g e |14 DIGITAL DESIGN LAB

SRI MANAKULA VINAYAGAR ENGINEERING COLLEGE

K-Map for SUM:

P a g e |15 DIGITAL DESIGN LAB