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# UEEA2333

Analogue Electronics
Topic 7

Power amplifiers

Topics
Examine the classes of power amplifiers and determine their
transfer characteristics and maximum power efficiency
Analyze various types of amplifiers used for the output stage such
as common-emitter, emitter follower, and push-pull amplifier to
determine their maximum power output and maximum power
dissipation
To learn various methods of biasing for class-AB operation
[Reference] Sedra, Smith, (2004) 5th Ed. Microelectronic Circuits,
Oxford University Press. Chapter 14.
Muhammad H. Rashid, (1999), Microelectronic Circuits: Analysis
and Design, PWS Publishing Company. Chapter 14.
Donald A. Neamen, (2007), Microelectronics Circuit Analysis and
Design, 3rd Edition, McGraw-Hill. Chapter 8.
Theodore F. Bogart, Jr. et al, (1997) 5th Ed. Electronic Devices and
Circuits, Prentice Hall. Chapter 14.
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PART 1

## Output Stage: General Requirements

Output stage refers to the part of an electronic device which
connects with an external device and sends out signal. It is
required to meet certain performance requirements.

## The output stage should provide a low output resistance, so

that output signals could be delivered to the load without
attenuation.
Linearity between the input and output signals should be
maintained, to give a low total harmonic distortion, THD.
The required signal power has to be delivered to the load
efficiently, to minimize the power loss originated from the
transistors/resistors in the stage.

## Classifications of Output Stage

The output stages of power amplifiers are classified according to
the time the output transistors are turned on (i.e. conducting):
Class A : Transistor conducts for the entire cycle of the input signal.
Class B : Transistor conducts for only half of each sine wave cycle.
Class AB: Transistor conducts for slightly more than half a cycle.
Class C : Transistor conducts for less than half a cycle.

## Class A Output Stage

The emitter follower (see right)
is the most popular class A
output stage because of a low
output resistance.
Transistor Q1 is biased with a
(fixed) current ICQ IEQ = I.
Q1 is kept on all the time (i.e.
conduction angle = 360):
I > iL(max)

I is approximately equal to IR :
(because of current mirror)
VR VCC VQ3 VCC VBE2
I IR

R
R
R

## The output voltage is :

v0 = vI VBE1
If we neglect the relatively
small changes in VBE1 for the
different load current (a
change of 60mV for every
factor of 10 change in iE1) a
linear input-output
relationship is obtained.

IR

current
mirror
7

At vo = 0, iL = 0:
IE1 = IR
At vo(max) = VCC VCE1sat : [Q1 saturate]
I E1 I R iL I R

VCC VCE1sat
RL

I E1 I R iL I R

VCC VCE2sat
RL

## Provided that IE = IR + iL > 0.

But if IE < 0, then Q1 turns off, and vo could
not go more negative and reach minimum at vo(min) = IRRL.
For maximum output swings, we need IR > iL.
Since IR = (VCC VBE2)/R, and iL = (VCC VCE2sat)/RL, therefore
RL > R (approx.), otherwise clipping will occur.

Example
Design the emitter follower. Assume
VCC
= 12 V
VCEsat = 0.5 V
VBE
= 0.7 V
IR
= 5 mA
RL
= 650 .
Assume also identical transistors of
hfe
= 100 (=)
(a) Determine the critical value of
load resistor to avoid clipping.
(b) Find the max peak-to-peak output
voltage swing if RL= 650 .
(c) Find the max peak-to-peak output
voltage swing if RL= 2.5 k.

## VCC VBE 12 0.7

a) R

2260
I
5m
b) RL ( critical) R 2260
c) For RL 650,
v0 max I R RL 5m(650) 3.25 V
v0 max VCC VCE ( sat ) 12 0.5 11.5 V
peak - to - peak voltage swing will be from - 3.25 V

10

Example
For the emitter follower in figure,
VCC
= 15V
VCEsat = 0.2 V
VBE
= 0.7 V (constant)
is very high.
Find the value of R that will
establish a bias current sufficiently
large to allow the largest possible
output signal swing for RL= 1 k.
Determine the resulting output
signal swing and the minimum and
maximum emitter currents.
Ans. 0.97k; -14.8 V to +14.8 V; 0
to 29.6 mA
11

## Class A Signal Waveforms

(neglect VCEsat)

vCE1 = VCC v0
iL(max) = VCC/RL IR
pQ1 = vCE1 iC1
IR =

12

## Let the output be sinusoidal vo = Vmsint and iL= vo / RL

Instantaneous power dissipation in Q1 is
pQ1
= vCE1 iC1
= (VCC Vmsint) (IR + Vm sint / RL)
= VCCIR + VCCVmsint/RL VmIRsint Vm2sin2t/RL
= VCCIR + (VCCVm/RL VmIR)sint Vm2sin2t/RL
From the above, we may determine the average power dissipation as
pQ1(ave) = VCC IR Vm2/RL
The negative term means some of the power goes through RL.
1) The minimum average power is VCC IR, when the output swing
is maximum (i.e. Vm VCC).
2) The maximum average power is VCC IR, when RL = or Vm = 0
(i.e. the negative term disappears). Q1 must be designed (i.e.
select a transistor with the proper power rating) to withstand this
value (i.e. maximum average power) continuously.
13

## Consider the instantaneous power dissipation of Q1

1) If RL = (open circuit)
iC1 = IR is constant, and the maximum power dissipation will occur
when v0 = VCC , so PQ1 = 2VCC IR. But, this condition would not
typically persist for a prolonged time, so the design need not be that
conservative.
2) If RL = 0 (short circuit)
Output short circuit theoretically results in infinite load current,
therefore a very large current would flow through Q1 and may burn
it up (thus Q1 requires some short-circuit protection circuitry).
The power dissipation in Q2 is
pQ2
= vCE2 iC2
= (VCCsint + VCC) IR
Use this average value for design
pQ2(ave) = VCC IR
purpose (i.e. select the transistor with
pQ2(max) = 2VCC IR
this power rating), since the maximum
dissipation will not last for a long time

14

Example
Consider the emitter follower
shown, with
VCC
= 10 V
I
= 100 mA
RL
= 100
Find the power dissipated in Q1
and Q2 under quiescent conditions
(i.e. v0 = 0). For a sinusoidal output
voltage of maximum possible
amplitude (neglecting VCEsat), find
the average power dissipation in
Q1 and Q2. Also find the load
power.
Ans. 1 W, 1W, 0.5W, 1W, 0.5W
15

## Class A: Power Conversion Efficiency

The power conversion efficiency is defined as
= PL / PS
where PL = The (average) load power (i.e. output power)
PS = The (average) supply power (i.e. total power)
For emitter follower, the average power consumed by the load
is PL = Vm2/RL for a sinusoidal output with peak Vm.
The average power drawn from the negative supply (through
Q2) is VCC I (because IC2 I IR and is constant).
The average power drawn from the positive supply (through Q1
and the load) is VCC I (try to verify it, i.e. PQ1 + PL).
Note, PS = PQ1 + PQ2 + PL. This gives,

1 Vm2
1 Vm Vm

(
)(
)
4 IRLVCC
4 IRL VCC
16

Since Vm VCC and Vm IRL, max efficiency is reached at Vm= VCC= IRL
(i.e. when Vm and iL reach maximum). This gives max = = 25%.
Because 25% is low, class A output stage is rarely used in large-power
applications (for more than 1 W). Furthermore, in practice the output is
limited to a lower level in order to avoid transistor saturation and the
associated nonlinear distortions. Thus, in practice, 10% to 20%.
The maximum average (load) output power is VCC I /2 when Vm VCC.
The maximum average power dissipation per transistor is VCC I.
A figure of merit is given by the ratio of maximum (average) power
dissipation per transistor to the maximum (average) load power

PD max
Fm
2
PL max
The transistor power dissipation is twice the maximum output power e.g.
for a maximum load of 50 W, the transistor must be rated at least 100 W.
It necessitates the use of a large and expensive heat sink to cool the
17
transistors.

## Class A Common-Emitter Amplifier

Consider the basic common
emitter amplifier.
This configuration lacks
biasing stability and is not
suitable for power
amplifier.
To simplify calculation,
assume that the
nonlinearity introduced by
the transistor is negligible,
so the output signals will
be sinusoidal for sinusoidal
input signals.
18

19

## The input voltage is related to the collector current IC by

iC
vI VBE VT ln
IS
The output voltage is

vI vBE

iC
VT ln
IS

vI
vO VCC RCiC VCC RC I S exp
VT

20

## The average power from power supply PS = VCCICQ

The average load or output power using peak values of output
signals is given by
2
V
I
V
I
I
R
I
I
p p
p p
p L p
p RL

PL

2
2
2
2 2

characteristics

Vp
Ip

2
I Cmax I Cmin
2

21

## To evaluate extending across full range,

Vp I p 1 VCE max VCE min I C max I C min
PL

2
2
2
2
VCE max VCE min I C max I C min

8
The maximum load power is delivered when,
VCE min 0, I C min 0,
PL max

CE max

## VCE min I Cmax I Cmin

8
VCC 02 I CQ 0 VCC I CQ

8
4

max

PL max
PS

100%

VCC I CQ
4 VCC I CQ

100% 25%
22

## The maximum power dissipation of transistor occurs during

quiescent condition, given by

PC max

VCC I CQ
2

Figure of merit:

Fm

PDmax
PLmax

VCC I CQ 2
VCC I CQ 4

23

Class A Transformer-Coupled
Common-Emitter Amplifier

## Standard Class A amplifier analyzed has maximum efficiency

of 25%. By using transformer-coupling, can increase
24
efficiency to 50%.

## Neglecting transformer winding resistances and assume RE is small, the

dc load line is almost vertical:

VCEQ VCC
Assuming ideal transformer, the load resistance seen at the primary
determines the ac load line

v1 av2
RL
a 2 RL
iC iL / a
'

## By correctly designing the turns ratio, we can achieve maximum

symmetrical swing in the output voltage and current (i.e. intercepts at
2ICQ and 2VCC on the graph above).
Assume VCE(min) = 0 and IC(min) = 0, the peak values of the output
voltage and current at the primary side is:

Vm

vCE (max)
2

VCC

Im

vC (max)
2

I CQ

Note, the ac load line shows that output signal swing can exceed VCC

25

## Maximum average power delivered to the load is equal to the

maximum average power delivered to the transformer primary
(take the rms power):

PL (max)

VCC I CQ
2

## Neglecting bias resistors, average supply power

PS = VCC ICQ
Thus, maximum efficiency = 50%
Power dissipation: PD = PS PL
Maximum dissipation occurs at quiescent condition:
PD(max) = VCC ICQ

Figure of merit = 2
26

Example
A transformer-coupled class A amplifier supplies an output
power of PL = 10 W to a load of RL = 4. Assume VCC = 12 V
and BJTs of hfe = 100 and VCE(sat) = 0.7 V. Determine a.
Solution:
VCE (max) 2VCC 2(12) 24 V
PD (max) Fm PL (max) 2(10) 20 W
I CQ PD (max) / VCC 20 / 12 1.67 A
RL VCC / I CQ 12 / 1.67 7.19
'

a 2 RL / RL 7.19 / 4 a 1.34
'

27

28

## Neglecting winding resistances and assuming ideal transformer:

VCEQ VCC
'
RL a 2 RL
The turns ratio is designed to produce maximum symmetrical
swing in the output current and voltage
Assume maximum amplitude of signal VCC and ICQ. Take the rms
power,
PL(max) = VCC ICQ
The supply supplies a constant VCC across the output stage (which
includes Q and the primary winding of the transformer) with a
sinusoidal current centered at ICQ. Neglecting power consumed in
the biasing resistors, the average supply power is
PS = VCC ICQ
Thus, maximum efficiency = 50%
Power dissipation is PD = PS PL
Maximum dissipation occurs at quiescent condition:
PD(max) = VCC ICQ
29
Figure of merit = 2

Example
Design a transformer-coupled emitter-follower amplifier to deliver average
power of 5 W to a load of 8 . The peak amplitude of the signal emitter
current should be not more than 0.9ICQ and the signal emitter voltage not more
than 0.9VCC, where VCC = 24 V. Assume = 100.
Solution:

Vm 2 RL PL 2(8)(5) 8.94 V
I m Vm / RL 8.94 / 8 1.12 A
Ve 0.9VCC aVm a 0.9(24) / 8.94 2.42
I e 0.9 I CQ I m / a
I CQ I m / 0.9a 1.12 / 0.9(2.42) 0.514 A

## PD (max) VCC I CQ 12(0.514) 12.3 W

Transistor must be capable of dissipatin g this power.
5/12.3 40.7%
Bias resistor values can be determined from dc analysis.

30

PART 2

31

Class B

## Each transistor conducts for

only half of a cycle (i.e.
conduction angle = 180).
During the other half of the
cycle, the other transistor
will alternatively conduct.

32

## Class B Output Stage

It consists of a
complementary pair of
transistors (pnp and npn
types) connected in series, so
that both cannot conduct at
the same time.
When the input voltage vI is
zero, both the transistors are
cut off and the output voltage
is zero, v0 = 0.

33

## For about vI > 0.5 V, QN conducts and operates as an emitter

follower. The VEB of QP will be reverse-biased by the VBE of
QN ( 0.7 V), thus QP will be cut off.
The output voltage is
v0 = vI VBEN
For a sufficiently large value of vI, QN will saturate and the
maximum output voltage is limited to vo(max) = VCC VCEN(sat).
For about vI < -0.5 V, QP turns on and acts as an emitter
follower, while QN will be cut off.
The output voltage is
v0 = vI + VEBP
For sufficiently large negative input, QP will saturate and the
max negative output is limited to vo(max) = VCC + VECP(sat).
34

## Assuming identical transistors of VBEN = VEBP = VBE, the output

voltage will be given by
vO = 0
for 0.5 V vI 0.5 V
vO = vI VBE
for vI 0.5 V, or vI 0.5 V
The interval when both QP and QN remain off is known as dead
35
zone, and crossover distortion occurs on the output.

## Class B is also known

as push-pull amplifier:
QN pushes (source)
current into the load
when vI is positive.
QP pulls (sink)
current from load
when vI is negative.

Push

Pull

36

## Class B: Power Conversion Efficiency

For simplicity, we neglect cross-over distortion and consider
the case of an output sinusoid of peak amplitude Vm.
The average output load power is:
2

Vm 1
Vm2

PL

2 RL 2 RL
The current flows from each of the (positive/negative) rail
through BJT and load (in series), and finally returns to the
ground -- This complete path has a voltage drop V = VCC.
The current drawn from each supply consists of a half sine
wave with a peak value Im = Vm/RL. Then, the average value is:

I C ( ave)

1
ic dt
2

Im

Vm
I m sin tdt

RL
37

From symmetry, the total power drawn from the supply should
be 2 V IC(ave), giving:

PS 2VCC

Vm

RL

4 VCC
m

## The maximum efficiency is obtained when Vm reaches

maximum, limited by transistor saturation, VCC VCEsat VCC.
So, substituting Vm VCC gives:

max

78.5%
38

## Class B: Power Dissipation

Unlike class A stage, which dissipates max power under
quiescent (vo = 0), the quiescent power dissipation of class B is 0.
When an input signal is applied, the average power dissipated is,
2 Vm
1 Vm2
PD PS PL
Vcc
RL
2 RL
The worst-case (i.e. maximum) average power dissipation is,
dPD
2 V CC Vm
2

0 Vm P
VCC
D m ax
dV m RL
RL

PD max

2V
2CC
RL

## (By symmetry, of PD occurs in QN and in QP)

2
VCC
PDN max PDP max 2
RL

## Each transistor must be able to

withstand this amount of power

## At the point of maximum power dissipation, = 50%.

39

The plot shows the variation of power dissipation PD versus the peak
output voltage Vm:
Maximum efficiency

## Increasing Vm beyond 2Vcc/ decreases the power dissipated in the class B

stage while increasing the load power. However, this increases nonlinear
distortion as a result of approaching the saturation region of transistor,
which flattens the peaks of the output sine waveform, and should be
avoided in applications requiring low THD.
40

## The figure of merit is the ratio of maximum power dissipation

to maximum output power:
2
2
PD max VCC
VCC
2
2 /
2 0.2 20%
PL max RL 2 RL

## The power dissipation rating of the individual transistors is

only approximately 1/5 of the output power (this results in a
much smaller heat sink).
E.g. if the maximum power output is 20 W, then each
transistor would need to dissipate only 4 W.

41

## Class B: Single Supply Operation

The class B stage can be operated from a single power supply
as shown, in which case the load is capacitively coupled.

## This uses 2VCC as shown.

42

Example
It is required to design a class B output stage to deliver an
average power of 20W to an 8 load. The power supply is to
be selected such that VCC is about 5 V greater than the peak
output voltage. This avoids transistor saturation and the
associated nonlinear distortion, and allows for including shortcircuit protection circuitry. Determine the supply voltage
required, the peak current drawn from each supply, the total
supply power, and the power-conversion efficiency. Also
determine the maximum power that each transistor must be
able to dissipate safely.

43

Since

1 Vm2
PL
2 RL

## Therefore we select VCC = 23 V

Vm 17.9

2.24 A
Peak current drawn from each supply: I m
RL
8
Average power drawn from each supply: PS PS

2.24(23)

16.4 W

## Total supply power = 32.8 W

PL
20
Efficiency

100 61%
PS 32.8
2
VCC
232
PDN max PDP max 2 2 6.7 W
RL 8

44

PART 3

45

Class AB

Biased at a nonzero dc
current (which is much
smaller than the amplitude of
signal current c).

## Transistor conducts for an

interval slightly greater than
half a cycle (i.e.
180 < conduction angle << 360):
iC = IC + C sint
where,
IC < C
46

## During an interval around the zero crossing of the input

sinusoid, both transistors conduct.
Preferred choice for audio amplifiers because crossover
distortion is almost eliminated, therefore low output distortion
(close to Class A) but good efficiency and low power
dissipation (close to Class B).

47

## Class AB Output Stage

Both transistors are on at zero input. Choose VBEN = VEBP = VBB/2.
For positive vI, the output voltage vO is given by,
vO = vI + VBB/2 VBEN
which gives, vO = vI (i.e. no crossover distortion for constant VBE)

48

## For positive vO, a current iO flows through RL:

iN = iP + iO
Any increase in iN will cause a corresponding increase in VBEN.
And since VBB = VBEN + VEBP, VEBP (and hence iP) will decrease.
For a small signal vx, the base-emitter voltage vBE is given by
vBE = VBE + vx
The collector current becomes
iC ISevBE VT ISe

VBE vbe VT

ISeVBE VT e be
v

VT

## If the ac vx = 0, the average collector current becomes

iN ISe

VBEN VT

VBEN VT ln iN IS ,
iP ISeVEBP VT

VEBP VT ln iP IS

49

## Let the dc collector current be

I Q ISeVBB

2VT

VBB 2VT ln I Q IS

Thus,
VBB = VBEN + VEBP
IQ
iN
iP
2VT ln VT ln VT ln
IS
IS
IS
iN iP
VT ln
IS IS
2

IQ
iN iP
ln ln
IS
IS IS
I Q2 iN iP iN iN iO iN2 iNiO

50

## Class AB stage operates in much the same manner as the class

B, except that for small vI, both the transistors conduct and as vI
is increased or decreased one of the transistors takes over (i.e.
dominates) the operation.
Since the transition is smooth, crossover distortion will be
almost totally eliminated.
The power relationships in the class AB stage are almost
identical to those of class B. The only difference is that under
quiescent conditions the class AB circuit dissipates a power of
VCC IQ per transistor.
Since IQ is usually much smaller than the peak load current the
quiescent power dissipation is usually small .

51

## Class AB: Enhancement-Mode MOSFET

Assume Mn and Mp are matched, and at vI = 0, VBB/2 is applied
across vGSn and vSGn.
Quiescent drain current:
iDn iDp I DQ

VBB

K
| VT |
2

## For vI > 0, vGSn increases ,so

vO increases and Mn sources
current to the load.
Since iDn increases, vGSn
increases, so vSGp decreases
and iDp decreases.
Similarly for vI < 0.
52

Example
Consider the MOSFET class-AB output stage. Given VDD = 10
V and RL = 20 . Assuming matched transistors with K = 0.20
A/V2 and |VT|=1 V. The quiescent drain current is to be 20% of
the load current when vO = 5V. Determine the required biasing.
Solution:

iL vO / RL 5 / 20 0.25 A
So choose I DQ

VBB

0.05 K
| VT |
2

VBB / 2 1.5 V
53

## Bias voltage VBB is generated by passing a constant current Ibias

through a pair of diodes or diode-connected transistors
54

## In circuits that supply large amount of power, the output

transistors are large-sized.
The biasing diodes however need not be large devices and thus
the quiescent current IQ in QN and QP will be IQ = nIbias, where n
is the ratio of the emitter junction area of the output devices to
the junction area of the biasing diodes.
When the output stage is sourcing current to the load, iBN
increases from IQ/N (usually small) to approximately iL/ N.
This base current must be supplied by the current source Ibias
Ibias must be greater than the maximum anticipated base drive
for QN; this sets a lower limit on the value of Ibias
Since IQ = nIbias and since IQ is usually much smaller than the
peak load current (less than 10%), n cannot be a large number.
we cannot make the diodes much smaller than the output
transistors QN and QP, which is the main disadvantage of the
diode biasing circuit
55

## The important advantage is that it can provide thermal

stabilization of the quiescent current in the output stage.
Under quiescent condition, class AB transistor dissipates power
which increases its temperature.
When the temperature of a transistor rises, VBE decreases if IC is
held constant; or if VBE is held constant, IC rises.
Increase of IC increases power dissipation which, raises
temperature, further increasing IC, resulting in thermal runaway
which can lead to damage of the transistor.
Diode biasing protects against thermal runaway by being placed
in close contact with the transistor.
Diode temperature also rises by same amount, thus VBB
decreases at the same rate as VBEN + VEBP, so IQ remains
constant.

56

Example
Consider the class AB output stage under the conditions that VCC
= 15 V, RL = 100, and the output is sinusoidal with a
maximum amplitude of 10 V. Let QN and QP be matched with IS
= 10-13 A and = 50. Assume that the biasing diodes have onethird the junction area of the output devices. Find the value of
IBIAS that guarantees a minimum of 1 mA through the diodes at
all times. Determine the quiescent current and the quiescent
power dissipation in the output transistors (i.e., at vo = 0). Also
find VBB for vo=0, +10 V, and -10V.

57

## The maximum current through QN is approximately equal to,

iLmax = 10 V/0.1 k = 100 mA
Thus, the maximum base current in QN is approximately 2 mA. To
maintain a minimum of 1 mA through the diodes, we select IBIAS = 3 mA.
The area ratio of 3 yields a quiescent current of 9 mA through QN and QP.
The quiescent power dissipation is,
PDQ = 2(15)(9) = 270 mW
For vo= 0, the base current of QN is 9/51 0.18 mA, leaving a current of 3 0.18 = 2.82 mA to flow through the diodes. Since the diodes have IS = 1/3
10-13 A, the voltage VBB will be (VT = 0.025V),
VBB = 2VT ln(2.82mA/IS) = 1.26 V
At vo = +10V, the current through the diodes will decrease to 1 mA,
resulting in VBB 1.21 V. At the other extreme of vo = -10V, QN will be
conducting a very small current; thus base current will be negligibly small
and all of IBIAS (3mA) flows through the diodes, resulting in VBB 1.26V.
58

## Class AB: VBE Multiplier

If we neglect IB1,
IR1 = IR2 = IR = VBE1/R1
VBB = IR(R1+R2)
= VBE1(1+R2/R1)
The circuit multiplies
VBE1 by the factor
(1+R2/R1), which is under
the designers control and
can be used to establish
the value of VBB required
to yield a desired IQ.
59

## VBE1 depends on the portion of IBIAS that flows through the

collector of Q1

IC1 = IBIAS IR
VBE1 = VT ln(IC1/IS1)

## where we have neglected the base current of QN which is

normally small both under quiescent conditions and when the
output voltage swing is negative.
However, for positive v0, especially at and near its peak value,
the base current of QN can become sizeable and reduces the
current available for the VBE multiplier.
But large changes in IC1 correspond to only small changes in
VBE1; the difference will be mostly absorbed by Q1, leaving IR
and hence VBB almost constant. Therefore, it is fair to design
parameters taking VBE1 at quiescent condition.
Thermal stabilization of IQ can be provided if R1 = R2 and Q1 is
in close thermal contact with the output transistors.
60

Example
Redesign the output stage of the previous example (where RL =
100 , vo peaks at 10 V, = 50, and ISN = 10-13 A), utilizing a
VBE multiplier for biasing. Use a small-geometry transistor for Q1
with IS1 = 10-14 A and design for a quiescent current IC1 = 2 mA.
Ans:
The peak output current is vo(max)/RL = 100 mA.
So, the base current of QN has a maximum value of
Ib(max) = 100mA/ = 2 mA
At Ib(max), let us choose IR = IC1 = 0.5 mA (small enough to
reduce power, but big enough to keep Q1 on, and to maintain
good stability for IR).
So, IBIAS = Ib(max) + IR + IC1 = 3 mA.
Here note, IC1 could vary anything from 0.5 mA to 2.5 mA..
61

## To obtain a quiescent current of IQN = 2 mA for the output

transistor, VBB should be (where VT = 0.025 V)
I QN
2 10 3
VBB 2VT ln
2VT ln
1.19 V
13
I SN
10
So R1+ R2 is:
R1 R2

VBB 1.19

2.38 k
IR
0.5

I C1
2.5 10 3
VBE1 VT ln
VT ln
0.66 V
14
I S1
10

## The value of R1 and R2 can now be determined as

VBE1 0.66
R1

1.32 k
IR
0 .5

R2 2.38 R1 1.06 k

62

## Class AB: Darlington Configuration

In ICs, pnp transistors may have lower (5-10) while npn
transistors may have higher (200) i.e. not well matched.
Use Darlington configuration to increase gain.

i2 (1 N )iBN
(1 N ) P iBP
N P iBP
63

## Q1-Q2 sources current

to the load
Q3-Q4-Q5 sinks current
from the load
Since Q3 have low
current gain, overall
Q3-Q4-Q5 gain is
similar to that of Q1-Q2

64

PART 4

65

Class C
The transistor conducts for
an interval shorter than half
a cycle (i.e. the conduction
angle is less than 180).
Output is highly distorted.
Usually used in highpower, high-frequency
applications, such as radiofrequency transmitters.

66

67

## Transistor base is biased by a negative voltage VBB

RFC presents high impedance to high frequency input
For transistor to begin conducting, input voltage must be
vin Vc = |VBB| + VBE
Usually, amplifier is designed so that VP is just sufficient to
drive transistor into saturation
Conduction angle:
1 Vc
C 2 cos
Vp

68

## Usually a LC tank circuit is

used as the load
The tank circuit produces the
fundamental component of the
pulsed, class C waveform
which is tuned to the same
frequency as vi

f o 1 / 2 LC
It acts as a high-Q filter that
suppresses the harmonics in
the class C waveform and
passes its fundamental
69

## Ratio of peak value of the fundamental component to the peak

of the class C waveform:
r1 (3.54 4.10 C 0.0072 C ) 10 3
2

where 0 C 180

## Ratio of dc value of the class C waveform to its peak value:

C
r0
180
Output power at the fundamental frequency under maximum
drive conditions is

Po (r1 I P )VCC / 2
Average power from the supply: PS (r0 I P )VCC

Po
r1

Efficiency:
PS 2r0

70

## Figure shows Class C amplifier used to produce amplitude

modulated signal
Collector voltage is sum of VCC and a signal proportional to vs
As vs increases and decreases, so does collector voltage
Effectively the supply voltage on the collector is varying
71

Power Op Amps
Op amps have desirable
characteristics such as
high open-loop gain, high
input impedance and low
input biasing current;
however the ac output
power is low.

Class
AB

Class
A

## To obtain high power,

connect op amp output to
a class AB buffer.

72

The buffer supplies the required load current until the current
increases to the point that the voltage drop across R3 (in the
currentsourcing mode) becomes sufficiently large to turn Q5
on. Transistor Q5 then supplies the additional load current
required.
In the current sinking mode Q4 supplies the load current until
sufficiently large voltage develops across R4 to turn Q6 on.
Then Q6 sinks additional load current. Thus the stage formed
by Q5 and Q6 acts as current booster.
The power op amp is intended to be used with negative
feedback in the usual close-loop configurations.
E.g. power op-amp LH 101 is a commercially available op
amp that can provide a continuous output current of 2 A, and
with proper heat sink can provide 40 W of output power.
73