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Summary
Experienced in pre-silicon functional verification of RISC processor core with emphasis on Memory Subsystem, including multi-processor verification.
Specialties:
- Processor Core Functional Verification
- SystemVerilog based testbench component development
- Experience in VMM/OVM like methodologies for verification
Experience
Design Verification Engineer at Qualcomm
July 2013 - Present (3 years 5 months)
Design Verification Engineer at Freescale Semiconductor
August 2010 - July 2013 (3 years)
Verification of a coherent L2 cache of a multi-processor system consisting of next generation Power
Architecture cores.
Developed SystemVerilog based response checkers, monitors, interfaces, stimulus, and functional coverage
using VMM/OVM like class library and methodology.
Intern at USC Center for Systems and Software Engineering
February 2010 - August 2010 (7 months)
Research, analyze, and document various design aspects of a ruggedized computer system.
Programmer Analyst at Cognizant Technology Solutions
November 2005 - July 2008 (2 years 9 months)
Developed, tested, and maintained various web applications based on .NET Framework 2.0 technology and
MS SQL Server 2000/2005 database. Built websites based on Microsoft SharePoint Server 2007.
Languages
English
Marathi
Hindi
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Education
University of Southern California
MS, Electrical Engineering (VLSI Design), 2008 - 2009
University of Pune
Bachelor of Engineering, Electronics and Telecommunication, 2002 - 2005
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Mahesh Mandekar
Design Verification Engineer at Qualcomm
mahesh.mandekar@gmail.com
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