DEPARTMENT OF ELECTRONICS &

COMMUNICATION ENGINEERING
SEEC, Manipal University, Jaipur

LAB MANUAL

VLSI Lab. EC1531

B.Tech. (ECE) III Year, v Semester

Contents
S.
No.
1
2
3
4

Contents

Page No.

Evaluation Scheme
Dos and Donts
Laboratory Instructions
List of Experiments

I
II
III
IV-V

Evaluation Scheme:
Class: Vth Semester B.Tech.

Evaluation

Branch: E.C.E

Examination Time = Two (2) Hours

Schedule per Week

Practical Hrs : 2 hr/week
Credit: 1

Maximum Marks = 100

[Internal (60) & External (40)]

DOS AND DONTS

DOS

Students should get the record of previous experiment checked before starting the new
experiment.

Read the manual carefully before starting the experiment.

Before starting the experiment, get circuit diagram checked by the teacher.

Get your readings or simulation result checked by the teacher.

Apparatus must be handled carefully.

Maintain strict discipline.

Keep your mobile phone switched off or in vibration mode.

Students should get the experiment allotted for next turn, before leaving the lab.

DONTS

Do not touch or attempt to touch the mains power supply wire with bare hands.

Do not overcrowd the tables.

Do not tamper with equipment.

Do not leave the lab without prior permission from the teacher.
2

Instructions to the students

General Instructions
Maintain separate observation copy for each laboratory.
Observations or readings should be taken only in the observation copy.
Get the readings counter signed by the faculty after the completion of the experiment.
Maintain Index column in the observation copy and get the signature of the faculty
before leaving the lab.
Before entering the Lab

The previous experiment should have been written in the practical file, without which
the students will not be allowed to enter the lab.
The students should have written the experiment in the observation copy that they are
supposed to perform in the lab.
The experiment written in the observation copy should have aim, apparatus required,
circuit diagram/algorithm, blank observation table (if any), formula (if any),
programmed (if any), model graph (if any) and space for result.

When working in the Lab

Necessary equipment/apparatus should be taken only from the lab assistant by making
an issuing slip, which would contain name of the experiment, names of batch members
and apparatus or components required.
Never switch on the power supply before getting the permission from the faculty.

Before leaving the Lab

The equipment/components should be returned back to the lab assistant in good

condition after the completion of the experiment.
The students should get the signature from the faculty in the observation copy.
They should also check whether their file is checked and counter signed in the index.

LIST OF EXPERIMENTS (EC1531)

Module 1:
1

Write a VHDL program for realization of AND, NAND, OR, NOR and XOR logic
gates using their respective logical operators and verify their truth-table by simulation.

Write VHDL programs for 8:1 MUX and 1:8 DEMUX (use case statement) and
verify its truth-table by simulation.
Write VHDL program for 4- bit Gray to Binary and Binary to Gray converter using
with select and verify their truth-table by simulation.
Write VHDL programs for Full Adder :

3
4

(a) Using behavioral modeling.

(b Using dataflow modeling.
)
(c) Using structural modeling with basic gates.
(d
)
5
6
7

Using structural modeling with half adders.

Write VHDL programs for implementing 9-input Parity Checker and generator and
verify their truth-table by simulation.
Write VHDL programs for realization of flip-flops (D, T, JK, SR-Flip flop) using
behavior modeling style and verify their truth-table by simulation
Write VHDL programs for BCD Up and Down Counter and verify using simulation.

Module 2:
8
Design the schematic and simulate resistive load inverter, enhancement load inverter,
depletion load inverter and CMOS inverter to derive the Voltage Transfer
Characteristics (VTC).
9
Simulate NMOS and PMOS transistor to derive input and output characteristics and
observe the effects of width and length on these characteristics.
1
Simulate resistive load and CMOS inverter to perform transient response and obtain the
0
rise time, fall time and propagation delays on inverters and also analyze the effect of
fan in and fan out on the delay on inverters.
1
Simulate CMOS inverter to perform DC and transient response. Also analyze the
1
effects of different width, length, supply voltage and capacitance on the responses.
1
Design layout of resistive load & CMOS inverters and perform DRC, LVS on the
2
designed layout.
1
Design the schematic of 2-input NAND gate and simulate it to observe the DC and
3
transient response.
1
Implement Boolean function (half adder) using Transmission gates (TG), Pass
4
Transistor Logic (PTL) and verify the truth table by simulating the circuits.
4

1
5

Simulate D-flip flop and observe the effects of set up and hold time on output response.

Experiment 1: Realization of Basic Gates

Aim: Write a VHDL program for realization of AND, NAND, OR, NOR and XOR logic gates
using their respective logical operators and verify their truth-table by simulation.
Objectives:
(i) To familiarize with the electronic development automation development automation software for
digital designing and learn the basic flow to write a program in VHDL using EDA tool such as Xilinx.
(ii) To verify the operation of logic gates using ISIM simulator.
(iii) To learn about timing diagram and verification of operation of logic circuit using timing diagram.
(iv) To learn about basic datatypes, ports and organization of VHDL program.
Requirements:
Software

- Active HDL/Cadence Encounter/Xilinx

Theory:
Logic gates are the most basic components of a computer. Logic gates take the binary inputs, does a
command based on what kind of gate it is and then it releases a binary output.
AND/NAND Gate
The function of an AND gate is to multiply all the values of the input, then output the product. The
Boolean equation of the logic gate is:
X = A.B
A NAND gate, also known as a Negated AND gate, does the function of the AND gate and then
negates it. The Boolean equation of the logic gate is:
X = (A.B)
OR/NOR Gate
The function of an OR gate is to add all the values of the input and then output the sum. The Boolean
equation of the logic gate is:
X = A+B
A NOR gate, also known as a Negated OR gate, does the function of the OR gate, then negates it. The
Boolean equation of the logic gate is:
X = (A+B)
X-OR Gate
The "X" in XOR stands for exclusive. This means that the XOR gate performs the function of the OR
gate but only if there is a single 1 and 0. If either input is true (1) then the other input is false (0) then
the output is true; if the inputs are both the same then the output is false(0). The Boolean equation of
the logic gate is:
X = A + B = AB+AB

** NAND and NOR gates are referred to as universal gates.

Procedure:
1) Define the design requirements.
2) Describe the design in VHDL.
3) Simulate the design.
4) Synthesize, optimize and fit the design.
5) Note down the RTL schematic and waveform.
6) Download the design onto a CPLD/FPGA chip. Verify the truth table.
Program:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Allgates is
port(
a : in STD_LOGIC;
b : in STD_LOGIC;
c_and : out STD_LOGIC;
d_or : out STD_LOGIC;
e_not : out STD_LOGIC;
f_nor : out STD_LOGIC;
g_nand : out STD_LOGIC;
h_xor : out STD_LOGIC;
i_xnor : out STD_LOGIC
);
end Allgates;
--}} End of automatically maintained section
Architecture rtl of Allgates is
begin
c_and<= a and b;
d_or<= a or b;
e_not<= not a;
f_nor<= a nor b;
g_nand<= a nand b;
h_xor<= a xor b;
i_xnor<= a xnor b;
end rtl;

Experiment No 2
Aim: Write VHDL programs for 8:1 MUX and 1:8 DEMUX (use case statement) and verify
its truth-table by simulation.
Objectives:
i) To learn about behavioral style of modelling.
ii) To learn the use of case statement.
iii) To learn about the use of standard logic vector.
Requirements:
Software

- Active HDL/Cadence Encounter/Xilinx

Theory:
A multiplexer

(or mux) is a device that selects one of several signals and forwards the selected input
into a single line. A multiplexer of 2n inputs has n select lines, to select which input line to send to the
output. Mux is mainly used to share a device or resource. Its use increases the amount of data that can
be sent over the network within a certain amount of time and bandwidth. A multiplexer is also called
a data selector.
Conversely, a demultiplexer (or demux) is a device taking a single input signal and selecting one of
many data-output-lines, which is connected to the single input. A multiplexer is often used with a
complementary demultiplexer on the receiving end.

MUX
Input data: A,B
Input data:
Select line: S
Select line: S
Output: Z

DEMUX
A
Output: Z1,Z0

Z 0 A.S , A.S

Z ( A.S ) ( B.S )
Boolean expression

Boolean expressions

The comparator to be designed should take up two inputs of 4 bits each and have 3 output bits to
indicate if (a>b) or (a<b) or (a=b).

Program:
Multiplexer:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity \8_1mux\ is
port(

x : in STD_LOGIC_VECTOR(0 to 7);
s : in STD_LOGIC_VECTOR(0 to 2);
y : out STD_LOGIC
);
end \8_1mux\;
--}} End of automatically maintained section
Architecture rtl of \8_1mux\ is
begin
process(x,s)
begin
case s is
when "000" => y <= x(0);
when "001" => y <= x(1);
when "010" => y <= x(2);
when "011" => y <= x(3);
when "100" => y <= x(4);
when "101" => y <= x(5);
when "110" => y <= x(6);
when "111" => y <= x(7);
when others => null;
end case;
end process;
end rtl;
Demultiplexer:
entity demux2 is
Port ( din : in std_logic;
s : in std_logic_vector(2 downto 0);
dout : out std_logic_vector(7 downto 0));
end demux2;
architecture Behavioral of demux2 is
begin
process(s)
begin
if din = '1' then
case s is
when "000" =>dout<= "00000001";
when "001" =>dout<= "00000010";
when "010" =>dout<= "00000100";
when "011" =>dout<= "00001000";
when "100" =>dout<= "00010000";
when "101" =>dout<= "00100000";
when "110" =>dout<= "01000000";
when "111" =>dout<= "10000000";
when others => null;

end case; end if; end process;

end Behavioral;

Experiment No 3: Combinational Circuits

Aim: (i) Write VHDL program for 4- bit Gray to Binary and Binary to Gray converter using
with select and verify their truth-table by simulation.
Objectives:
(i)
(ii)

To learn about the design of code converter.

To learn about the use of with select statement.

Requirements:
Software

- Active HDL/Cadence Encounter/Xilinx

Theory:
Gray Code is a non-weighted code which belongs to a class of codes called minimum change codes.
In this code two adjacent code numbers differs from each other by only one bit. The change of bit
always occurs from the right side i.e. from L.S.B towards the M.S.B. This code is not applicable in
any types of arithmetical operations but it has some applications in analog to digital converters and in
some input/output devices.
Binary to gray code conversion is a very simple process. There are several steps to do this types of
conversions. Steps given below elaborate on the idea on this type of conversion
1

The M.S.B. of the gray code will be exactly equal to the first bit of the given binary number.

Now the second bit of the code will be exclusive-or of the first and second bit of the given
binary number, i.e if both the bits are same the result will be 0 and if they are different the
result will be 1.

The third bit of gray code will be equal to the exclusive-or of the second and third bit of the
given binary number. Thus the Binary to gray code conversion goes on. One example given
below can make your idea clear on this type of conversion.

Gray code to binary conversion is again very simple and easy process. Following steps can make your
idea clear on this type of conversions.
1

The M.S.B of the binary number will be equal to the M.S.B of the given gray code.

Now if the second gray bit is 0 the second binary bit will be same as the previous or the first
bit. If the gray bit is 1 the second binary bit will alter. If it was 1 it will be 0 and if it was 0 it
will be 1.

This step is continued for all the bits to do Gray code to binary conversion.

Program:

(i)

Binary to Gray:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity b_g is
port(
i : in STD_LOGIC_VECTOR(0 to 3);
o : out STD_LOGIC_VECTOR(0 to 3)
);
endb_g;
--}} End of automatically maintained section
Architecture rtl of b_g is
begin
with i select
o <= "0000" when "0000",

"0001" when "0001",

"0011" when "0010" ,
"0010" when "0011",
"0100" when "0100",
"0101" when "0101" ,
"0111" when "0110" ,
"0110" when "0111" ,
"1000" when "1000" ,
"1001" when "1001",
"1011" when "1010",
"1010" when "1011",
"1100" when "1100",
"1101" when "1101",
"1111" when "1110",
"1110" when others;
End rtl;
end Behavioral;

(ii)
(iii)

Gray to Binary

(iv)
(v)
(vi)
(vii)
(viii)
(ix)
(x)
(xi)
(xii)
(xiii)
(xiv)

entity g2b is
Port ( g : in std_logic_vector(3 downto 0);
b : out std_logic_vector(3 downto 0));
end g2b;
architecture Behavioral of g2b is
begin
b(3)<= g(3);
b(2)<= g(3) xor g(2);
b(1)<= g(3) xor g(2) xor g(1);
b(0) <= g(3) xor g(2) xor g(1) xor g(0);
end Behavioral;

(xv) Experiment No 4: Full Adders

(xvi)

Aim: Write VHDL programs for Full Adder and verify using simulation.

i) Using behavioral modeling.

ii) Using dataflow modeling.
iii) Using structural modeling with basic gates.
iv) Using structural modeling with half adders.
(xvii) Objectives:
(i)
(ii)

To learn the various style of modelling.

To learn about the arithmetic circuit used in digital system.

(xviii)

(xix)

Requirements:

(xx)

Software

- Active HDL/Cadence Encounter/Xilinx

(xxi)

(xxii) Theory:
(xxiii) The half adder adds two single binary digits A and B. It has two outputs, sum (S) and
carry (C). The carry signal represents an overflow into the next digit of a multi-digit
addition. The circuit and truth table for half adder is shown below.

(xxiv)
(xxv) A full adder adds binary numbers and accounts for values carried in as well as out. A onebit full adder adds three one-bit numbers, often written as A, B, and Cin; A andB are the
operands, and Cin is a bit carried in from the next less significant stage. Full adder can be
implemented in 2 ways:i
by direct modelling (using basic logic gates).
ii
by using 2 half adders.
(xxvi)
(xxvii) Implementation with both these methods is shown below with the truth table.

(xxviii)

(xxix)
(xxx)
(xxxi)

(xxxii)
(xxxiii)

Programs:

(lxxi) endfa_exp;

(xxxiv)Full Adder Behavioral:

(lxxii)

(xxxv) Entity fa is
(xxxvi) Port (inputs: instd_logic_vector(2
downto 0);
(xxxvii) s,c : out std_logic);
(xxxviii) end fa;
(xxxix)architecture Behavioral of fa is
(xli) begin
(xlii)
process(inputs)
(xliii)
begin
(xliv)
case inputs is
(xlv)
when "000" => s<='0';c<='0';
(xlvi)
when "001" => s<='1';c<='0';
(xlvii)
(xlviii)
(xlix)
(l)
(li)
(lii)
when "010" => s<='1';c<='0';
(liii) when "011" => s<='0';c<='1';
(liv)
when "100" => s<='1';c<='0';
(lv)
when "101" => s<='0';c<='1';
(lvi)
when "110" => s<='0';c<='1';
(lvii)
when "111" => s<='1';c<='1';
(lviii)
when others=> null;
(lix)
end case;
(lx)
end process;
(lxi) end Behavioral;

(lxxiii) Full Adder Structural:

(xl)

(lxii)
(lxiii)
(lxiv)
(lxv)
(lxvi) Full Adder Using Data Flow
Model:
(lxvii)

(lxviii) Entity fa_exp is

(lxix)
Port ( a,b,cin : in std_logic;
(lxx) sout, cout : out std_logic);

(lxxiv)

(lxxv) library IEEE;

(lxxvi) use IEEE.STD_LOGIC_1164.all;
(lxxvii)
(lxxviii) entity full_generate is
(lxxix)
port(
(lxxx)
cin : in STD_LOGIC;
(lxxxi)
a : in
STD_LOGIC_VECTOR(0 to 3);
(lxxxii)
b : in
STD_LOGIC_VECTOR(0 to 3);
(lxxxiii)
cout : out
STD_LOGIC;
(lxxxiv)
s : out
STD_LOGIC_VECTOR(0 to 3)
(lxxxv)
);
(lxxxvi) End full_generate;
(lxxxvii)
(lxxxviii) --}} End of automatically
maintained section
(lxxxix)
(xc)
(xci)
(xcii)
(xciii)
(xciv)
(xcv)
(xcvi)
(xcvii)
(xcviii)
(xcix)
(c)
(ci)
(cii)
(ciii)
(civ)
(cv)

architecture Behavioral of fa_exp is

(cvi) begin
(cvii)
sout<=a xor b xor cin;
(cviii) cout<=(a and b) or (b and cin) or
(cin and a);
(cix) end Behavioral;
(cx)
(cxi)
(cxii) architecture rtl of full_generate is
(cxiii) signal c:std_logic_vector(0 to 4);
(cxiv) begin
(cxv)
G2:for M in 3 downto 0
generate
(cxvi)
s(M)<=(a(m) xor b(m))
xor c(m);
(cxvii)
c(m+1)<=(a(m)
and
b(m)) and c(m);
(cxviii)
end generate;
(cxix)
c(0)<= cin;
(cxx)
cout<= c(4);
(cxxi)
(cxxii)
(cxxiii)end rtl;

(cxxiv)
(cxxv)
(cxxvi)
(cxxvii)
(cxxviii)
(cxxix)
(cxxx)
(cxxxi)
(cxxxii)
(cxxxiii)

(cxxxiv)

Full Adder Using Half Adders

(cxxxv) entity ha is
(cxxxvi)
Port ( a,b : in std_logic;
(cxxxvii) s,c : out std_logic);
(cxxxviii) end ha;
(cxxxix) architecture Behavioral of ha is
(cxl) begin
(cxli)
s<=a xor b;
(cxlii)
c<=a and b;
(cxliii) end Behavioral;
(cxliv) entity fulladder is
(cxlv)
Port ( x,y,cin : in std_logic;
(cxlvi) sout,cout : out std_logic);
(cxlvii)end fulladder;
(cxlviii) architecture Behavioral of
fulladder is
(cxlix)
component ha
(cl)
port(a,b:instd_logic;
(cli)
s,c:outstd_logic);
(clii)
end component;
(cliii)
signal
c1,c2,s1:std_logic;
(cliv)
begin
(clv)
u1:ha port
map(x,y,s1,c1);
(clvi)
u2:ha port
map(s1,cin,sout,c2);
(clvii)
(clviii)
(clix)
(clx) cout<=c1 or c2;
(clxi)
end Behavioral;

(clxii) Experiment No 5: Design of Parity Checker and Generator.

(clxiii) Aim: Write VHDL programs for implementing 9-input Parity Checker and Generator and
verify their truth-table by simulation.
(clxiv) Objectives:
i) To learn about the use of loop statement to design digital system.
ii) To learn about the design of parity checker & generator circuit.
(clxv) Requirements:
(clxvi) Software

- Active HDL/Cadence Encounter/Xilinx

(clxvii)Theory:
(clxviii)

Parity Checker:

(clxix) A parity bit, or check bit, is a bit added to the end of a string of binary code that indicates
whether the number of bits in the string with the value one is even or odd. Parity bits are used as
the simplest form of error detecting code.
(clxx) There are two variants of parity bits: even parity bit and odd parity bit. In case of even parity,
the parity bit is set to 1 if the count of ones in a given set of bits (not including the parity bit) is
odd, making the count of ones in the entire set of bits (including the parity bit) even. If the count
of ones in a given set of bits is already even, it is set to a 0. When using odd parity, the parity bit
is set to 1 if the count of ones in a given set of bits (not including the parity bit) is even, making
the count of ones in the entire set of bits (including the parity bit) odd. When the count of set
bits is odd, then the odd parity bit is set to 0.
(clxxi) Parity Generator:
(clxxii)Parity bits are extra signals which are added to a data word to enable error checking. There are
two types of Parity - even and odd. An even parity generator will produce a logic 1 at its output
if the data word contains an odd number of ones. If the data word contains an even number of
ones then the output of the parity generator will be low. By concatenating the Parity bit to the
data word, a word will be formed which always has an even number of ones i.e. has even parity.
(clxxiii)

Program: (Parity Checker)

(clxxiv)
(clxxv)
(clxxvi)
(clxxvii)
(clxxviii)
(clxxix)
(clxxx)
(clxxxi)
(clxxxii)
(clxxxiii)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity paritychecx is
Port ( insid1 : in STD_LOGIC_VECTOR (8 downto 0);
outsid2: inoutstd_logic);
end paritychecx;
11

(clxxxiv) architecture Behavioral of paritychecx is

(clxxxv)
(clxxxvi) begin
(clxxxvii) process(insid1)
(clxxxviii) variable a :std_logic:='1';
(clxxxix) begin
(cxc)
fori in 8 downto 0 loop
(cxci)
if insid1(i)='1' then
(cxcii)
a:= not a;
(cxciii)
else
(cxciv)
a:=a;
(cxcv)
end if;
(cxcvi)
end loop;
(cxcvii) outsid2<=a;
(cxcviii) end process;
(cxcix)
end Behavioral;
(cc)
(cci)
(ccii)
(cciii)
(cciv) Program:(Parity Generator)
(ccv) entity parity_9bit is
(ccvi)
Port ( d0 : in STD_LOGIC;
d1 : in STD_LOGIC;
(ccvii) d2 : in STD_LOGIC;
d3 : in STD_LOGIC;
(ccviii) d4 : in STD_LOGIC;
d5 : in STD_LOGIC;
(ccix) d6 : in STD_LOGIC;
d7 : in STD_LOGIC;
(ccx) d8 : in STD_LOGIC;
(ccxi) even :inout STD_LOGIC;
(ccxii) odd : out STD_LOGIC);
(ccxiii) end parity_9bit;
(ccxiv) architecture structure of parity_9bit is
(ccxv) component xor2
(ccxvi)
port(a,b:instd_logic;z:outstd_logic);
(ccxvii)
end component;
(ccxviii)
component inv2
(ccxix)
port(p:instd_logic;q:outstd_logic);
(ccxx)
end component;
(ccxxi)
signal e0,e1,e2,e3,f0,f1,h0:std_logic;
(ccxxii) begin
(ccxxiii) x0:xor2 port map(d0,d1,e0);
(ccxxiv)
x1:xor2 port map(d2,d3,e1);
(ccxxv) x2:xor2 port map(d4,d5,e2);
(ccxxvi) x3:xor2 port map(d6,d7,e3);
(ccxxvii) x4:xor2 port map(e0,e1,f0);
(ccxxviii) x5:xor2 port map(e2,e3,f1);
12

(ccxxix) x6:xor2 port map(f0,f1,h0);

(ccxxx) xeven:xor2 port map(h0,d8,even);
(ccxxxi) xodd:inv2 port map(even,odd);
(ccxxxii)
end structure;
(ccxxxiii)
(ccxxxiv)
(ccxxxv)
(ccxxxvi)
(ccxxxvii)
(ccxxxviii)
(ccxxxix)
(ccxl)
(ccxli)
(ccxlii)
(ccxliii)
(ccxliv)
(ccxlv)
(ccxlvi)
(ccxlvii)
(ccxlviii)
(ccxlix)
(ccl)
(ccli)

(cclii) Experiment No 6: Modelling Flip Flops

(ccliii) Aim: Write VHDL programs for realization of flip-flops using behavior modeling style
and verify their truth-table by simulation.
(ccliv) a) D flips flop
(cclv) b) T flips flop
(cclvi) c) JK flips flop
(cclvii) d) SR flips flop
(cclviii)

(cclix) Objectives:
(i)
(ii)
(iii)

To familiarize students about sequential design.

To learn about the clock sensitive digital circuit and their timing diagram.
To learn about triggering of digital circuits.

13

(cclx) Requirements:
(cclxi) Software

- Active HDL/Cadence Encounter/Xilinx

(cclxii) Theory:
(cclxiii) D Flip Flop: D is the information input and clk is the clock input\ control. When the flip
flop is enabled the output of flip flop follows the value applied to D input.
(cclxiv) T Flip Flop: T is the information output and clk is the clock or control signal. When the flip
flop is enabled and T is 0, the output of flip flop remains in the previous state.When the flip flop
is enabled and T is 1, the output of flip flop is opposite of previous state i.e the output toggles.
When disabled, the output remains in previous state.
(cclxv) Sr Flip Flop: The information input lines S,R are used to set or reset the flip flop. Clk is the
clock or control signal . The rising or falling edge clk causes a change in the output depending
on S and R. The asynchronous inputs SN(set/preset) and RN(reset/clear) are used to forcibly set
and reset the flip flop independent of control input.
(cclxvi) Jk Flip Flop:To avoid the invalid condition when SR=11 in a SR flip flop, the JK flip flop
is used .When JK=11 the output of JK flip toggles. All other conditions are similar to SR flip
flop.
(cclxvii) The truth tables for the above flip-flops are given below:
(cclxviii) D
Flip
flop

(cclxix) T
Flip
flop

(cclxx) S-R Flip flop

(cclxxi)

J-K Flip flop

(cclxxii) (cclxxiii) (cclxxiv) (cclxxv) (cclxxvi) (cclxxvii) (cclxxviii)(cclxxix) (cclxxx) (cclxxxi)

D
Q
T
Q
S
R
Q
J
K
Q
(cclxxxii) (cclxxxiii) (cclxxxiv) (cclxxxv) (cclxxxvi) (cclxxxvii)(cclxxxviii)
(cclxxxix)(ccxc)
0
0
0
Q
0
0
Q
0
0

(ccxci)
Q

(ccxcii)
1

(ccxciii) (ccxciv) (ccxcv)

1
1
Q

(ccxcvi) (ccxcvii) (ccxcviii) (ccxcix) (ccc)

0
1
0
0
1

(ccci)
0

(cccii)

(ccciii)

(cccvi)
1

(cccxi)
1

(cccxii)

(cccxiii) (cccxiv) (cccxv)

(ccciv)

(cccv)

(cccvii)
0

(cccviii) (cccix)
1
1

(cccxvi) (cccxvii) (cccxviii) (cccxix) (cccxx)

1
1
XX
1
1

(cccxxii)
(cccxxvi) Procedure:
1)
2)
3)
4)
5)
6)

(cccx)
0

Define the design requirements.

Describe the design in VHDL.
Synthesize, optimize and fit the design.
Simulate the design.
Note down the RTL schematic and waveform.
Download the design onto a CPLD chip. Verify the truth table.

(cccxxvii)
14

(cccxxi)
Q

(cccxxviii)
(cccxxix) Programs:
(cccxxx)

D Flip Flop:

STD_LOGIC;
(ccclxviii)
q : out
STD_LOGIC
(ccclxix)
);
(ccclxx) End t_ff;
(ccclxxi)
(ccclxxii) --}} End of automatically
maintained section
(ccclxxiii)
(ccclxxiv) architecturertl of t_ff is
(ccclxxv) begin
(ccclxxvi)
(ccclxxvii)
process(clk)
(ccclxxviii)
begin
(ccclxxix) if(clk'event and clk='0')then
(ccclxxx) q<=not t;
(ccclxxxi) else
(ccclxxxii) q<='0';
(ccclxxxiii)
end if;
(ccclxxxiv)
end process;
(ccclxxxv)
(ccclxxxvi)
end rtl;
(ccclxxxvii)
(ccclxxxviii)
JK FLIP FLOP:
(ccclxxxix)
library IEEE;
(cccxc)use IEEE.STD_LOGIC_1164.all;
(cccxci)
(cccxcii) entity jk_ff is
(cccxciii)
port(
(cccxciv)
j : in STD_LOGIC;
(cccxcv)
k : in STD_LOGIC;
(cccxcvi)
clk : in
STD_LOGIC;
(cccxcvii)
q :inout
STD_LOGIC
(cccxcviii)
);
(cccxcix) End jk_ff;
(cd)
(cdi) --}} End of automatically maintained
section
(cdii)
(cdiii) Architecture rtl of jk_ff is
(cdiv) begin

(cccxxxi) library IEEE;

(cccxxxii) use IEEE.STD_LOGIC_1164.all;
(cccxxxiii)
(cccxxxiv) entity d_ff is
(cccxxxv)
port(
(cccxxxvi)
d : in STD_LOGIC;
(cccxxxvii)
clk : in
STD_LOGIC;
(cccxxxviii)
q : out
STD_LOGIC
(cccxxxix)
);
(cccxl) endd_ff;
(cccxli)
(cccxlii) --}} End of automatically
maintained section
(cccxliii)
(cccxliv)
(cccxlv)
(cccxlvi) Architecture rtl of d_ff is
(cccxlvii) begin
(cccxlviii)
(cccxlix)
process(clk)
(cccl)
begin
(cccli)
if (clk'event and clk='1')
then
(ccclii)
q<=d;
(cccliii) else q<='0';
(cccliv) end if;
(ccclv) end process;
(ccclvi)
(ccclvii) end rtl;
(ccclviii)
(ccclix)
(ccclx) T- Flip Flop:
(ccclxi) library IEEE;
(ccclxii) use IEEE.STD_LOGIC_1164.all;
(ccclxiii)
(ccclxiv) entity t_ff is
(ccclxv)
port(
(ccclxvi)
t : in STD_LOGIC;
(ccclxvii)
clk : in
15

(cdv)
(cdvi)
process (j, k, clk)
(cdvii) begin
(cdviii)
ifclk = '1' then
(cdix)
if j ='0' and k = '0' then
(cdx)
q <= q;
(cdxi)
elsif j ='0' and k = '1' then
(cdxii)
q <= '0';
(cdxiii)
elsif j ='1' and k = '0' then
(cdxiv)
q <='1';
(cdxv)
elsif j ='1' and k = '1' then
(cdxvi)
q <= not q;
(cdxvii)
end if;
(cdxviii)
end if;
(cdxix)
end process;
(cdxx)
(cdxxi) end rtl;

(cdxxxiii)
);
(cdxxxiv) endsr_ff;
(cdxxxv)
(cdxxxvi) --}} End of automatically
maintained section
(cdxxxvii)
(cdxxxviii)Architecture rtl of sr_ff is
(cdxxxix) begin
(cdxl)
(cdxli)
process(s,r,clk)
(cdxlii)begin
(cdxliii)
ifclk = '1' then
(cdxliv)
if s ='0' and r = '0'
then
(cdxlv)
q <= q;
(cdxlvi)
elsif s ='0' and r =
'1' then
(cdxlvii)
q <= '0';
(cdxlviii)
elsif s ='1' and r =
'0' then
(cdxlix)
q <='1';
(cdl)
elsif s ='1' and r = '1' then
(cdli)
q <= 'X';
(cdlii)
end if;
(cdliii)
end if;
(cdliv)
end process;
(cdlv)
(cdlvi) end rtl;
(cdlvii)
(cdlviii)
(cdlix)

(cdxxii)
(cdxxiii) SR FLIP FLOP:
(cdxxiv) library IEEE;
(cdxxv) use IEEE.STD_LOGIC_1164.all;
(cdxxvi)
(cdxxvii) entity sr_ff is
(cdxxviii)
port(
(cdxxix)
s : in STD_LOGIC;
(cdxxx)
r : in STD_LOGIC;
(cdxxxi)
clk : in
STD_LOGIC;
(cdxxxii)
q :inout
STD_LOGIC

16

(cdlx) Experiment No. 7: Design of Counters

(cdlxi)

Aim: Write VHDL programs for BCD Up and Down Counter and verify
using simulation.

(cdlxii)

Objectives:

i) To learn about design & simulation of counter.

ii) To learn about the use of variable statement.
(cdlxiii)

Requirements:

(cdlxiv)

Software

- Active HDL/Cadence Encounter/Xilinx

(cdlxv)Theory:
(cdlxvi) The primary function of a counter is to produce a specified output sequence. A
counter is a collection of flip flops. The total number of states is called the modulus.
(cdlxvii) A BCD counter or decade counter can be constructed from a straight binary
counter by terminating the "ripple-through" counting when the count reaches decimal
9 (binary 1001). Since the next toggle would produce 1010, that drives both X 1 and
X3 high, and since they are the inputs to the NAND gate, the output of the NAND
goes low. This zero output to the asynchronous clear line will clear the registers and
start the count over after 9.

(cdlxviii)
(cdlxix) Counters whose counting sequence corresponds to that of the binary numbers are
called binary counters. The modulus of a binary counter is 2n where n is the number
of flip flops in the counter. For a binary up counter the counting sequence starts from
0000 and ends with 1111 or from 0 to 2 N-1, where N is the number of bits/flipflops in the counter. Each flip-flop is used to represent one bit. The flip-flop in the
lowest-order position is complemented/toggled with every clock pulse and a flip-flop
in any other position is complemented on the next clock pulse provided all the bits in
the lower-order positions are equal to 1.
(cdlxx) To implement a synchronous counter, we need a flip-flop for every bit and an AND
gate for every bit except the first and the last bit. The diagram below shows the
implementation of a 4-bit synchronous up-counter.

(cdlxxi)

(cdlxxii) In a binary up counter, a particular bit, except for the first bit, toggles if all the
lower-order bits are 1's. The opposite is true for binary down counters. That is, a
particular bit toggles if all the lower-order bits are 0's and the first bit toggles on every
pulse.
(cdlxxiii) Synchonization is used to avoid the settling problems. In synchronous counters,
the count pulses are applied directly to control inputs of all clocked flip flops.This
causes all flip flops to change simultaneously after a time delay.

(cdlxxiv)
(cdlxxv)

Programs:

(cdlxxvi) BCD Up Counter:

(cdlxxvii)
(cdlxxviii) Entity bcd is
(cdlxxix)
Port ( sreset,areset,clk : in std_logic;
(cdlxxx) q :inout std_logic_vector(3 downto 0));
(cdlxxxi) end bcd;
(cdlxxxii) architecture Behavioral of bcd is
(cdlxxxiii) begin
(cdlxxxiv)
process(areset,sreset,clk)
(cdlxxxv) variable count:std_logic_vector(3 downto 0);
(cdlxxxvi)
begin
(cdlxxxvii)
if(areset='1') then count:="0000";
(cdlxxxviii)
elsif(clk='1' and clk'event)then

(cdlxxxix)
(cdxc)
(cdxci)
(cdxcii)
(cdxciii)
(cdxciv)
(cdxcv)
(cdxcvi)
(cdxcvii)
(cdxcviii)

if(sreset='1')then
count:="0000";
else count:=count+1;
if (count="1010")then count:="0000";
end if;
end if;
end if;
q<=count;
end process;
end Behavioral;

(cdxcix)

Experiment No. 8

(d)

Aim: Design the Schematic and Simulate Resistive Load Inverter, Enhancement
Load Inverter, Depletion Load Inverter and CMOS Inverter to derive the
Voltage Transfer Characteristics (VTC).

(di)

Objectives:

(i)
(ii)

To familiarize student with cadence EDA tool.

To learn how to design schematic of inverters and simulate with encounter tool.

(dii)

Requirements:

(diii) Software

- Cadence Encounter

(div)

Theory :

(dv)

The basic CMOS inverter is shown in Figure 1. It utilizes two MOSFETs: one, QN,
with an n channel and the other, QP, with a p channel. The body of each device is
connected to its source, and thus no body effect arises. This CMOS circuit realizes the
conceptual inverter implementation, where a pair of switches are operated in a
complementary fashion by the input voltage vI.

(dvi)

Digital inverter quality is often measured using the voltage transfer curve (VTC) as
shown in Figure 2, which is a plot of output vs. input voltage. From such a graph,
device parameters including noise tolerance, gain, and operating logic levels can be
obtained. Ideally, the VTC appears as an inverted step function this would indicate
precise switching between on and off but in real devices, a gradual transition region
exists. The VTC indicates that for low input voltage, the circuit outputs high voltage;
for high input, the output tapers off towards the low level. The slope of this transition
region is a measure of quality steep (close to infinity) slopes yield precise
switching.

(dvii)

(dviii)
(dix)

Figure 1:- The CMOS inverter.

Figure 2:- The VTC of the CMOS

inverter

(dx)
(dxi)

Circuit Simulation (DC analysis) using Cadence :-

(dxii) 1 Schematic Capture

(dxiii) 1.1 Creating a New Schematic
(dxiv) 1. To view all the libraries in the current work directory click on Tools Library
Manager as outlined in Figure 1. and the Library Manager window will pop up as
shown in Figure 2.
(dxv) Note: If you want to manually add a library that you copied from an external source
into your Cadence work directory you would need to edit the cd.lib file found in your
work directory folder by opening it in a text-editor.

(dxvi)
(dxvii) Figure 1: Launch Instructions for Library Manager

(dxviii)
(dxix) Figure 2: Library Manager Window
(dxx) 2. To create a new library click on File New Library and name the library as
TestLib as highlighted in Figure 3. After creating the new library you need to specify
the Technology File to be used in your respective PDK. In our case we will `Attach an
existing technology library', specically the `NCSU TechLib tsmc02d' which
corresponds to 180nm CMOS process. Figure 4 shows the steps involved in attaching
the appropriate technology file to a new library.
(dxxi)

(dxxii) Figure 3: Steps to Create New Library

(dxxiii)
(dxxiv)Figure 4: Attaching Tech File
(dxxv) 1.2 Creating a New schematic
(dxxvi)1. To create a new schematic click on on the library you created above, i.e. click on
`TestLib' which will then be highlighter. Now within the Library Manager window

click on File Ne w Cell View and call the new schematic inv as highlighted in
Figure 5. In this tutorial we will use a CMOS Inverter as an example circuit to
explore the steps involved in basic circuit simulation using Cadence ADE (Analog
Design Environment).
(dxxvii) 2. Once you have created your new schematic cell view a `Virtuoso Schematic
Editor' window will open up as shown in Figure 6.
(dxxviii)

(dxxix)Figure 5: Steps to Create New Schematic

(dxxx)
(dxxxii)

(dxxxi)Figure 6: Schematic Window

3. In order to create a circuit in the schematic editor we need to add `instances' or

circuit components like transistors, supply nets and wires. In the case of an inverter
we need one NMOS and one PMOS transistor, thus to add an instance press I from
your keyboard. This will open up a `Component Browser' as shown in Figure 7.
Choose the `NCSU Analog Parts' library and check-off the `Flatten' icon by clicking
on the grey box next to it. This will list all the components housed within the `NCSU
Analog Parts' library and gives you the ability to search for a specific component
from the `Filter'. Search for `nmos4' and follow the steps outline in Figure 8.
(dxxxiii)

(dxxxiv)

Figure 7: Adding an Instance on Schematic

(dxxxv)
(dxxxvi) Figure 8: Inserting NMOS Transistor on Schematic
(dxxxvii) 4. Similarly, following the same steps as (2) add a PMOS transistor to your
schematic by choosing the `pmos4' transistor from the `NCSU Analog Parts' library.
Your schematic should now look like Figure 9.

(dxxxviii)
(dxl)

(dxxxix) Figure 9: PMOS Transistor

5. In order to add wires to your schematic press W from your keyboard and make
appropriate connections across all transistor elements. Figure 10 demonstrates the
steps involved in labeling wires with a circuit schematic. This will come in very
handy during simulation, especially when dealing with circuits with several
components.

(dxli)

(dxlii) Figure 10: Inserting Wire Names on Circuit

(dxliii) 6. It is often advisable to add `Pin' names to each of the IO terminals in a circuit.
Thus, to add pins to your schematic press P from your keyboard or click on the pin
symbol as shown in Figure 11 and make appropriate connections across all IO ports.
Figure 12 demonstrates the steps involved in labeling wires with a circuit schematic.
(dxliv) Note: The `VDDA' and `GNDA' pins should be chosen to be `InputOutput' when
selecting the `Direction' during pin creation.

(dxlv)
(dxlvii)

(dxlvi) Figure 11: Creating Pin Names

7. Finally your schematic should look like Figure 12. Now click on `Check and
Save' icon (as shown in Figure 13) in the toolbar so that you can move onto the next
step of creating a symbol for the inverter schematic.

(dxlviii)
(dxlix) Figure 12: Inverter Schematic

(dl)
(dli) Figure 13: Check and Save
(dlii) 1.3 Creating a Symbol
(dliii) 1. When dealing with large circuits its often advisable to generate symbols for each
sub-circuit in the design and perform all simulations by placing the corresponding
symbols in a test bench. Figure 14 summarizes the steps involved in generating a
symbol from the inverter schematic designed in the previous section.
(dliv)
(dlv) Figure 14: Generating Symbol from Schematic
(dlvi) 2. Once you create the symbol it will pop-up. By default Cadence will generate a
rectangular symbol; however you can edit the generated symbol as per your needs. In
our case we will edit the symbol shape to make it resemble the traditional inverter
symbol used in conventional system design (as shown in Figure 15).
(dlvii)
(dlviii) Figure 15: Designing Schematic Symbol
(dlix) 1.4 Creating a Testbench
(dlx) Create a new-schematic following the steps outlined earlier in Section 3.1 and name it
`Tb inv'. This will be the testbench schematic from which we will run all our

simulations. Insert `vdc', `gnd' and `vsource' from the Component Library by
navigating to the `Analog Parts' library. Figure 16 shows the initial conditions to be
set for the voltage sources and Figure 17 shows what your testbench schematic should
look like at the end of this step.
(dlxi)

(dlxii) Figure 16: Inserting Sources in Testbench

(dlxiii)

(dlxiv) Figure 17: Designing the Testbench

(dlxv) 2. Circuit Simulation Using Spectre

(dlxvi) 2.1 Launching ADE
(dlxvii)
1. We will simulate our circuits using Cadence Spectre Simulation engine. Spectre
is a variant of HSPICE developed by Cadence and provides greater accuracy, speed
and flexibility especially when dealing with mixed signal circuits thus we will use it
as our preferred simulation engine in this course as well.
(dlxviii) 2. Make sure you first `Check and Save' your testbench schematic and click on
Launch ADE to open up the ADE window as shown in Figure 18.
(dlxix) 3. Click on Setup Simulator to make sure the Simulator is set to Spectre as shown
in Figure 18.

(dlxx)
(dlxxii)

(dlxxi) Figure 18: Simulating Circuit with ADE

4. Now click on Setup Model Libraries to configure the Spectre model files.
Figure 19 shows the path you need to browse to in order to get the correct model files
for the PDK used in this course.

(dlxxiii)
(dlxxiv) Figure 19: Configuring Model Files
(dlxxv)A) DC operating point analysis
(dlxxvi) 1. First simulation you will be exposed to is simulation of the DC operating point
for the inverter you designed earlier.
(dlxxvii) 2. Click on AC, DC, Tran icon on the right pane of the ADE window and a
window like Figure 20 should pop open. Choose `dc' and under `DC Analysis' save
the the DC Operating point. Note: Make sure you keep the Enabled option checked
off before you click on `Ok'.
(dlxxviii) 3. The output window should look like Figure 21 after you simulate the testbench
by pressing the green `Play' button on the right sidebar of ADE.
(dlxxix) 4. Suppose we want to now view the DC Operating points for the PMOS
transistor in the inverter. In order to do so we need to descend into the schematic view
from the testbench schematic.

(dlxxx)
(dlxxxi) Figure 20: Configuring DC Operating Point

(dlxxxii)
(dlxxxiii) Figure 21: DC Operating Point Netlist Output
(dlxxxiv) First click on Results Print DC Operating Points as shown in Figure 22.
Now in order to descend into the actual schematic of the inverter and select the
PMOS transistor we start off from the testbench schematic and click Edit
Hierarchy Descend Point Click on inverter symbol select PMOS. The
complete steps are outlined in Figures 22, 23 and 24.

(dlxxxv)
(dlxxxvi) Figure 22: Viewing DC Operating Point from ADE

(dlxxxvii)
(dlxxxviii) Figure 23: Viewing DC Operating Point from ADE

(dlxxxix)
(dxc) Figure 24: Final DC Operating Point Results
(dxci) B) DC Analysis
1.

The steps to run a DC analysis is similar to the transient setup shown above

2.

One can either use the "vpulse" as shown above or switch it for "vdc" from the same library
as source.

3.

Choose the source and press "q"

4.

The window Edit Object Properties opens: Enter Vin in the field DC voltage and press OK.
"Vin" is a variable name, that you can choose freely.

5.

Back in "Analog Enviroment" choose "Variables Copy From Cellview",

6.

Choose Analyses Choose and the window "Choosing Analyses" opens. Pick "dc" under
"Analysis" and set "Sweep Variable" to "Design Variable" and choose "Vin".

7.

For "Sweep Range" set "Start", "Stop" and for instance "Number of Steps".

(dxcii)

Back in "Analog Environment" use the button marked with "x y z" and give "Vin" some
random value (e.g. 0).

Choose the signals to be plotted by "Outputs->To Be Plotted->Select On Schematic".

These are now plotted against "Vin". If you click on a wire, you get a voltage. If you click
on a terminal on a component, you get a current.

(dxciii) Assignment :- Similar analysis is to be done for Resistive load inverter, depletion
load inverter, enhancement load inverter.
(dxciv)
(dxcv)

(dxcvi) Experiment No. 9

(dxcvii) Aim : Simulate NMOS and PMOS Transistor to derive Input and Output
Characteristics and observe the effects of Width and Length on these
Characteristics.
(dxcviii)
(i)
(ii)

Objectives:

To learn about the characteristics of MOS transistors using cadence.

To observe the effects of physical parameter variations on the characteristics.

(dxcix)Software :- Cadence Encounter

(dc)

Theory :

(dci)

Figure shows a typical transfer curve. The current IDSS at VGS <=0 is very small,
being of the order of a few nano-amperes. When the V GS is made positive, the drain
current ID increases slowly at first, and then much more rapidly with an increase in
VGS. The manufacturer sometimes indicates the gate-source threshold voltage VGST at
which the drain current ID attains some defined small value, say 10 uA. A current I D,on,
corresponding approximately to the maximum value given on the drain characteristics
and the values of VGS required to give this current VGs QN are also usually given on the
manufacturers data sheet.

(dcii) Drain characteristics of an N-channel E-MOSFET are shown in figure. The lowest
curve is the VGST curve. When VGS is lesser than VGST, ID is approximately zero. When
VGS is greater than VGST, the device turns- on and the drain current I D is controlled by
the gate voltage. The characteristic curves have almost vertical and almost horizontal
parts. The almost vertical components of the curves correspond to the ohmic region,
and the horizontal components correspond to the constant current region. Thus EMOSFET can be operated in either of these regions i.e. it can be used as a variablevoltage resistor (WR) or as a constant current source.

(dciii)

(dciv) Figure :- Transfer (input) and Drain (Output) characteristics of an NMOS transistor
(dcv) Circuit Simulation (Parametric sweep) using Cadence :(dcvi) After you start Cadence Virtuoso, create a new project library an then a new cell view.
Assemble a schematic as in the following figure.

(dcvii)
(dcviii)As can be seen, the transistor gate source has its DC value defined as VGS. On the
other hand, the transistor drain source has its DC value defined as VDS. The
transistor dimensions can be resized to a desired value.
(dcix) After pressing the Check and save button, open the Analog Design Environment
(ADE). In the ADE window, press the Edit variables button and a window will popup. Then press the Copy from button in order to obtain the VGS and VDS schematic
design variables, and define any value to each of them (these values are not important
for the present simulation but are actually needed to define a netlist). The edit
variables window should resemble following figure.

(dcx)
(dcxi) After this, in the ADE window press the choose analyses button or go to the
Analyses menu and select the option choose. A window will appear. In that window,
select a DC Analysis and press the Save DC Operating Point option. Then in the
Sweep Variable set of options, select the Design Variable option, and in the
Variable Name text box write VDS. In the Sweep Range set of options, select the

Start-Stop option and fill the Start and Stop text boxes with the desired values for
the VDS variable sweep. The configuration should be similar to the following figure.

(dcxii)
(dcxiii)In the ADE window click in the Output menu, option To be plotted > Select on
schematic and press the transistor drain. Also in the Output menu, select the option
To be saved > Select on schematic. This way, the drain current of the transistor will
be saved and plotted whenever a simulation is performed. The ADE window should
be similar to the following picture.
(dcxiv)
(dcxv) To execute the simulation, select the option Parametric analysis in the Tools menu

option. In the window that will appear fill the gaps similarly to the values shown in
the next figure.
(dcxvi)

(dcxvii) Then in the Analysis menu press the Start option to begin the parametric
simulation. A graphic will be plotted with several simulation results of the parametric
analysis. It may resemble something like depicted in the following figure. Of course
the results may vary from technology to technology.
(dcxviii)
(dcxix) Drain current of NMOS and PMOS transistor is proportional to the width of
transistors, while inversely proportional to the length of transistors as indicated in the
following figures.
(dcxx) NMOS I-V Equations :-

(dcxxi)
(dcxxii) PMOS I-V Equations:-

(dcxxiii)
(dcxxiv) Circuit simulation (Parametric sweep) using Cadence:(dcxxv) For input characteristics, keep Vds constant and make Vgs, width as variable
parameter during parametric sweep.
(dcxxvi) For output characteristics, keep Vgs constant and make Vds, width as variable
parameter during parametric sweep.
(dcxxvii)
(dcxxviii) Assignment :- Draw the NMOS input characteristics by interchanging Vgs and Vds.
Similarly draw input and output characteristics of PMOS.
(dcxxix)
(dcxxx)
(dcxxxi)
(dcxxxii)
(dcxxxiii)
(dcxxxiv)
(dcxxxv)
(dcxxxvi)
(dcxxxvii)
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(dcxxxix)

(dcxl) Experiment No. 10

(dcxli) Aim

:- Simulate resistive load and CMOS inverter to perform transient

response and to obtain the rise time, fall time and propagation delays on
inverters and also analyze the effect of fan in and fan out on the delay on
inverters.

(dcxlii)
(i)

Objectives:

To learn how to perform transient analysis of inverter circuit.

(ii)

To learn about the calculation of rise and fall time from inverter characteristic
(dcxliii)

Software :- Cadence encounter

(dcxliv)

Theory :

(dcxlv) The switching characteristics of digital integrated circuits and, in particular, of

inverter circuits, essentially determine the overall operating speed of digital systems.
The transient performance requirements of a digital system are usually among the
most important design specifications that must be met by the circuit designer.
Therefore, the switching speed of the circuit must be estimated and optimized very
early in the design phase.
(dcxlvi) The input and output voltage waveforms of a typical inverter circuit are shown in
Fig.. The propagation delay times tPHL and tPLH determine the input-to-output
signal delay during the high-to-low and low-to-high transitions of the output,
respectively. By definition, tPHL is the time delay between the V 50%-transition of the
rising input voltage and the V50% -transition of the falling output voltage. Similarly,
tPLH is defined as the time delay between the V50% -transition of the falling input
voltage and the V50%-transition of the rising output voltage.
(dcxlvii) To simplify the analysis and the derivation of delay expressions, the input voltage
waveform is usually assumed to be an ideal step pulse with zero rise and fall times.
Under this assumption, tPHL becomes the time required for the output voltage to fall
from VOH to the V50% level, and tPLH becomes the time required for the output
voltage to rise from VOL to the V50% level.

(dcxlviii)
Figure :- Input and output voltage waveforms of a typical inverter, and the
definitions of propagation delay times.
The rise time trise is defined here as the time required for the output voltage to rise
from the V10% level to V90% level. Similarly, the fall time t fall is defined here as the
time required for the output voltage to drop from the V90% level to V10% level.

(dcxlix)
(dcl)

(dcli)
(dclii) Figure :- Output voltage rise and fall times.
(dcliii) Fan-in is the number of inputs a gate can handle. Physical logic gates with a large fanin tend to be slower than those with a small fan-in. This is because the complexity of
the input circuitry increases the input capacitance of the device.
(dcliv) Fanout for CMOS gates is the ratio of the load capacitance (the capacitance that it is
driving) to the input gate capacitance. As capacitance is proportional to gate size, the
fanout turns out to be the ratio of the size of the driven gate to the size of the driver
gate. Fanout of a CMOS gate depends upon the load capacitance and how fast the
driving gate can charge and discharge the load capacitance. Digital circuits are mainly
about speed and power tradeoff. CMOS gate load should be within the range where
driving gate can charge or discharge the load within reasonable time with reasonable
power dissipation.
(dclv)
(dclvi) Circuit simulation (Transient analysis) using Cadence :(dclvii)1. Transient analysis of any circuit is the key to study the time domain behavior. In
this section you will simulate the transient time domain response of the inverter Vout,
Vin and compute propagation delay using the in-built Calculator in ADE.
(dclviii) 2. First open the testbench schematic and change the Vsource into a `Pulse' type
signal and configure it with the characteristics shown in Figure 29. Make sure you
`Check and Save' the schematic and now in ADE click on the AC, DC, Tran icon on
the right pane. Choose the `tran' simulation type, pick the stop time to be 10ns and
choose `moderate' in the `Accuracy details'.
(dclix) 3. Click on the green `Play' button to run the simulation and click on Result Direct
Plot to view the transient simulation plots.
(dclx) 4. In order to calculate the propagation delay of the inverter designed, in the ADE
window click on Tools Calculator and follow the instructions shown in Figure 30.
(dclxi) 5. Finally, your propagation delay and the final transient simulation plot should look
like Figure 31.

(dclxii)
(dclxiii)

Figure 29: Transient Simulation Setup

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(dclxv) Figure 30: Propagation Delay Calculation

(dclxvi)
Figure 31: Propagation Delay and Transient Analysis Output

(dclxix)
(dclxx)

(dclxxi) Experiment No. 11

(dclxxii) Aim: Simulate CMOS Inverter to perform DC and transient response. Also
analyze the effects of different Width, Length, Supply Voltage and Capacitance
on the responses.
(dclxxiii) Objectives:
(i)

To learn about the effect of parameter variation on DC response using Encounter tool.

(dclxxiv) Software :- Cadence SOC Encounter

(dclxxv)

Theory :

(dclxxvi) Reducing the supply voltage indiscriminately has a positive impact on the energy
dissipation, but is absolutely detrimental to the performance on the gate. The dccharacteristic becomes increasingly sensitive to variations in the device parameters
such as the transistor threshold, once supply voltages and intrinsic voltages become
comparable. Scaling the supply voltage means reducing the signal swing as shown in
Figure . While this typically helps to reduce the internal noise in the system (such as
caused by crosstalk), it makes the design more sensitive to external noise sources that
do not scale.
(dclxxvii)

(dclxxviii) Figure :- VTC of CMOS inverter as a function of supply voltage

(dclxxix) Both the n and p-channel transistors have a beta. Varying their ratio will change
the characteristics of the output curve as shown in Figure.

(dclxxx)
(dclxxxi) Figure :- VTC of CMOS inverter as a function of width and length of transistors
(dclxxxii) Minimizing propagation delay amounts to:
(dclxxxiii) 1) Reducing CL - Which is composed of self-loading (diffusion) (intrinsic),
routing and fan-out (extrinsic) capacitance. Careful layout can reduce diffusion and
interconnect caps.
(dclxxxiv) 2) Increase W/L ratio of the transistors - Increases the self-loading and therefore
CL. Once intrinsic (self-loading) cap starts to dominate the extrinsic load cap (wires +
fanout), increasing the width doesn't help delay as shown in Figure .

(dclxxxv)
(dclxxxvi) Figure :- Effect of NMOS width on tPLH delay of CMOS inverter
(dclxxxvii)3) Increase VDD - The delay of a gate can be modulated by modifying the supply
voltage. This allows the designer to trade off energy dissipation for performance as
shown in Figure .

(dclxxxviii)
(dclxxxix) Figure :- Normalized propagation delay and average switching power dissipation
of a CMOS inverter, as a function of the power supply voltage VDD.
(dcxc) Circuit simulation (parametric analysis) using Cadence :(dcxci) 1) To analyze the effect of width, length and supply voltage on DC characteristics,
perform parametric sweep considering these parameters as variables with varying
gate to source voltage during DC analysis.
(dcxcii) 2) To analyze the effect of width, length and supply voltage on delay, perform
parametric sweep considering these parameters as variables with time during transient
analysis.
(dcxciii) Assignment :- Other inverters such as resistive load inverter, depletion load
inverter, enhancement load inverter in similar way.
(dcxciv)
(dcxcv)
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(dcciv)

(dccv) Experiment No. 12

(dccvi)

Aim :- Design Layout of Resistive Load and CMOS Inverters and

perform DRC, LVS on the Designed Layout

(dccvii)
(i)
(ii)
(iii)

Objectives:

To familiarize students with cadence layout design tool.

To learn about design rule checking and LVS of designed layout.
To Generate GDSII file for the designed layout.

(dccviii)

Software :- Cadence Encounter

(dccix) Theory :
(dccx) A layout-design of an integrated circuit refers essentially to the three-dimensional
character of the elements and interconnections of an integrated circuit.
An integrated circuit (IC) is an electronic circuit in which the elements of the circuit
are integrated into a medium, and which functions as a unit. Currently the medium
used to create this unit is a solid semiconductor such as silicon. The circuit is
integrated into the piece of silicon, commonly called a "chip" or a "silicon chip". The
terms "integrated circuit", "semiconductor" and "silicon chip" are used synonymously
as commercial ICs are usually fabricated from silicon semiconductors.
(dccxi) Layout design using Cadence :(dccxii) Now, we will go through custom layout using Layout L, by creating a layout for
the inverter cell. To do this, in the Library Manager window, click on File > New >
Cell View. Make sure the New File dialog box looks as below and click OK.

(dccxiii)

(dccxiv) If the license window pops up, click YES. The Virtuoso Layout Suite L Editing
window should open up along with the LSW window, as shown below:

(dccxv)
(dccxvi) The LSW window contains all the layers that would be used to draw the layout.
To create the inverter layout, let us first instantiate the PMOS transistor. To do this,
press hokey i or click on Create > Instance. In the create instance window, enter
library name as NCSU_TechLib_ami06, cell as pmos, View as layout, Width as 1.5u,
Length as 600n and press ENTER. Place the instance in the layout window. Similarly,
instantiate a nmos transistor from the same library and place below the pmos
transistor in the layout window. The layout should look similar to one shown below.
Instead, if it appears as a red rectangle with pmos and nmos written on it, after
instantiating, press ShiftF/ControlF to toggle views.
(dccxvii)
(dccxviii) The red rectangle (poly layer) in the middle of each transistor is the gate of the
transistor. The black filled rectangles on either side of the gate are vias and can be
used interchangeably as source/drain terminals of the transistor. Now, we connect the
gates of the pmos and nmos transistors using poly layer. Left click on the poly layer
in the LSW window. Then switch back to the layout window and press rectangle
hotkey r. The rectangle window appears. Switch back to the layout window, and left
click at the left bottom corner of the rectangle you want to draw. Then left click at the
top right corner of the rectangle you want to draw. Most hotkeys used in the
schematic editor work in the layout editor too. After drawing a rectangle you might
want to take a few minutes to familiarize yourself with manipulating the rectangle
shape and size. Try using different hotkeys such as m for move, s for stretch and z/Z

for zoom, f for Fit in Window, k to draw a scale. To cancel the current command,
press ESC. At the end of this, the gates should be connected, as shown below:
(dccxix)

(dccxx) Similarly, create a metal 1 wire (using rectangle) to connect the drains of the two
transistors (connect the two vias, as shown below). Use more rectangles to draw out
the wires. Next, create the in pin. This pin is going to be created on the poly layer. So
click on poly in the LSW window. Then in the layout window, click on Create > Pin.
Create the in pin by filling out the fields as shown below and press ENTER:

(dccxxi)
(dccxxii)
(dccxxiii) Place the pin on the poly wire connecting the two gates. To do this, click
anywhere on the poly wire once. This will be the bottom left corner of the pin
rectangle. Then click once again at the top right corner of the pin rectangle. Next,
click next to pin where you want the pin name to appear. It is a good idea to make
sure that the pin is placed at a location where there is only one layer underneath the
pin, in this case the poly layer. This helps avoid confusion regarding which layer the
pin is attached to. Similarly create the out pin as an output pin, the vdd! and gnd! pins
as input output pins, and place them on metal1, as shown below:
(dccxxiv)
(dccxxv) You may have noticed that the bulk terminal is missing in the above layout for the
pmos and nmos transistors. At the layout level, one bulk connection is made for
several adjacently placed transistors. In this case, we only have one pmos and nmos
transistor. So we will still create the bulk connections for these transistors. To do this,
instantiate ntap from NCSU_TechLib_AMI06 and place next to the pmos transistor.
Instantiate a ptap from the same library and place next to the nmos transistor. Connect
the terminals from the taps to the supply nets vdd and gnd, as shown below:
(dccxxvi)
(dccxxvii)
(dccxxviii) Now the layout is complete. The next step is to verify the layout satisfies the
technology rules and then extract and simulate it. To verify the Design Rules Check
(DRC) is passed, in the layout window, click on Verify > DRC. In the DRC window,
select Join Nets with the Same Name and click OK. Then check the CIW window for
errors.
(dccxxix) If there are errors, they flash in white rectangles in the layout window. The find
out what the error is, in the layout window, click on Verify > Markers > Explain. Then
left click on any one of the flashing white rectangles. A window pops up explaining

what the error at that location is. An example pop up window with a metal width error
is shown below:
(dccxxx)

(dccxxxi)
(dccxxxii) So use the ruler (hotkey k) to draw scale for your references near this metal strip
and measure the width. Then resize your rectangle to satisfy the width requirement.
Use this procedure to fix all errors. Then run DRC check again to ensure that error
does not occur anymore. Once a particular markers error is fixed, you can delete that
marker by clicking on Verify > Markers > Delete and clicking on that marker. Repeat
this process until there are no DRC errors. Then save the layout.
(dccxxxiii) After this, the next step is to extract the electrical circuit netlist from this layout
diagram. To do that, from the layout window, click on Verify > Extract. In the
Extractor window, select Join Nets with Same Name, and click on Set Switches
button. In the Set Switches window, click on the first option Extract_parasitic_caps
and press OK. Press OK in the extractor window. Look at the CIW window and make
sure there are no errors.
(dccxxxiv) If there are no errors, then the extracted view has been created. Goto the Library
Manager window and open the extracted cell view for the inverter. It should look
similar to the window shown below. If it doesnt try toggling the view with
ShiftF/ControlF.
(dccxxxv)
(dccxxxvi)
(dccxxxvii)

Now the extracted layout is ready to be simulated.

(dccxxxviii)

Layout Instantiations

(dccxxxix) Similar to creating symbols at the schematic level, your layouts can also be
instantiated and repeatedly used several times while designing a hierarchical design.
Let us go back to the inverter example. Create a new layout cell view for the inverter
cell. Create an instance by clicking Create > Instance in the layout window. Then
browse to the Lab1 library, inverter cell and select the layout. This can now be
instantiated in your layout multiple times and used similar to the schematic symbols.
The layout can be DRV verified, extracted and simulated using the steps described

earlier.
(dccxl) Assignment :- Similarly layout of resistive load inverter can be designed and verified.
(dccxli)
(dccxlii)
(dccxliii)

(dccxliv)

Experiment No. 13

(dccxlv)

Aim :- Design The Schematic Of 2-Input NAND Gate And Simulate It

To Observe The DC And Transient Response.

(dccxlvi) Software :- Cadence Encounter

(dccxlvii) Theory :
(dccxlviii) In digital electronics, a NAND gate (negative-AND) is a logic gate which
produces an output which is false only if all its inputs are true; thus its output is
complement to that of the AND gate. A LOW (0) output results only if both the inputs
to the gate are HIGH (1); if one or both inputs are LOW (0), a HIGH (1) output
results. It is made using transistors and junction diodes.
(dccxlix) Circuit simulation using Cadence :
(dccl) 1) Connect the circuit as shown in Figure
(dccli) 2) Perform DC analysis to obtain VTC of the NAND gate and compare it with VTC
of a inverter.
(dcclii) 3) Perform transient analysis to find out of the delay of NAND gate and verification
of truth table. Also compare gate delay of NAND gate with the delay of a inverter.
(dccliii)

(dccliv)
(dcclv) Figure :- 2-input NAND gate
(dcclvi) Assignment :- Simulate DC and transient analysis of 2-input NOR gate and
compare with inverter, 2-input NAND gate.

(dcclvii)

Experiment No. 14

(dcclviii)

Aim:- implement Boolean function (half adder) using transmission

gates (TG), pass transistor logic (PTL) and verify the truth table by simulating
the circuits.

(dcclix)

Software :- Cadence Encounter

(dcclx) Theory :
(dcclxi) In principle, a transmission gate made up of two field effect transistors, in which in contrast to traditional discrete field effect transistors - the substrate terminal (Bulk)
is not connected internally to the source terminal. The two transistors, an n-channel
MOSFET and a p-channel MOSFET are connected in parallel with this, however,
only the drain and source terminals of the two transistors are connected together.
Their gate terminals are connected to each other via a NOT gate (inverter), to form
the control terminal.
(dcclxii) In electronics, pass transistor logic (PTL) describes several logic families used in
the design of integrated circuits. It reduces the count of transistors used to make
different logic gates, by eliminating redundant transistors. Transistors are used as
switches to pass logic levels between nodes of a circuit, instead of as switches
connected directly to supply voltages. This reduces the number of active devices, but
has the disadvantage that the difference of the voltage between high and low logic
levels decreases at each stage. Each transistor in series is less saturated at its output
than at its input. If several devices are chained in series in a logic path, a
conventionally constructed gate may be required to restore the signal voltage to the
full value.
(dcclxiii)

Circuit simulation using Cadence :-

(dcclxiv) 1) Connect the circuit as shown in Figures .

(dcclxv)
(dcclxvi) Figure :- Half adder implementation using Transmission gates (TG)

(dcclxvii)
(dclxvi)
(dcclxix) Figure :- Half adder implementation using Pass Transmission Logic (PTL)
(dcclxx) 2) Perform transient analysis as done for inverter and apply the input waveforms
with covering all input patterns. Output for all possible input patters can be checked
now.
(dcclxxi) Assignment :- Similarly verify the truth table for full adder circuit.
(dcclxxii)
(dcclxxiii)
(dcclxxiv)
(dcclxxv)
(dcclxxvi)
(dcclxxvii)
(dcclxxviii)
(dcclxxix)
(dcclxxx)
(dcclxxxi)
(dcclxxxii)
(dcclxxxiii)
(dcclxxxiv)
(dcclxxxv)
(dcclxxxvi)
(dcclxxxvii)

(dcclxxxviii)
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(dccxc)
(dccxci)
(dccxcii)
(dccxciii)

(dccxciv)

Experiment No. 15

(dccxcv) Aim: Simulate D Flip-Flop and observe the effects of Set Up and Hold time
on output response.
(dccxcvi) Software :- Cadence Encounter.
(dccxcvii) Theory :(dccxcviii) Consider the D-latch circuit diagram given in Figure , which shows a basic twoinverter loop and two CMOS transmission gate (TG) switches. The TG at the
input is activated by the CK signal, whereas the TG in the inverter loop is activated
by the inverse of the CK signal, CK. Thus, the input signal is accepted (latched)
into the circuit when the clock is high, and this information is preserved as the state
of the inverter loop when the clock is low. The operation of the CMOS D-latch
circuit can be better visualized by replacing the CMOS transmission gates with
simple switches, as shown in Figure B. A timing diagram accompanying this figure
shows the time intervals during which the input and the output signals should be
valid.

(dccxcix)
(dccc) Figure :- CMOS implementation of the D-latch

(dccci)
(dcccii)

Figure :- Simplified schematic view and the corresponding timing diagram of the
CMOS D- latch circuit, showing the setup time and the hold time.

(dccciii) Note that the valid D input must be stable for a short time before (setup time,
tsetup) and after (hold time, thold) the negative clock transition, during which the
input switch opens and the loop switch closes. Once the inverter loop is completed
by closing the loop switch, the output will preserve its valid level. In the D-latch
design, the requirements for setup time and hold time should be met carefully. Any
violation of such specifications can cause metastability problems which lead to
seemingly chaotic transient behavior, and can result in an unpredictable state after
the transitional period.
(dccciv)

Circuit simulation using Cadence :-

(dcccv)

1) Connect the circuit as shown in Figure A.

(dcccvi) 2) During transient analysis, keep reducing the time difference between clock and
D-input before as well as after the clock. Also measure the setup and hold time.
(dcccvii) Assignment :- Find out a new D-latch design from design which has less setup
and hold time.
(dcccviii)
(dcccix)

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