2014 International Conference on Electronic Systems, Signal Processing and Computing Technologies

Design of Phase Frequency Detector and Charge

Pump for Low Voltage High Frequency PLL
Aniruddha C. Kailuke

Pankaj Agrawal

Department of Electronics & Communication Engineering

P.I.E.T.
Nagpur, India

Department of Electronics & Communication Engineering

R.C.O.E.M.
Nagpur, India

R. V. Kshirsagar
Department of Electronics Engineering
P.C.E.
Nagpur, India
commonly used for its high operation speed, low power
consumption, and wide input range. The proposed PFD
consists of 22 transistors. When CKref is equal to CKout, both
the outputs, that is, Up and Down signals are zero. If CKref is
high compared to CKout then up signal is high else down signal
is high indicating the phase error between CKref and CKout. The
conditions of inputs and outputs are depicted in state machine
diagram shown in Fig. 2 [4]. The Dickson charge pump [2] is
shown in Fig. 3.

AbstractA simple new phase frequency detector and

integrated Dickson Charge pump design with charge transfer
switches (CTSs) are presented in this paper. The proposed
Phase-Frequency Detector (PFD) and Charge-Pump are useful
for low voltage, high frequency Phase-Looked-loops (PLL). This
brief analyzes the blind zone in latch-based PFDs and proposes a
technique that removes the blind zone caused by the precharge
time of the internal nodes. With the proposed technique, the PFD
achieves a small dead zone. The experimental results shows that
the proposed PFD has minimal dead zone compared with the
conventional PFD and CTS based Dickson charge pump is the
best structure for integration. The PFD and Charge Pump are
designed and simulated on Tanner 13.0V tool and has been
simulated in a 0.18m CMOS technology.

The Dickson charge pump circuit consists of two pumping

clocks 1, and 2, which are anti-phase and have voltage
amplitude of V.

KeywordsPhase Frequency Detector (PFD), Dead Zone,

Charge Pump (CP), Phase lock loop (PLL)

I. INTRODUCTION
Charge pump based phase-locked loops (PLLs) have been
widely used in many high-speed designs, such as high-speed
microprocessors or communication systems [1-4]. This type of
PLL often includes a phase frequency detector (PFD) to
monitor the phase and frequency differences between its two
inputs and transfers the information to the charge pump
generating the voltage signal that controls the frequency of the
voltage-controlled oscillator [3]. The basic architecture of PFD
is as shown in Fig. 1 [4]. The design consists of two flip-flops
and a NAND gate to provide a reset path when both outputs go
high at the same time. The PFDs are usually built with memory
elements, and thus, they need a reset signal to clear the memory
elements. Due to the reset path this design suffers from large
dead zone. The dead-zone problem occurs when the rising
edges of the two clocks to be compared are very close and it is
the minimum pulse width of the PFD output that is needed to
turn on the charge pump completely. Due to lots of reasons
such as circuit mismatch and delay mismatch, the PFD has a
difficulty in detecting such a small difference [4]. The PFD
doesnt detect the phase error when it is within dead zone
region and PLL locks to a wrong phase. PFD is the most
978-1-4799-2102-7/14 $31.00 2014 IEEE
DOI 10.1109/ICESC.2014.21

Fig 1. Basic architecture of PFD

Fig. 2. PFD state machine diagram

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The diodes operate as self-timed switches characterized by

a forward bias voltage, Vd. Stray capacitance, Cs, is the
multiplier operates by pumping charge along the diode chain as
the capacitors are successively charged and discharged during
each clock cycle. When clock phase  goes low, diode D1
conducts until the voltage at node 1 becomes (Vin Vd). When
 is switched to V the voltage at node 1 now becomes [Vin +
(V Vd)] this causes diode D2 to conduct until the voltage at
node 2 becomes equal to

Vin + (V Vd ) Vd
When  goes low again, the voltage at node 2 becomes

Vin + 2 (V Vd ) Vd
After N stages, it is easy to see that the output voltage is

VOUT = Vin + N (V Vd ) Vd

Fig. 4b. Schematic of Modified D flip-flop

(1)

II. CIRCUIT DESCRIPTION OF PFD

The stray capacitance, Cs, can be taken into account by
noticing that it reduces the transferred clock voltage V, by a
factor(C/C+Cs). Thus, the actual output voltage becomes

VOUT = Vin + N ((

Traditional D flip flops are modified to satisfy the required

function of D flip-flop for PFD. The operations of the proposed
D flip flop are very simple. When input clock and reset signals
are low, the node A is connected to Vdd through M1, M2 and
charges the node A to Vdd as shown in Fig. 4a and Fig. 4b. At
the rising edge of the clock signal, output node is connected to
ground through M3 and M4. Once the node A is charged to
Vdd, the output node is not affected by input clock signal.
Because the charge at node A turn off the M3 and this prevents
the output node from pulled up. Therefore, the output node is
disconnected from input node. When the reset signal is applied,
node A is disconnected from Vdd by Mr1 and connected to
ground by Mr2. As soon as the node A is discharged, the
output node is pulled up through M2. The Mr1 is added to
prevent the short circuit that happens whenever the reset signal
is applied. If the clock signal is low and reset signal is high, a
current path is made from Vdd to ground without Mr1. This
increases the power consumption. Moreover, the reset time is
increased because M1 charges the node A to Vdd while the
Mr2 discharges node A to ground. Fast discharging node A
means the fast reset operation. The operations of D flip flop in
Fig. 4a & Fig. 4b are same but the connection is different. The
output wave form of PFD with modified D flip flop is shown in
Fig. 8 where both input i.e. CLK and RST are in phase.
Dynamic power consumption can be reduced by lowering the
internal switching and speed is increased by shortening the
input to output path. A conventional sequential type PFD
structure is used. For high-speed operation, a pseudo NAND
gate is used. The W/L ratio of proposed PFD can be calculated
as shown in (2) with assuming minimum current through each
branch. Equations (3) and (4) give the current through PMOS
and NMOS respectively.

C
)V Vd ) Vd
C + CS

The following Fig. 4a and Fig. 4b shows schematic of

Traditional and the Modified D flip-flop respectively which is
used to design the proposed architecture of PFD with NAND
gate.

Fig 3. Dickson Charge Pump

2
W
I D = K ! (Vgs Vth )
L
2
W
I D = p Cox (Vgs Vth )
L

Fig. 4a. Schematic of Traditional D flip-flop

2
W
I D = n Cox (Vgs Vth )
L

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(2)

(3)
(4)

III. ARCHITECTURE OF MODIFIED DICKSON CHARGE PUMP

This paper describes new charge pumps that are suitable for
low-voltage operation and offer better voltage pumping gains
and higher output voltages than the Dickson charge pump
[5,6]. The design of new Dickson charge pump is shown in
Fig.5a. The circuit consists of two pumping clocks 1 and 2,
which are anti-phase and have voltage amplitude of V. The
diodes are replaced by MOS transistor. The multiplier chain is
implemented using diode-connected NMOS transistors. Here
the diode forward voltage, Vd, is replaced by the MOS
threshold voltage, Vth. C1C4 are the coupling capacitors where
the two clocks 1 and 2 push the charge voltage upward
through the transistors. Neglecting the boundary conditions, the
voltage fluctuation at each pumping node V is identical and
can be expressed as shown in (5).

AP = AP1 = V = V2 V1 = VCLK

I0
C

C + C S f (C + C S )

Fig. 6. The modified Dickson Charge pump with static charge transfer switches
(Design-1)

MD1MD4 are diodes for setting up the initial voltage at each

pumping node. They are not involved in the pumping
operation. MS1MS4 are the CTSs. The idea is using the
already established high voltage to control the CTS of the
previous stage. If the switches can be turned on and turned off
at the designated clock phases, they can also allow the charge
to be pushed in only one direction. Then for each pumping
stage, the upper voltage of the input is equal to the lower
voltage of output, since the MOST switches is turned on at this
moment. The voltage pumping gain per stage can be expressed
as

(5)

Where Cs is the parasitic capacitance associated with each

pumping node, f- is the frequency of the pumping clocks, and
I0 is the output current loading. This is the voltage change that
occurs at each node of a charge pump from one clock cycle to
the next. This is illustrated for the four stage Dickson charge
pump in Fig. 5b.
IV. CHARGE PUMP USING STATIC CTSS (DESIGN-1)

AP = AP1 = V = V2 V1

The modified Dickson Charge pump with static charge

transfer switches is as shown in Fig. 6. The MOS transistor
switches with proper on/off cycles, are used instead of the
diodes to direct the flow of charges in pumping operation,
referred to as CTSs. The CTSs have been used to realize the
charge pumps and show better voltage pumping gain than the
diodes.

(3)

A five-stage Design-1 has been simulated using a standard

0.18m CMOS technology. This prototype is similar to the
circuit shown in Fig. 6, except that MD5 and MD0 are merged
into one device, the pumping capacitor C5 is connected to the
source node of MD0, and the output voltage is smoothed by an
RC low-pass filter [3]. The gate geometric size is 180nm for all
devices. All pumping capacitors are 50 pF. The circuit is used
in a 1.8V switched-capacitor system for driving MOST analog
switches.
V. CHARGE PUMP USING DYNAMIC CTSS (DESIGN-2)
If the reverse charge sharing phenomenon inherent in the
Design-1 circuit can be eliminated, better pumping
performance can be obtained. In other charge pump designs [8
- 11], each CTS is accompanied by an auxiliary pass transistor
so that the CTSs can be turned off completely in the designated
period. However, the CTS in those charge pumps are difficult
to turn on in the low-voltage environment. Techniques such as
putting CTS in individual wells to eliminate the body effect
and applying boosted clocks to drive the CTS have been used
[3]. The four-phase clock scheme has also been used to
precharge the CTS so that they become easier to turn on [9,
10]. However, additional concern is that the auxiliary pass
transistors must be turned on during the precharging phase.
Fig. 7 shows a new charge pump (Design-2) that can assign the
control inputs for the CTS dynamically by adding pass
transistors MN and MP to the NCP-1 circuit [3].

Fig.5a. New Dickson Charge Pump

Fig..5b. Voltage Fluctuation

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Fig. 8. The waveforms of proposed PFD with NAND gate when the input
frequency is ~1GHz and two inputs are in phase

Fig. 7. The modified Dickson Charge pump with Dynamic charge transfer
switches (Design-2)

The CTSs in NCP-2 can be turned off completely when

required and still can be turned on easily by the backward
control as in the NCP-1 case. The expression for the singlestage voltage pumping gain is the same as (3). Fig. 8 shows the
simulation results of modified Dickson Charge pump with
Dynamic charge transfer switches (Design-2) and output
current is 0.05A. All charge pumps have four pumping stages.
All coupling capacitors are 50 pF. The voltage smoothing
capacitor at the output is 100pF. The frequency of the pumping
clocks is 4 MHz. The V for the Design-2 is less than that
predicted by (1) due to additional parasitic capacitors and
switching delay. Nevertheless, the Design-2 still exhibits the
best charge pumping performance among the three circuits.

Fig. 9. Measured dead zone of proposed PFD for 10MHz to 1GHz frequency

VI. SIMULATION RESULTS

The proposed PFD based on Modified D Flip Flop with
NAND gate is simulated on Tanner 13 in 0.18m CMOS
process with 1.8V supply voltage. Fig. 8 shows the output
waveforms of Modified D Flip Flop PFD having input
frequency is 1GHz and both input are in phase i.e. FEB and
REF having zero degree phase difference. The Measured dead
zone of proposed PFD for 10MHz to 1GHz frequency is shown
in Fig. 9. The prototype can maintain a 3V output while
providing 12.71A of output current. For comparison, the
output voltage of a five-stage Dickson charge pump operating
under the identical condition is less than 2V. The output
waveforms of modified Dickson Charge pump are shown in
Fig. 10. The output waveforms of modified Dickson Charge
pump with Dynamic charge transfer switches (Design-2) is
shown in Fig. 11. The performance of all PFD and Dickson
Charge pump is shown in Table I.

Fig. 10. Output waveforms of modified Dickson Charge pump with CTSs

Fig. 11. Output waveforms of modified Dickson Charge pump with Dynamic
charge transfer switches (Design-2)

VII. CONCLUSION
This paper demonstrates two techniques for designing
PFDs using Conventional D Flip Flop and Modified D Flip
Flop which is simulated with operating clock frequency
greater than 1GHz with minimal dead zone. Even for highperformance systems with clock frequency less than 1GHz the
proposed PFDs acquire frequency lock more quickly. This
PFD is suitable for high frequency PLL application without
frequency divider network in feedback.

In the Charge Pump as the supply voltage decreases, both

V and V are decreased accordingly, and the voltage
pumping gain per stage is also reduced. Furthermore, if V is
not much larger than the MOSTs threshold voltage, then the
influence of the MOSTs body effect cannot be neglected.

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TABLE I. PERFORMANCE COMPARISON OF ALL DICKSON CHARGE PUMPS

Charge Pump

PFD

Parameter

New
Dickson
CP

Design-1

Design-2

Parameters

Technology

0.18m

0.18m

0.18m

Tool

VDD

1.8V

1.8V

1.8V

Technology

70pF

50pF

50pF

12.71A

0.05A

1.8V to
3V

1.8V to
6V

Max.
Capacitor
Output
Current
V(Out)
Range

51.55
A
1.8V to
4.2V

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Supply
Voltage
Maximum
Frequency
Dead zone

Proposed
PFD

Tanner
13.0V
0.18m
1.8V
1GHz
Free

Charge pumps utilizing CTSs to direct charge flow can

provide better voltage pumping gain than those using MOST
diodes. The resulting charge pumps (Design-1) can operate
under a supply voltage below 1.8V and still offer good
pumping performance. The reverse charge sharing
phenomenon inherent in the Design-1 circuits can be
eliminated by applying dynamic control to the CTSs. The
Design-2 charge pumps use two additional MOSTs per stage
to implement the dynamic CTSs. The performance
improvement of the Design-2 over the Design-1 is more
significant at higher supply voltages.
ACKNOWLEDGMENT
Authors are thankful to Priyadarshini College
Engineering Research centre for using their laboratory.

of

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