INTELLIGENT ANTENNAS

Antenna front end can be split to the basic antenna element an the related array configuration and processing blocks. Antenna size
is proportional to the operating radio frequency. The main activities in antenna domain to enable SDR concept (to support the
broad range of frequencies with the same antenna elements) are in array processing blocks and techniques to make the antenna
systems more performing and intelligent
Smart antennas (also known as adaptive array antennas, multiple antennas and recently MIMO) are antenna arrays with smart
signal processing algorithms used to identify spatial signal signature such as the direction of arrival (DOA) of the signal, and use it
to calculate beam forming vectors, to track and locate the antenna beam on the mobile/target. The antenna could optionally be any
sensor.

DOA (DIRECTION OF ARRIVAL)

The smart antenna system estimates the direction of arrival of the signal, using techniques such as MUSIC (Multiple Signal
Classification), estimation of signal parameters via rotational invariance techniques (ESPRIT) algorithms, Matrix Pencil method or
one of their derivatives. They involve finding a spatial spectrum of the antenna/sensor array, and calculating the DOA from the
peaks of this spectrum. These calculations are computationally intensive.
Matrix Pencil is very efficient in case of real time systems, and under the correlated sources.
BEAM FORMING

Two of the main types of smart antennas include switched beam smart antennas and adaptive array smart antennas. Switched beam
systems have several available fixed beam patterns. A decision is made as to which beam to access, at any given point in time,
based upon the requirements of the system. Adaptive arrays allow the antenna to steer the beam to any direction of interest while
simultaneously nulling interfering signals [3]. Beamdirection can be estimated using the so-called direction-of-arrival (DOA)
estimation methods.

PROGRAMMABLE RF MODULES
The RF section (also called as RF front-end) is responsible for transmitting/receiving the radio frequency (RF) signal from the
antenna via a coupler and converting the RF signal to an intermediate frequency (IF) signal. The RF front-end on the receive path
performs RF amplification and analog down conversion from RF to IF. On the transmit path, RF front-end performs analog up
conversion and RF power amplification. It is a challenging task to cover the entire frequency band with the same peace of
equipment. The essential RF component both in transmitter and receiver are band pass filters. In the SDR based RF domain the
real challenge is to design programmable band pass filters. One of the employed techniques for existing SDR systems is to use a
bank of RF modules. The Wideband synthesizer, MEMS and superconductor technologies and low noise high performance
semiconductor processes are the subjects of active research in this domain..

WITH PROGRAMMING WE CAN ADJUST

a.

operating range of frequencies(300-928 MHz)

b.

convert to intermediate frequencies

c.

output power level(attenuation or gain)(+/- 60 dbm)

d.

data rate( 1.2-500kbps)

e.

operating supply voltage(1.8-3.6V)

f.

sensitivity(250kbps: -88dBm)

Digital-to-Analog and Analog-to-Digital Conversion

They are the doors between physical and digital domains. The realization of a true SDR based systems depend upon their
performance. In related literature, it is said that the goal of the SDR concept is to connect the converters directly to antenna
element. The traditional converters are pushing the envelope to achieve more resolution and faster conversion rates. The superconductivity and optical sampling techniques are the area of active research to achieve even higher performance.

DIGITAL DOWN CONVERSION(DDC) AND DIGITAL UP CONVERSION(DUC) AND BASEBAND

OPERATION

DDC/DUC blocks perform digital-down- conversion (on receive path) and digital-up-conversion (on transmit path), respectively.
DUC/DDC blocks essentially perform modem operations, i.e., modulation of the signal on transmit path and demodulation (also
called digital tuning) of the signal on receive path. The baseband section performs baseband operations (connection setup,
equalization, frequency hopping, timing recovery, correlation) and also implements the link layer protocol (layer 2 protocol in OSI

protocol model).

The DDC/DUC and baseband processing operations require large computing power and these modules are

generally implemented using ASICs or stock DSPs.

Digital Signal Processing (DSP)

DSP is the key element to realize SDR based systems. The sampling techniques, rate conversion and multi-rate processing DSP
techniques have been instrumental in the progress of SDR [essential]. To implement DSP algorithms to enable SDR concept, the
candidate technologies are PDSP, ASICS, FPGA and mixture of them.

PDSP play a prominent role in SDR

1.They offer development flexibility and are used primarily for number crunching operations in DSP algorithms. They have been
used extensively for advanced digital communications transceiver designs and finding their way into detection, equalization,
demodulation, frequency synthesis and channel filtering.
The PDSP are not fast enough to implement all radio functions.

High-speed instruction set processors are increasing in speed, decreasing in feature size, and improving low-power operation. As
these new generations of chips begin to appear and feature size continues to decline, there are proportionate increase in speed,
power efficiency and heat dissipation

2.ASICS Application Specific Integrated Circuit (ASIC) is fast but not flexible; limited ability to add/modify new feature once the
device is in the market. Companies that have tried to design parametized ASICs, have found that it takes an order of magnitude
more effort to create the parameterized ASICS. This has led to Time-to-Market problems.
Field Programming Gate Arrays (FPGA) is an ASICS, which contain DSP blocks that can be re-configured to work as parallel
multiplier/adder or MAC. They contain block/distributed memories, PLLs and programmable routing capabilities among the
blocks. FPGA are extremely flexible and fast. Their performance is increasing rapidly to provide the flexibility of PDSP and the
speed of ASICs. The following table, taken from [2], shows the comparison between PDSP, ASICs and FPGAs.

Interconnect Technologies:
It is required for a SDR enabled system to have the ability to connect various independent functional blocks to setup a radio link.
The interface standards are needed to be developed within framework of an interconnect technology. Three main interconnect
architectures are Bus, Switch fabric and tree. The following table shows the comparison of these three architectures

Software architecture:
Software architecture can be grouped into 4 basics levels of programmability.
1. Higher level Protocols like WAP and TCP/IP
WAP: Wireless Application Protocol (WAP) is a technical standard for accessing information over a mobile
wireless network.WAP helps in accessing emails,websites,news or sports updates,downloading mobile
applications,musics or videos over GSM,IS-95(CDMA) networks.
TCP/IP:Transmission control protocol helps in accessing internet over fixed or mobile connections.It assigns a
unique IP address to all the hardware resources(routers and modems) presents in network thus establishing
connection between them.It implements network and transmission layer of OSI-7 model.
2.Radio application: Link layer Protocols and modulation/demodulation.The important
modulation/demodulation presents are GMSK for GSM/GPRS services and Spread Spectrum techniques for

CDMA applications In SDR system, the software modules that implement link- layer protocols and
modulation/demodulation operations are called radio applications and these applications provide link-layer
services to higher layer communication protocols such as WAP and TCP/IP.
3.Operating Environment (hardware resource management,memory management, interrupt management). The
operating environment performs hardware resource management activities like allocation of hardware resources
to different applications, memory management, interrupt servicing and providing a consistent interface to
hardware modules for use by applications.
Hardware resources: The system uses a generic hardware platform with programmable modules (DSPs, FPGAs,
microprocessors) and analog RF modules.

SOFTWARE ARCHITECTURE:

Model based design

CANDIDATE LANGUAGES AND TOOLS

META LANGUAGE FOUNDATION CANDIDATE
1.

C/C++

2.

VERILOG/MATLAB

3.

MATLAB

4.

SYSTEM C/SYSTEM VERILOG

5.

UML/XML

6.

n ML/LISA

7.

WIRELESS MARKUP LANGUAGE(WML)

8.

PROLAC(MIT)

MODELLING TOOL FOUNDATION CANDIDATE

1.

COSSAP(SYNOPSYS)

2.

SPW(CoWARE)

3.

SIMULINK(MATLAB Hardware)

4.

ML DESIGNER(ML Design Technologies)

5.

METROPOLIS(UC BERKLEY)

6.

PTOLEMY(UC BERKLEY)

7.

RHAPSODY(I LOGIX)