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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010

A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution

Sub-Exponent TDC in 0.18 m CMOS
Seon-Kyoo Lee, Young-Hun Seo, Hong-June Park, Member, IEEE, and Jae-Yoon Sim, Member, IEEE

AbstractAn all-digital PLL for wireline applications is designed with a sub-exponent TDC which adaptively scales its
resolution according to input time difference. By cascading 2
time amplifiers, the TDC efficiently generates the exponent-only
information for fractional time difference. To improve linearity
in a wide input range, a replica-based self-calibration scheme is
applied to the time amplifier. The TDC, implemented in a 0.18 m
CMOS, shows the minimum resolution of 1.25 ps with a total
conversion range of 2.5 ns, the maximum operating frequency of
250 MHz, and power consumption of 1.8 mW at 60 MHz. The
measured rms jitter of PLL was 5.03 ps at 960 MHz.
Index TermsAll-digital PLL, PLL, time amplifier, time-to-digital converter.

I. INTRODUCTION
N RECENT few years, replacement of analog blocks with
robust digital circuits has been a leading drive in the development of circuit technologies. All-digital phase-locked loop
(ADPLL) is one of the most actively researched topics as it gives
many advantages of improved programmability, insensitivity to
PVT variations, and small size by avoiding the use of large
capacitors for the loop filter [1], [2]. To achieve jitter performance comparable to analog PLL, however, quantization error
should be sufficiently reduced by improving the resolution of
time-to-digital converter (TDC) and digitally-controlled oscillator (DCO). Since the resolution and linearity of DCO can be
improved by reducing the gain of DCO or by using a high-frequency sigma-delta modulator at the front stage of DCO [3],
TDC becomes a major bottleneck limiting the performance of
ADPLL.
Bang-bang phase-frequency detector (PFD), as the one bit
TDC, is often used in wireline DPLL for its simplicity [4].
But, the bang-bang operation results in the trade-off limitation
between frequency acquisition time and jitter performance [5]
since it provides only one bit (i.e., up/dn) information to the
loop filter. To improve the jitter performance with bang-bang
PFD, the one bit output should be effectively scaled with
additional logic as the lock process goes on [6]. In most cases,

Manuscript received April 20, 2010; revised July 12, 2010; accepted August
09, 2010. Date of publication October 25, 2010; date of current version December 03, 2010. This paper was approved by Guest Editor Jae-Yoon Sim. This
work was supported by IDEC and Basic Science Research Program through the
National Research Foundation grant funded by the Korean Government (NRF2010-0001875).
The authors are with the Department of Electronic and Electrical Engineering,
Pohang University of Science and Technology (POSTECH), Pohang, Kyungbuk
790-784, Korea (e-mail: leesk@postech.ac.kr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/JSSC.2010.2077110

Fig. 1. Previous approaches for fine resolution TDC; (a) vernier TDC,
(b) 2-step TDC, and (c) noise shaping TDC.

multi-bit linear TDCs are more preferred for flexible control

of ADPLL bandwidth [7]. However, the resolution of multi-bit
linear TDC is closely related to process technology since the
minimum resolvable time quantity is proportional to one-inverter delay [8].
For fine time resolution in linear TDC, vernier delay line
shown in Fig. 1(a) is generally considered [9], [10]. Since the
time resolution is determined by the difference between two inverter delays,
, an excessive number of inverter stages are
required to cover large detection range, causing long conversion
time and large power consumption. For large conversion range
with a small number of delay cells, logarithmic conversion can

0018-9200/$26.00 2010 IEEE

LEE et al.: A 1 GHZ ADPLL WITH A 1.25 ps MINIMUM-RESOLUTION SUB-EXPONENT TDC IN 0.18 m CMOS

be considered [11]. The logarithmic digitization, however, additionally requires the post-linearization process with a look-up
table for the converted number to be applied to the digital loop
filter.
Well-established data conversion architectures have been also
sought to form TDCs with proper circuit schemes handling signals in time domain [12], [13]. Fig. 1(b) shows the two-step
TDC [12] to improve both the resolution and detectable range by
amplifying the time residue after the coarse conversion for the
fine conversion. But, the time amplification schemes [12], [14]
utilize the delay increase by metastability and suffer from small
input range and uncertainties of gain due to nonlinearity and
PVT variations. Another approach is to adopt a noise-shaping
feature in TDC to improve effective resolution. Fig. 1(c) shows
the first-order noise shaping TDC scheme with a multi-phase oscillator [13]. By storing the time residue in the form of voltage
on the capacitance of each node in the oscillator, the unconverted time residue is effectively added to the input of the next
conversion, hence compensation of the current stages quantization error in the following stages. However, since the noise
shaping is based on the first order delta-sigma conversion with
multiple sampling of input, high resolution is not guaranteed for
fast-varying input. In addition, the multiphase generation and
multiple counters consume large power when used with a gated
ring oscillator (GRO) for higher resolution.
This paper presents a novel concept of a power-efficient subexponent TDC [15] suitable for wireline ADPLL. Based on a
self-calibrated cascaded chain of 2 time amplifiers, the proposed TDC generates the exponent-only information for the
fractional time difference and effectively achieves the minimum
resolution of 1.25 ps even with a 0.18 m digital CMOS process.
Section II describes circuits of the proposed TDC and ADPLL
with simulation results. Section III shows the measurements,
and Section IV concludes this work.
II. CIRCUIT DESCRIPTION
A. TDC
The block diagram of the proposed TDC is shown in
Fig. 2(a). The TDC consists of a front-end PFD, an integer
TDC, and a sub-exponent TDC. The front-end PFD is the
conventional PFD typically used in an analog PLL and it is
included in the proposed TDC for the function of frequency
detection. The integer TDC is the conventional 5-bit TDC with
one bit resolution of two-inverter delay defined as ( 80 ps
),
in 0.18 m CMOS). For the fractional time difference (
as shown in Fig. 2(b), the sub-exponent TDC generates 1-ofencoded 7-bit output with each bit representing a fraction of
of the two inverter delay, respectively.
Since both the 5-bit output of the integer TDC and the 7-bit
output of the sub-exponent TDC follow the binary number
system, two outputs can be directly merged to form a 12-bit
binary number. Therefore, the proposed sub-exponent TDC
greatly improves the dynamic range and resolution for smaller
input while keeping linearity with the integer TDC for larger
input, resulting in a fast lock time and low jitter performance
when used in a PLL.

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Fig. 2. (a) Block diagram and (b) transfer curve of the proposed TDC.

Fig. 3 shows the circuit diagram of the sub-exponent TDC. The

output of PFD is applied to the cascade of six stages of 2 time
amplifiers (TAs). The input time difference is amplified by twice
on each stage as propagated through the chain of TAs. The output
of each stage is tested by an integer checker. The integer checker
is the 1-bit TDC and outputs ONE if the time difference is larger
than which is two-inverter delay which is equal to the one bit
resolution of the integer TDC. With the chain of XORs, the outputs of the integer checkers are simply converted to a 7-bit 1-ofcode. Since the integer ONE corresponds to 80 ps,
to
represent 40 ps
to 1.25 ps
, respectively.
The LSB
covers all the cases less than 1.25 ps, resulting in the
minimum resolution of 1.25 ps which is the same as . When
PLL is in locked state, the input to the TDC is smaller than the
resolution of the integer TDC. To reduce the power consumption,
the integer TDC is disabled for a small input difference by using
an extra integer checker at the input stage of TA chain, and only
the sub-exponent TDC operates.
Fig. 4 shows the brief schematic of the 2 time amplifier proposed in this work. The nodes A and B are initially pre-charged
to
when two inputs are low. The output of the TA is determined by the discharging times of A and B when rising transitions of the inputs are applied. The discharging is performed
by two pull-down paths an inverter-driven path, by M1 and
M3, and a dependent path, by M2 and M4. The strength of one
dependent path is determined by the discharging status of the
counterpart node. In other words, the first transition makes the
other transition slower by reducing the strength of the dependent
path, resulting in an amplified time difference. Assuming W/L
of M1M4 are identical, the first discharging is performed by
two identical pull-down paths at the initial phase of transition.

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010

Fig. 3. Circuit diagram of the proposed sub-exponent TDC.

2 TA.

Fig. 4. Conceptual circuit diagram of the proposed 2

But the second discharging is performed by only one pull-down

path at the end of the transition. So the gain of TA becomes
roughly two for small input case. In the case of large input, however, the amount of delay increase becomes saturated, so the
output shows an additional delay offset with the gain of one.
To increase the input range of TA, the inverter-based independent discharging path shown in Fig. 4 is modified to be another dependent path and calibrated (Fig. 5). Similarly to M2
and M4, the strengths of M1 and M3 are controlled by the other
input. But, the pMOS diodes make slow discharging on C and
D and also guarantee M1 and M3 not completely turning off to
ensure A and B to be fully discharged to ground. To achieve a
stable gain of two in wide input range, an one-point calibration
scheme is used with a replica TA. The size of pMOS diodes is
digitally calibrated so that the replica TA would experience the
output difference of
at the point of the input difference of
. As shown in the simulation results in Fig. 6, the proposed
calibration achieves a high linearity for a wide input range of
upto 100 ps. This one-point calibration at slightly increases
the gain in the small input region showing the maximum gain
error of about 8% for the small input. But, the gain error in the
small input range affects little in the linearity performance since
it causes only a very small amount of time error when translated
into absolute time. Since this scheme does not require extra load
capacitor, simulation shows that the delay time from the first

Fig. 5. Full circuit schematic of TA with calibration.

input edge to the last output edge is only 200 ps for zero input
difference and 400 ps for the largest input difference of 100 ps.
This fast amplification gives another advantage of better adaptability to applications requiring high conversion rate of TDC.
In traditional data converters using cascaded amplifiers (e.g.,
pipelined ADC), an open-loop amplifier with the one-point
calibration does not give sufficient linearity. For example, an
open-loop amplifier with 10-percent gain error hardly achieves
more than 3-bit linearity when used in pipeline ADC. However,
the proposed sub-exponent TDC does not generate full uniform
code steps. The exponent-only conversion sees relative time
error normalized to each code step, and it greatly releases the
requirement in gain accuracy of TA, which will be described in
the next paragraph.

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2 TA; (a) transfer curve and (b) gain.

Fig. 6. Simulation results of 2

Fig. 8. (a) Acceptable TA gain error as a function of the number of stages for
given bit error requirements and (b) transfer curves of 7-bit sub-exponent TDC
with various cases of TA gain error.
Fig. 7. Cascaded TAs generating 1-bit at the
and (b) with gain error of .

"

N th stage (a) without gain error

To derive the requirement in TA gain, Fig. 7(a) shows the ideal

is
case with no gain error when an input time difference of
equal to after stages of time amplification, leading to
(1)
One bit error occurs when this amplified result equals to . Assuming the worst case combination with an identical gain error
of
in all TA stages as shown in Fig. 7(b), which results in
error accumulation through stages, the amplified output should
be smaller than
to keep the error of less than one bit. The
condition for less than one-bit error can be derived as
(2)
Otherwise, an integer will be generated in one of the previous
stages, causing an error in the output code. By substituting (1)
to (2), the requirement of the gain error for less than one bit can
be obtained as
(3)

When compared with the requirement

in traditional pipeline ADC, (3) is greatly released and easy to achieve
with the proposed open-loop time amplifier.
The reason for this released requirement can be understood as
follows. The number of stages required for the exponent generation increases as
becomes smaller. Only when
is small
enough to be in the range of the minimum resolution, it goes
through the whole stages to be compared with . In this case,
the small
also causes a small absolute time error in the output
even with a large gain error. So the gain error does not cause
one-bit error unless the gain error is larger than
. On the contrary, when the input is large, it goes through only a few stages to
generate the integer . In this case, even with a large gain error,
the small number of stages also causes a small time error compared with the corresponding one-bit resolution. Likewise, the
gain error does not cause one-bit error unless the gain error is
larger than the inverse of the number of stages. Fig. 8(a) shows
boundaries of acceptable gain error to maintain several cases of
normalized code error. The calculated transfer curves of TDC
with various cases of the gain error are also denoted in Fig. 8(b).
B. ADPLL
Fig. 9 shows the block diagram of designed ADPLL which
consists of the proposed TDC, a digital loop filter (DLF) [1],

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 45, NO. 12, DECEMBER 2010

Fig. 9. Block diagram of designed ADPLL.

Fig. 11. Photomicrograph of the test chip.

Fig. 10. (a) Behavioral model of ADPLL and (b) simulation results with various cases of TDC and DCO resolutions.

a ring-type 8-bit DCO with a first-order DSM, and feedback

dividers. The frequency of DCO is tuned by controlling the
pull-up resistance of four-stages of differential delay cells as in
[16]. For the clocking of DSM, half-divided output frequency
of DCO is used. The loop bandwidth and phase margin are designed to be 1 MHz and 70 , respectively.
Since the proposed TDC does not provide uniform resolution, the effect of exponent-only representation on jitter
performance of PLL needs to be characterized. To investigate
the effective resolution of sub-exponent TDC, the PLL with
various cases of TDC and DCO resolutions are simulated with
SPECTRE. As the jitter performance of PLL is also affected
by quantized DCO frequency, DCO resolution should be also
taken into account in performance characterization. To estimate
theoretical jitter performance affected only by the resolutions

Fig. 12. Measured and target transfer curves of the sub-exponent TDC.

of TDC and DCO, behavioral descriptions were taken for

modeling of TDC and DCO without including circuit-induced
imperfections. Fig. 10(a) shows the simulated behavioral model
of ADPLL with the same loop parameters as designed (Fig. 9).
The TDC is modeled with a delay chain and flipflops. The DCO

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Fig. 15. Jitter histogram of PLL.

TABLE I
PERFORMANCE SUMMARY

Fig. 13. Measured linearity performance of sub-exponent TDC with normalized (a) differential error (NDE) and (b) absolute error (NAE).

Fig. 14. Measured linearity performance of integer TDC: (a) DNL and (b) INL.

is modeled with a DAC followed by a VCO. In addition to

the sub-exponent TDC, four cases of uniform step TDCs with
resolutions of 0.3 ps, 1.25 ps, 5 ps, and 20 ps were simulated
for comparison. The resolution of DCO was swept for each
case. Fig. 10(b) shows the summary of simulated peak-to-peak
jitter performance as a function of DCO resolution. When TDC
resolution is small enough (e.g., 0.3 ps), it does not limit the
jitter performance. In this case, the performance is dominated
by DCO resolution. As the minimally resolvable time by
TDC increases, however, the quantized TDC output becomes
another limiting factor and the minimally achievable jitter also

increases. The proposed sub-exponent TDC with the minimum

resolution of 1.25 ps shows almost the same performance as
the case of the 1.25 ps-full-uniform step TDC.
This can be understood as followings. Once the jitter performance is limited by DCO quantization, fine resolution of TDC
does not give useful information in reducing the jitter. So the
output of finer TDC is no better than that of coarser TDC. On
the other hand, the sub-exponent TDC is able to scale its resolvable time down to 1.25 ps as needed. Therefore, the proposed
sub-exponent scheme provides a dramatically efficient architecture with greatly simplified circuit complexity without compromise of performance.
III. MEASUREMENTS
For verification, the designed PLL was fabricated in a
0.18 m CMOS. Fig. 11 shows the microphotograph of the
test chip. For the test of TDC resolution, a time sweeping input
was generated by two clock signals with a small difference
in frequency. Since the measurement of sub-exponent TDC is
significantly affected by the jitter in two input clocks, more
than 400 cycles of time-swept TDC outputs were collected with

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TABLE II
TDC PERFORMANCE COMPARISON

a logic analyzer. By measuring the cumulative code count, the

transfer curve was obtained with noise averaged out. Fig. 12
shows the measured transfer characteristics of the sub-exponent
TDC at a 50 MHz. As a reference, ideal sub-exponent transfer
curve is also denoted in the same figure. To quantify the code
linearity, the difference in time step between measured and ideal
curves is normalized to corresponding each-bit resolution and
is denoted by normalized differential error (NDE), representing
similar quantity of DNL. For a quantity representing INL, the
difference in code transition time between measured and ideal
curves is normalized and is denoted by normalized absolute
error (NAE). Without any missing code, the sub-exponent TDC
shows the maximum NDE of 0.3 bit and NAE of 0.4 bit as
shown in Fig. 13. The minimum resolution was 1.25 ps. The
maximum operating frequency was 250 MHz. With one integer
of 80 ps, the integer TDC covers a conversion range of
2.5 ns. Fig. 14 shows the measured linearity of integer TDC.
The PLL showed a lock range of 900-to-1250 MHz with a
DCO gain of 1.4 MHz/LSB. Fig. 15 shows the measured jitter
histogram at 960 MHz. The rms and peak-to-peak jitters were
5.03 ps and 35.6 ps, respectively, which are 0.48-percent and
3.4% of the output clock period. The TDC consumes 2 mA in
tracking phase and 1 mA in locked state due to the disabling of
the integer TDC. Table I summarizes performance of the PLL
and TDC. Table II shows comparison with previously reported
high-performance TDCs. The proposed TDC shows the best
performance in the minimum resolution, power consumption,
and conversion rate even with a 0.18 m CMOS.
IV. CONCLUSION
An all-digital PLL suitable for wireline applications is designed with a TDC which adaptively scales its resolution according to range of input time difference. For wide input range
and fine resolution, the proposed TDC consists of a conventional
integer TDC for integer-level time difference and a sub-exponent TDC which generates the exponent-only information for
fractional time difference. By cascading 2 time amplifiers with
an integer checker on each output stage, the exponent output is
efficiently obtained in terms of true-or-false representation. To
improve linearity in a wide time input range, a replica-based

self-calibration scheme is applied to the proposed open-loop

time amplifier. The TDC, implemented in a 0.18 m CMOS,
shows the minimum resolution of 1.25 ps with a total conversion
range of 2.5 ns, the maximum operating frequency of 250 MHz,
and power consumption of 1.8 mW at 60 MHz. The measured
rms jitter of PLL was 5.03 ps at 960 MHz.
REFERENCES
[1] V. Kratyuk et al., A design procedure for all-digital phase-locked
loops based on a charge-pump phase-locked-loop analogy, IEEE
Trans. Circuits Syst. II, vol. 54, no. 3, Mar. 2007.
[2] T. Olsson and P. Nilsson, A digitally controlled PLL for SoC applications, IEEE J. Solid-State Circuits, vol. 39, pp. 751760, May 2004.
[3] R. B. Staszewski, Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS
process, IEEE Trans. Circuits Syst. II, vol. 50, pp. 815828, Nov. 2003.
[4] J. A. Tierno et al., A wide power supply range, wide tuning range, all
static CMOS all digital PLL in 65 nm SOI, IEEE J. Solid-State Cir.,
vol. 43, no. 1, pp. 4251, Jan. 2008.
[5] V. Kratyuk, A digital PLL with a stochastic time-to-digital converter,
in Proc. Symp. VLSI Circuits, Jun. 2006, pp. 3839.
[6] S.-Y. Yang et al., A 7.1 mW 10 GHz all-digital frequency synthesizer
with dynamically reconfigurable digital loop filter in 90 nm CMOS,
in IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2009, pp. 9091.
[7] R. B. Staszewski et al., All-digital PLL and transmitter for mobile
phones, IEEE J. Solid-State Circuits, vol. 40, pp. 24692482, Dec.
2005.
[8] R. B. Staszewski et al., 1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS, IEEE Trans. Circuits Syst. II, vol.
53, no. 3, pp. 220224, Mar. 2006.
[9] P. Dudek et al., A high-resolution CMOS time-to-digital converter
utilizing a vernier delay line, IEEE J. Solid-State Cir., vol. 35, no. 2,
pp. 240247, Feb. 2000.
[10] J. Yu et al., A 12-bit vernier ring time-to-digital converter in 0.13 m
CMOS technology, in IEEE Symp. VLSI Circuits Dig., Jun. 2009, pp.
232233.
[11] J. Lin et al., A PVT tolerant 0.18 MHz to 600 MHz self-calibrated
digital PLL in 90 nm CMOS process, in IEEE Int. Solid-State Circuits
Conf., Feb. 2004, pp. 488489.
[12] M. Lee et al., A 9 b, 1.25 ps resolution coarse-fine time-to-digital
converter in 90 nm CMOS that amplifies a time residue, in IEEE Symp.
VLSI Circuits Dig., Jun. 2007, pp. 168169.
[13] M. Z. Straayer et al., An efficient high-resolution 11-bit noise-shaping
multipath gated ring oscillator TDC, in IEEE Symp. VLSI Circuits
Dig., Jun. 2008, pp. 8283.
[14] A. M. Abas et al., Time difference amplifier, IEE Electronics Lett.,
vol. 38, no. 23, pp. 14371438, Nov. 2002.
[15] S.-K. Lee et al., A 1 GHz ADPLL with a 1.25 ps minimum-resolution sub-exponent TDC in 0.18 m CMOS, in IEEE Int. Solid-State
Circuits Conf. Dig., Feb. 2010, pp. 482483.
[16] D.-H. Oh et al., A 2.8 Gb/s all-digital CDR with a 10 b monotonic
DCO, in IEEE Int. Solid-State Circuits Conf. Dig., Feb. 2007, pp.
222223.

LEE et al.: A 1 GHZ ADPLL WITH A 1.25 ps MINIMUM-RESOLUTION SUB-EXPONENT TDC IN 0.18 m CMOS

Seon-Kyoo Lee received the B.S. degree in electronic

and electrical engineering from Hanyang University,
Seoul, Korea, in 2006. He is currently pursuing the
Ph.D. degree in electronic and electrical engineering
from Pohang University of Science and Technology
(POSTECH), Korea.
His interests include high-speed links, PLL/DLL
circuits, data converters, and low-power analog
circuits.

Young-Hun Seo received the B.S. degree in electrical

engineering from Kyungpook National University in
1999 and the M.S. degree in electrical engineering
from Pohang University of Science and Technology
(POSTECH) in 2001. In 2001, he joined Samsung
Electronics Company Ltd., Hwasung, Korea, where
he has been involved in DRAM circuit design. Since
2007, he has been pursuing the Ph.D. degree in electrical engineering from POSTECH.
His research interests include low-voltage and lowpower memory circuits, high-speed chip-to-chip interface circuits, clock and data recovery and low-power CMOS analog circuits.

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Hong-June Park (M88) received the B.S. degree in

electronic engineering from Seoul National University, Seoul, Korea, in 1979, the M.S. degree from the
Korea Advanced Institute of Science and Technology,
Daejeon, in 1981, and the Ph.D. degree in electrical
engineering and computer sciences from the University of California, Berkeley, in 1989.
He was a CAD engineer with ETRI, Korea, from
1981 to 1984 and a Senior Engineer in the TCAD
Department of Intel from 1989 to 1991. In 1991,
he joined the Faculty of Electronic and Electrical
Engineering, Pohang University of Science and Technology (POSTECH),
Gyeongbuk, Korea, where he is currently Professor. His research interests
include high-speed CMOS interface circuit design, signal integrity, device and
interconnect modeling.
Prof. Park is a member of IEEK, IEEE, and IEICE.

Jae-Yoon Sim (M02) received the B.S., M.S., and

Ph.D. degrees in electronic and electrical engineering
from Pohang University of Science and Technology,
Korea, in 1993, 1995, and 1999, respectively.
From 1999 to 2005, he was with Samsung
Electronics, Korea, where he developed low-power
DRAMs as a Senior Engineer. From 2003 to 2005,
he was a post-doctoral student with the University of
Southern California, Los Angeles. In 2005, he joined
the Faculty of Electronic and Electrical Engineering,
Pohang University of Science and Technology,
Korea, where he is currently an Assistant Professor. His research interests
include PLL/DLL, high-speed serial/parallel links, memory circuits, and power
modules for microwave-excited plasma generation.
Prof. Sim was a co-recipient of the Takuo Sugano Award at the IEEE International Solid-State Circuits Conference (ISSCC). From 2007 to 2009, he
served on the technical program committees of the IEEE Symposium on VLSI
Circuits (SOVC) and IEEE Asian Solid-State Circuits Conference (ASSCC).
Since 2008, he has been a member of the ISSCC technical program committee.