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Magic Blue Smoke is a blog
dedicated to discussing the
challenges of low power ASIC
Design
Categories
Architecture
chip finishing
implementation
Infrastructure
Library Modelling
low power general
Power Format
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I Forgot to add the syntax of Modelling Isolation cells. Thanks Sampath for reminding me on this. Here is
one way to model ISOLATION cells
cell (isolation_cell) {
cell_leakage_power : 2.382 ;
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
}
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
}
pin(data_in) {
direction : input;
capacitance : 0.001867;
rise_capacitance : 0.001234;
fall_capacitance : 0.004567;
}
pin(isolation_enable) {
direction : input;
capacitance : 0.007890;
rise_capacitance : 0.001234;
fall_capacitance : 0.005678;
isolation_cell_enable_pin : true;
}
pin(clamped_data) {
direction : output;
max_capacitance : 0.09876;
function : (data_in+isolation_enable);
timing() {
related_pin : isolation_enable;
timing_sense : positive_unate;
.
}
.
}
Posted in Library Modelling | 1 Comment
I have worked in
the VLSI industry
for 14 years as a
digital IC designer. My recent
work has been focused on
low-power challenges
associated with multi-voltage/
multi-supply designs. The goal
of this blog is to open a free
exchange of ideas with
regards to low power. Please
participate!
- Godwin Maben
}
(4) Always on Buffer:
cell (always_on_buffer) {
always_on : true;
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
}
pg_pin (VDD_retain) {
voltage_name : VDD_retain;
pg_type : backup_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
}
.
}
(5) Switch Cell:
cell (header_switch) {
switch_cell_type : coarse_grain;
pg_pin(VDD) {
voltage_name : VDD;
pg_type : primary_power;
direction : input;
}
pg_pin(VDD_internal) {
voltage_name : VDD_internal;
pg_type : internal_power;
switch_function : sleepin;
pg_function : VDD;
direction : output;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type : primary_ground;
direction : input;
}
pin(sleepin) {
switch_pin : true;
always_on : true;
direction : input;
capacitance : 0.0046;
rise_capacitance : 0.0046;
fall_capacitance : 0.0046;
}
pin(sleepout) {
power_down_function : !VDD + VSS;
direction : output;
max_capacitance : 0.1694;
function : sleepin;
..
}
If the required attributes highlighted in the above .lib model is present, most of the tools will be able to
identify them as special cells and optimize them accordingly.
Posted in Library Modelling | 8 Comments
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