Karapetyan 2 Presentation

Low Power Design Methods:
Design Flows and Kits

Shushanik Karapetyan
1st year PhD Student
Synopsys Armenia Educational Department,
State Engineering University of Armenia
Moscow
March 23, 2011
Copyright 2011 Synopsys, Inc.
Outline
Low Power Design Flows
Library requirements for Low Power Design
Example of 90nm EDK
Conventional Design Flow

System and Software Architecture
Power Management should be

taken into account at the earliest
design stages
RTL Implementation
Logic simulation
Logic Synthesis
Almost every step of design flow

need to be modified for LPD
Timing Analysis
Formal Verification
Physical Synthesis
Signoff
Power-Aware Design Flow

System and Software Architecture
RTL Implementation
Logic simulation
Choose appropriate
power intent, design styles etc.
Implement power intent
in appropriate format
Power aware simulation
and analysis
Logic Synthesis
Timing Analysis
Formal Verification
Automate synthesis
of LPD techniques
Power-aware verification
needed to reveal power
Related bugs
Physical Synthesis
Signoff
Signoff tools must be voltageaware for silicon success

LPD Techniques Automation Levels

Clock Gating
EN
CG
Leakage
FF
Multi-threshold
Delay
Low-Vth Std-Vth High-Vth
Clk
Clock Gate
Automatically
No special treatment needed
OFF
Power gating
0.9V
0.9V
Automatically
0.9V
Multi Voltage
0.9V
0.7V
0.9V
Specification of power intent (UPF)
Unified Power Format (UPF): Necessity

Language
Specification of
power intent
Interoperable
Can be freely used
among EDA tools
(open standard)
Hardware
Description
Languages
(Verilog, VHDL, etc.)
Vendor Specific
Formats
UPF
Specifying Power Intent
0.9V
Periphery
Power Domain
0.9/OFF
iso
LS
LS
OFF
LS
0.7V/1.2V
C
0.9V
LS
Operation Scenario
(OFF, 0.9V, 0.7V)
(0.9V, 0.9V, 1.2V)
MV with power gating

Supply Network
MV with Power Gating Example
VDDA
0.9V
VDDB
VDD
0.9/OFF
RR
VDD
Control
VDDV
OFF
iso
LS
LS
VSS
B
VDDA
0.7V/1.2V
0.9V
LS
VDDB
LS
VSS
VDD
VSS
VSS
UPF: Power Domains
VDDA
UPF
A
0.9V
VDDB
VDD
VDD
0.9/OFF
RR
VDDV
OFF
Power
Domain
Power
State
0.9/OFF
0.7/1.2
0.9
LS
Control
B
VDDA
0.7V/1.2V
LS
VSS
C
0.9V VDD
LS
VDDB
iso
LS
LS
VSS
VSS
VSS
UPF: Supply Network
VDDA
UPF
A
0.9V
VDDB
VDD
VDD
0.9/OFF
RR
Supply
Net
Voltage
Level (V)
Power
Domain
VDD
0.9
VDDA
0.7
VDDB
1.2
VDDV
Virtual 0.9
VSS
Common
Ground
A/B/C
VDDV
OFF
LS
iso
LS
LS
VSS
Control
B
VDDA
0.7V/1.2V
LS
0.9V VDD
LS
VDDB
VSS
C
VSS
VSS
UPF: Periphery
VDDA
UPF
A
0.9V
VDDB
VDD
VDD
Level Shifters between A and B
0.9/OFF
RR
Required Periphery
VDDV
Level Shifters between B and C
OFF
Isolation between C and A

LS
Retention Cell inside A
iso
LS
LS
VSS
Control
B
VDDA
0.7V/1.2V
LS
VSS
C
0.9V VDD
LS
VDDB
Control Block inside A
VSS
VSS
UPF: State Scenario
VDDA
UPF
A
0.9V
VDDB
VDD
VDD
0.9/OFF
RR
VDDV
Scenario
0.9
0.7
0.9
Allowed
0.9
1.2
0.9
Allowed
OFF
0.7
0.9
Allowed
OFF
1.2
0.9
Not Allowed
OFF
LS
iso
LS
LS
VSS
Control
B
VDDA
0.7V/1.2V
LS
VDDB
LS
VSS
C
0.9V VDD
VSS
VSS
Design Flow Modification with UPF

Design Specification
RTL
Ex. Synopsys
Design Compiler
Initial UPF
Initial Power Intent

LPD Technique strategy
Implementation details
Logic Synthesis
Gate Level
Ex. Synopsys
IC Compiler
Initial UPF description is

modified during design
Gate Level
UPF
Supply net connections

Special cells
Physical Synthesis
Gate Level
PG Gate Level
Physical
UPF
Modifications to low-power
circuit structures
Design Compiler Visual UPF

Strategies Visualization
Supply port
PD boundary
Block PD primary
power net
Power Switch
ISO location
parentwith
backup power
defined
Retention register
LS strategy
defined in
UPF
Top PD primary
ground net
IC Compiler UPF Placement
Placement respects
voltage area
boundary
Special Level Shifter
and Isolation Cells
placement
Special cells
placed closer to
VA boundary
LS cells
ISO cells
Library Requirements for LPD
Special cells
Special versions of library
Characterization in additional corners
Additional views/files/attributes
90nm EDK: Digital Standard Cell Library

Digital Standard Cell Library (DSCL)
Aimed at optimizing the main characteristics of designed Ics
Contains 340 cells, cell list compiled based on the requirements for educational
designs
Typical combinational and sequential logic cells for different drive strengths
Typical combinational and sequential
Special cells for different styles LPD
Inverters/Buffers
Logic Gates
Flip-Flops
(regular+scan)
Isolation Cells
Level Shifters
Retention
Flip-Flops
Latches
Delay Lines
Physical
(Antenna diode)
Clock gating
Always-on
Buffers
Power Gating
Provides the support of IC design with different core voltages to minimize

dynamic and leakage power.
Special Cells for LPD: Level Shifter
1.2
LS
LS
LS
LS
LS
0.9
0.7
LS
Level Shifters
Level Shifter
VDDL
VDDL
VDDH
VDDH
VSS
VSS
Logic Symbol of Low to High Level Shifter
Logic Symbol of High to Low Level Shifter
Low to High Level Shifter Truth Table
High to Low Level Shifter Truth Table
D (0.8V)
Q (1.2V)
D (1.2V)
Q (0.8V)
Level Shifter Physical Structure

VDD
L
VDD
H
VDDH
VDDL
VS
S
VS
S
H
VDDL
VDDH
High-to-Low
Low-to-High
Level Shifter (High to Low) Physical

Design
VDDL
High
voltage
areas
VDDH
Low voltage
area
VDDL
Level Shifter (Low to High) Physical

Design
VDDH
Low voltage
area
VDDL
High
voltage
areas
VDDH
Special Cells for LPD: Isolation Cells

Power Gating
0.9
0.9
OFF/0.7
Isolation Cells
Isolation Cells
D
Q
ISO
ISO
Logic Symbol of Clamp 0

Isolation Cell (Logic AND)
Logic Symbol of Clamp 1

Isolation Cell (Logic OR)
Hold 0 Isolation Cell (Logic AND) Truth Table
ISO
Hold 1 Isolation Cell (Logic OR) Truth Table
Bypass
mode
Output clamped
ISO
Bypass
mode
Isolation Cells: Physical Design
Special Cells for LPD: Always-on Buffers

Power Gating
0.7 1.08
0.9
OFF/0.7
Always on cells
Always-on Buffer
VDDG
INP
VDD local
(on/off)
VSS
Logic Symbol of Always

on Non-Inverting Buffer
Always on
area
VDD_global
(always-on)
Always on Non-Inverting
Buffer Truth Table
IN
VDDG
VSS
VSS local
(on/off)
Special Cells for LPD: Always-on Isolation cells

Always-on
Isolation Cells
0.7
0.9
OFF/0.7
Always on Isolation Cells

VDD
VDDG
VDD VDDG
D
Q
ISO
ISO
VSS
VSS
Logic Symbol of Clamp 0 Isolation Cell

(Logic AND),Always On
Logic Symbol of Clamp 1 Isolation Cell

(Logic OR), Always On
Hold 0 Isolation Cell (Logic AND) Truth Table
ISO
Hold 1 Isolation Cell (Logic OR) Truth Table
Bypass
mode
Output clamped
ISO
Bypass
mode
Isolation Cell (always-on) Physical Design

Always on supply
Always on area
Special Cells for LPD: Enable level

shifters
Combination of Level
Shifter and ISO cell
Enable level
shifters
1.08
0.9
OFF/0.7
Level Shifters With Active Low Enable

VDDL
VDDH
VDDH
ENB
VDDL
ENB
LSUPEN
D
VSS
VSS
Symbol of High to Low Level Shifter

Active Low Enable, Clamp 1
Symbol of Low to High Level Shifter

Active Low Enable, Clamp 0
D(0.8V)
ENB
Q(1.2V)
D(1.2V)
ENB
Q(0.8V)
Bypass
mode
Output clamped
Bypass
mode
Enable Level Shifter (low-to-high)

Physical design
Low voltage
area
VDDH
VDDL
High
voltage
areas
VDDH
State Retention Registers

State Retention Registers
RR
RR
RR
CTR
1.08V/OFF
1.08V/OFF
0.7V
sleep
0.9V
Retention Register - preserve

status while the logic is turned off
Retention Register Physical design
Always-on Power pin
Always on area, with highVth
Power Gates
RR
RR
RR
CTR
1.08V/OFF
1.08V/OFF
0.7V
sleep
0.9V
Power Gates
Retention Register - preserve

status while the logic is turned off
Coarse Grain - Power Gates
(switch cells)
Header Cells
VDDG
VDDG
VDD
VDD
SLEEP
SLEEP
SLEEPOUT
Logic Symbol of Header Cell
Logic Symbol of Header Cell(with SLEEPOUT output )
Header Cell Truth Table
Header Cell (with SLEEPOUT output) Truth Table
SLEEP
VDDG
VDD
SLEEP
VDDG
VDD
SLEEPOUT
hi-z
hi-z
Header Cells Physical Design
a. Header Cell
b. Header Cell (with SLEEPOUT output)
Multi-Threshold Libraries
100%
FF
FF
80%
60%
40%
Critical
Path
FF
0%
FF
FF
20%
Low-Vth
Std-Vth
Leakage
Multi-Vth libraries
AL
BL
CL
Low Vth
AS
BS
CS
Std Vth
AH
BH
CH
High Vth
High-Vth
Delay
DSCL: Multi Threshold Versions of Cells

For implementation of Multi-Vth technique the
whole DSCL is available in 3 versions (1020
cells)
All cells with Low threshold voltage
All cells with Standard threshold voltage
All cells with High threshold voltage
Characterization
Characterization computes cell parameter (e.g. delay, output
current) depending on input variables: output load, input slew, etc.
Characterization is preformed for various combinations of operating
conditions: process, voltage, temperature (also called PVT corners).
slew
Input Slew
slew
slew
Iout
Cchar
0.7
0.7 0.5
0.7 0.5
0.2
0.5 0.2
0.1
0.2 0.1
0.1
Process: Fast
Temp:
125o
Voltage: 1.32v
Process: Slow
Temp:
-40o
.023 .047 .065 .078 .091 Voltage: 1.08v
output cap
.023 .047 .065 .078 .091 Process: Typical

Temp:
25o
output cap
.023 .047 .065 .078 .091
Voltage: 1.2v
output cap
DSCL: Characterization Corners
TTNT1p20v
SSHT1p08v
FFLT1p32v
Process
(NMOS proc.
PMOS proc.)
Typical - Typical
Slow - Slow
Fast - Fast
FFHT1p32v
Fast - Fast
Corner
Name
SSLT1p32v
SSLT1p08v
TTNT0p80v
SSHT0p70v
FFLT0p90v
Temperature (T)
Power Supply (V)
Notes
25
125
-40
1.2
1.08
1.32
125
1.32
Typical corner
Slow corner
Fast corner
High leakage
corner
Low temperature
corners
-40
Slow - Slow
1.32
-40
Slow - Slow
1.08
Low Voltage Operating Conditions
25
Typical - Typical
0.80
125
Slow - Slow
0.70
-40
Fast - Fast
0.90
FFHT0p90v
Fast - Fast
125
0.90
SSLT0p90v
SSLT0p70v
Slow - Slow
Slow - Slow
-40
-40
0.90
0.70
Typical corner
Slow corner
Fast corner
High leakage
corner
Low temperature
corners
DSCL: Additional Data

Power / ground (PG) pin
definitions are required for
all cells in a library
Defined as attributes in .lib

Allows accurate definition of
multiple power / ground pin
information
Benefits
Power domain driven

synthesis
Automatic power net
connections
PST-based optimization
Verification of PG netlist vs.
power domains
Power switch verification
pg_pin(VDD) {
std_cell_main_rail : true ;
voltage_name : VDD;
pg_type
: primary_power;
}
pg_pin(VSS) {
voltage_name : VSS;
pg_type
: primary_ground;
}
DSCL: Power Verilog Models

Power Verilog models
Separate verilog models with
power modeling
module AND2X1(IN1,IN2,Q);
output Q;
input IN1,IN2;
and (Q,IN2,IN1);
endmodule
module AND2X1 (IN1,IN2,Q,VDD,VSS);

output Q;
Modeling output
input IN1,IN2;
state dependence
inout VDD;
inout VSS;
on power
power_down iQ (Q, Qint, VDD, VSS);
and (Qint,IN1,IN2);
endmodule
primitive power_down (Q, Qint, vdd, vss);
output Q;
input Qint, vdd, vss;
table
0 1 0 : 0 ;
1 1 0 : 1 ;
? 0 0 : x ;
? 0 1 : x ;
? 1 1 : x ;
? x ? : x ;
? ? x : x ;
endtable
endprimitive
DSCL: Special Cells for Low Power

Techniques (1)
Power Gatings
VDDG
5 cells with different loads
Always on
VDDG
VDD
IN
AOn
SLEEP
10 cells: 3 inverters, 3 buffers and

4 DFFs
VSS
Retention cells
VDD
44 cells negedge/posedge, scan
RETN
VDDG
ISO
Isolation cells
D
ISO
CLK
QN
8 cells with different logic, load

VSS

Techniques (2)
Level shifters
VDDL
16 cells Low/High, High/Low, with

or without enable, with different
loads
VDDH
LSUP
D
Clock gatings:
11 cells with different loads, edges,
and control (post/pre)
VSS
SE
ENL
HVT Cells
EN
All logical cells are designed using

HVT, LVT
CLK
L
A
T
C
H
OBS
GCLK

Techniques (3)
Power Gates
(MTCMOS)
0.9V
0.9V 0.9V
0.9V
0.7V 0.9V
OFF
0.9V
0.9V 0.9V
OFF
0.9V
0.7V 0.9V
OFF
S 0.9V
R
0.7V 0.9V
Isolation
Cells
Level Shifters
Retention
Registers
Always On
Logic
Multiple Power
Domains
Single Voltage
Multiple Voltage
(MV)
Domains
Power Gating
(shut down)
Single Voltage
No State
Retention
MV Domains
Power Gating
No State
Retention
MV Domains
Power Gating
State Retention
+
+
Low Power Design of ChipTop Developed

with DSCL: DC view
Low Power Design of ChipTop Developed

with DSCL: ICC View
Conclusion
Low Power Design requires significant design flow modifications
UPF enables LPD flow automation
Low Power design techniques have their huge impact on libraries

SAED 90nm EDK DSCL includes all special cells needed for low
power design techniques
This 90nm EDK is currently in use in 235 universities of 37 countries
This 90nm EDK is used inside Synopsys for education of customers
Currently similar EDK is being developed for 32/28nm technology,
initial release is planned in June 2011

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Low Power Design Methods:

Design Flows and Kits

Copyright 2011 Synopsys, Inc.

Conventional Design Flow

Power Management should be

Almost every step of design flow

Copyright 2011 Synopsys, Inc.

Power-Aware Design Flow

Signoff tools must be voltageaware for silicon success

LPD Techniques Automation Levels

No special treatment needed

Specification of power intent (UPF)

Copyright 2011 Synopsys, Inc.

Unified Power Format (UPF): Necessity

Copyright 2011 Synopsys, Inc.

Specifying Power Intent

MV with power gating

MV with Power Gating Example

Copyright 2011 Synopsys, Inc.

UPF: Power Domains

Copyright 2011 Synopsys, Inc.

UPF: Supply Network

Copyright 2011 Synopsys, Inc.

Level Shifters between A and B

Level Shifters between B and C

Isolation between C and A

Retention Cell inside A

Control Block inside A

Copyright 2011 Synopsys, Inc.

UPF: State Scenario

Copyright 2011 Synopsys, Inc.

Design Flow Modification with UPF

Initial Power Intent

Initial UPF description is

Supply net connections

Copyright 2011 Synopsys, Inc.

Design Compiler Visual UPF

Copyright 2011 Synopsys, Inc.

IC Compiler UPF Placement

Copyright 2011 Synopsys, Inc.

Library Requirements for LPD

Copyright 2011 Synopsys, Inc.

90nm EDK: Digital Standard Cell Library

Special cells for different styles LPD

Provides the support of IC design with different core voltages to minimize

Special Cells for LPD: Level Shifter

Copyright 2011 Synopsys, Inc.

Logic Symbol of Low to High Level Shifter

Logic Symbol of High to Low Level Shifter

Low to High Level Shifter Truth Table

High to Low Level Shifter Truth Table

Copyright 2011 Synopsys, Inc.

Level Shifter Physical Structure

Level Shifter (High to Low) Physical

Copyright 2011 Synopsys, Inc.

Level Shifter (Low to High) Physical

Copyright 2011 Synopsys, Inc.

Special Cells for LPD: Isolation Cells

Copyright 2011 Synopsys, Inc.

Logic Symbol of Clamp 0

Logic Symbol of Clamp 1

Hold 0 Isolation Cell (Logic AND) Truth Table

Hold 1 Isolation Cell (Logic OR) Truth Table

Isolation Cells: Physical Design