Sie sind auf Seite 1von 10

Review: FPGA based point-to-point for wireless communication

Liban Barre Mohamed1 , Dr Siti Zarina Binti Mohd Muji2


1

Faculty electric and electronic department of communication engineering, UTHM Johor 86400 , he140025@siswa.uthm.edu.my.
2
Faculty electric and electronic department of computer engineering UTHM , Johor 86400 Malaysia

Abstract
This paper presents a compact implementation of advanced encryption standard using different devices of
FPGA technology. Earlier technologies like Bluetooth with secure communication using secure wireless
connection terminals on a field programmable gate array (FPGA) gives most efficient secure communication in
wireless networks. available for the development in this project. Father more we have different cyclones The
first one (A) is a Cyclone II based FPGA. And cyclone III based for FPGA. The second platform (B) is a
Cyclone IV GX starter kit from Altera. The third platform (C) is based on an Arria V GX FPGA, which contains
a lot of logic and arithmetic resources. It has shown better results in terms of throughput rate and power
consumption which are very important parameters in Bluetooth based wireless communication systems. In this
techniques cost and speed are the two main factors in communication for wireless techniques.
keywords: FPGA secured wireless communication

1.0 INTRODUCTION
A few research works shows FPGA based
embedded system have become a platform for the
implementation of cryptographic algorithms, which
needs large number of bit-level operations, and that
can be done efficiently on FPGA. [1]
FPGA has rich resources as prebuilt logic blocks
and
programmable
routing
resources.
By programming, one actually rerouting the
connectivity of all the available prebuilt logic
blocks, thus a FPGA can be used for different
functionality.[4]
With the development of CAD tools, now, one can
not only using HDL code, but also using graphic
interfacing or even C code to implement logic
function,over,a,FPGA.
FPGAs have been around since the 1980s and were
originally conceived to give all design teams the
ability
to
create
custom
logic.
FPGAs contain programmable logic components
called logic blocks, and a lot of reconfigurable
interconnects that allow the blocks to be wired
together.
In most FPGAs, the logic blocks also include
memory elements, which may be simple flip-flops
or more complete blocks of memory
1.1FPGA
FUNCTION
COMMUNICATION

perform a completely different function.


FPGA consists of thousands of universal building
blocks, known as configurable logic blocks,
connected using programmable interconnects.
Reconfiguration is able to change a function of
each CLB and connections among them, leading to
a
functionally
new
digital
circuit.
For implementing cryptography in hardware,
FPGAs provide the only major alternative to
custom and semicustom Application Specific
Integrated
Circuits.
Integrated circuits that must be designed all the
way from the behavioral description to the physical
layout are sent for an expensive and timeconsuming fabrication.

FOR

FPGA Field Programmable Gate Array is an


integrated circuit that can be bought off the shelf
and reconfigured by designers themselves.
With each reconfiguration, which takes only a
fraction of a second, an integrated circuit can

Fig 1: Overall system design

1.2 Differential encoder of GPGA


The ideal frequency for this clock is the exact
frequency of the incoming data.
The reference clock must be driven from an
external input and therefore the recovered clock

pg. 1

cannot be used and routed internally which might


have been preferable.
In order to solve this problem an external clock
conditioner from Texas Instruments, LMK03000C,
was used.
The clock conditioner contains a PLL and locks to
an incoming clock and outputs a stable and clean
clock signal.
After a lot of testing and debugging it was
determined that the best way to make the system
run was to start the clock conditioner with a clock
signal from an on-board oscillator and then switch
to the recovered clock from the transceiver.
In this way the transceiver is driven by a stable
clock that is matched with the incoming data and
actually originates form its own recovered clock
signal.
The programming of the clock conditioner was
done based on the specifications of the circuit
described in.
1.3 PROPOSED SYSTEM POINT TO POINT
PROPOSED SYSTEM The transmitter block
obtains its data which can be numbers, text or
images acquired using the RC10 CMOS
camera.AES algorithm is then used to securely
transmit the data using Bluetooth connectivity to
the receiver block. The file transfer utility, host
application is used to configure the FPGA with the
corresponding bitstream files for configuring the
transmitter, receiver, and AES execution. FPGA
processes the acquired data and operates as the base
station of the transferred data. The RC10
prototyping board has been used for testing and
evaluating the proposed system. Bluetooth
connection has been established using the LM058
serial to Bluetooth adapters on both transmitting
and receiving terminals.

1.4 RELATED WORK


Bluetooth establishes ad-hoc voice and data
connections and operates in the 2.4 GHz unlicensed
ISM band. Its specification is open and royaltyfree. The symbol rate is 1 Ms/s to exploit a
maximum available channel bandwidth of 1 MHz.
Fast frequency hopping is applied to combat
interference and fading. A shaped, binary FM
modulation is applied to minimize transceiver
complexity.
1.5 ON-FPGA COMMUNICATION
ARCHITECTURES
FPGA architectures provide a high density of prefabricated wires and programmable switches that
can be used to realize different communication
architectures. Note that the onFPGA
communication architectures discussed in this
section inherit only the logical characteristics of the
communication architectures in the previous
section. Research into modifi- cations to the
programmable interconnect fabric of FPGAs is out
of the scope of this survey.

2.0 Point-to-Point Interconnect


An early FPGA-based systolic array architecture,
proposed by Dick [22], provides an example of this
architecture with a structural and systematic
topology. Processing elements are connected in a
well defined structure with data being In , the
Discrete Fourier Transform is mapped to a systolic
array of processing elements.
The welldefined interconnection between the
processing elements enables effective parallel
computation and control. The design was
implemented with a Xilinx XC4010 FPGA running
at a clock frequency of 15.3 MHz. By using more
recent FPGA the clock frequency of the design
could be improved. In the systolic array design for
gene sequencing, running at a clock frequency of
202 MHz, was reported. The communication
between processing elements is achieved by
System Integrating Module with Predefined
Physical Links. Asynchronous FIFOs were
implemented as the interface between
programmable switch and processing element, such
that the communication architecture is more
adaptable to IP cores with different operation
frequency. The design was implemented with
Xilinx Virtex-II FPGA and the SIMPPL control
was able to run at 50 MHz..

Figure 2 proposed system block diagram

pg. 2

2.1 ADVANTAGES OF FPGA


include the ability to re-program in the field to fix
bugs, a shorter time to market and lower nonrecurring ngineering costs. Vendors can also take a
middle road by developing their hardware on
ordinary FPGAs, but manufacture their final
version so it can no longer be modified after the
design
has
been
completed.

2.3 FPGAs VS ASICs


Xilinx stated that several market and technology
dynamics are changing the ASIC/FPGA paradigm:
[4]

Integrated circuit costs are rising aggressively

ASIC complexity has lengthened development time .

R&D resources and headcount are decreasing

Revenue losses for slow time-to-market


are increasing

Financial constraints in a poor economy


are driving low-cost technologies

These trends make FPGAs a better


alternative than ASICs for a larger number
of higher-volume applications than they
have been historically used for, to which
the attributes.

wireless base stations. In this section, several practical applications are considered. Those under consideration include basic radio I/Q sample connectivity, advanced I/Q sample connectivity, basestation internal transport, and integrated I/Q and
internal transport networks. [10]

2.5 . Available FPGA-platforms


There were three different hardware platforms
available for the development in this project. The
first one (A) is a Cyclone III based FPGA and it
exists in two variants, one for transmitting and one
for receiving. The board has separate circuits for
DVI I/O and SDI video I/O via an optical interface.
This platform is relatively cheap, but also not very
adaptable. The second platform (B) is a Cyclone IV
GX starter kit from Altera.
The FPGA in this platform has embedded
transceivers with corresponding connectors on the
board as well as a number of general I/O pins. The
third platform (C) is based on an Arria V GX
FPGA, which contains a lot of logic and arithmetic
resources and some /O, including one HDMI
output. Photos of the three different platforms can
be seen in appendix C. Table 4.1 shows a selection
of specifications of the different platforms . [18]

Table 1. Comparison of the FPGA platforms

2.3.1 FPGAs VS CPLDs


The primary differences between CPLDs and
FPGAs
are
architectural.
A CPLD has a somewhat restrictive structure the
result of this is less flexibility, with the advantage
of more predictable timing delays and a higher
logic-to-interconnect
ratio.[25]
The FPGA architectures, on the other hand, are
dominated
by
interconnect.
This makes them far more flexible but also far
more
complex
to
design
for.
Another notable difference between CPLDs and
FPGAs is the presence in most FPGAs of higherlevel embedded functions and embedded memories,
as well as to have logic blocks implement decoders
or mathematical functions.[26]

2.4 FPGA Connectivity Architectures for


Base Stations.
FPGA technology is ideally suited to meet the wide
range of connectivity requirements associated with

From the table it is clear that the Arria V FPGA has


a lot more resources for both
logic and arithmetic operations compared to the
other two. Another interesting feature
in this project is the performance of the embedded
transceivers. The Cyclone IV GX
transceivers can operate at up to 2.5 Gbit/s while
the Arria V GX can reach 5.6 Gbit/s.
The FPGA on platform A has no embedded
transceivers and has to rely on other circuits
for high speed serial data transfer.
At the start of the project the possibility to
implement all the desired functions on the
Arria V GX platform was explored. One problem
that was discovered is that the single HDMI
connector can only be used as an output. This
means that some modifications and additional
hardware would have been needed. Another
difficulty with this platform was that the FPGA at
the time was a very new design with new features
that were hard to find documentation and support
for. Based on this and the fact that the other

pg. 3

platforms seemed to be good enough and also less


costly platform C was abandoned.

2.6 Video processing of the FPGA


The first was to output a test image generated in the
FPGA to a monitor from the board that would be
used to receive serial video data, called the receiver
side.
The test image generator was also designed using
generic values in order to easily test different
resolutions
and
refresh
rates.
[13]
To send data as serial SDI signals using the onboard circuit, the RGB color data had to be
converted to YCrCb data according to the circuits
input,specifications.
Since the conversion only applies to the color data
and takes a couple of clock cycles to perform, the
synchronization signals have to be delayed by the
same
amount
of
cycles.
On the receiver side the conversion back to RGB
needs
to
be
made.[15]
Except for the inverse conversion the FPGA design
on this side is very similar to the one on the
transmitter
side.
When the serial video transfer was verified the test
image generator could be replaced with an actual
input of video data from an ordinary personal
computer.[18]

the demodulator. Since the receiver was unable to


lock to the differential encoded data the
implementation of this solution was unsuccessful
and the differential encoding had to be
implemented on a separate platform.

2.7 Differential encoder of FPGA


The ideal frequency for this clock is the exact
frequency
of
the
incoming
data.
The reference clock must be driven from an
external input and therefore the recovered clock
cannot be used and routed internally which might
have
been
preferable.
In order to solve this problem an external clock
conditioner from Texas Instruments, LMK03000C,
was used. The clock conditioner contains a PLL
and locks to an incoming clock and outputs a stable
and clean clock signal. After a lot of testing and
debugging it was determined that the best way to
make the system run was to start the clock conditioner with a clock signal from an on-board
oscillator and then switch to the recovered clock
from
the
transceiver.
The programming of the clock conditioner was
done based on the specifications of the circuit
described in. As mentioned in section 4.3.4 this
component needs to be configured and this is done
in a similar way to the configuration of the clock
conditioner.

figure 2
FIG 4

2.7 Digital Implementation Of The Fpga

Fig 3 overview of the FPGA design for radio


processing on the received side.
data could be sent instead, which is required for the
recovery of the original signal in

The digital parts of the system have been


implemented
using
different
FPGA-based
platforms. The parts of the design that were
implemented in FPGAs are the video processing
and the differential encoder. The first subsection
below explains what FPGAs and hardware
description languages implies and may be skipped
by initiated readers.
After this the implementation of the different parts
of the design are explained.

pg. 4

3.0 FPGA Design


Description Languages.

And

Hardware

A Field-Programmable Gate Array (FPGA) is a


reconfigurable integrated circuit that usually
contains an array of logic blocks, routing
interconnects and I/O blocks. A logic block
consists of a number of logic cells, by configuring
these blocks and the routing between them,
different functions can be adopted. The principal
function of a logic cell can be described with
configurable lookup tables, a full adder and a Dtype flip-flop.
Figure 4.2 shows the basic structure of an FPGA
and a logic cell. In addition to these
fundamental components a modern FPGA may also
contain multipliers dedicated for
digital signal processing, embedded memory,
processors and other embedded components to
form a complete system on a chip.[15].
An FPGA with its main components

Fig 5: Basic description of an FPGA and a logic


cell.
The typical applications for FPGAs are prototyping
and smaller production series
where low latency and a high level of parallelism
are needed. Compared to micro controllers and
ordinary computers an FPGA offers a lot more
parallel computing power and higher power and
space efficiency. On the other hand an Application
Specific Integrated
Circuit (ASIC) offers even better performance in
these aspects, but comes with the drawbacks that it
has a very high initial cost to start manufacturing of
the circuits,
more expensive developing costs and is more
complex to test. According to Xilinx, the largest
FPGA manufacturer in the world, FPGAs are a
better choice than ASICs for an increasing number
of higher-volume applications. This statement is
based on the facts that FPGAs have higher
performance, reduced power consumption and
lower material costs than before at the same time as
ASICs are affected negatively by a number of

factors. These factors include rising initial


production costs, higher complexity and therefore
development time which leads to costs and
increasing revenue losses for time to market.[19] In
order to configure an FPGA a Hardware
Descriptive Language (HDL) must be used. The
two most common languages are VHDL and
Verilog where the major difference lies in the
syntax. These two languages are also endorsed as
standards at the Institute of Electrical and
Electronics Engineers (IEEE). Compared to
common computer programming languages the
HDLs are not executed as sequential programs but
are said to describe the hardware, and can do so for
both sequential and concurrent functions. The
concurrent functions are executed in parallel, while
this enables very effective solutions for a number
of problems it also introduces potential problems
such as race conditions.
A HDL designer often writes the code at the
registry transfer level (RTL).[13] This means that
the code describes the design as a flow of data
signals between registers and logic operations
applied to these signals. Since an FPGA does not
execute the HDL code as a regular processor that
processes instructions, the code is rather far from
how it is physically implemented in the FPGA. To
successfully configure the device based on a
design, synthesis tools are used. These tools often
come from the respective FPGA manufacturer and
analyzes the code, breaks it down to basic logicgate functions and then translates it into actual
connections and configurations of the circuit. Not
all HDL code is possible to synthesize though and
is used purely for simulations and test benches.
There are also tools that can carry out synthesis of
the HDL code targeting ASIC production.[15]
A state machine is often used in order to implement
more advanced sequential functions in VHDL. In
this project the state machines have been based on
Gaislers two process method. It is a method that
can be used for any single-clock design, some of its
most important goals are to increase the abstraction
level, improve readability and simplify debugging.
By using one sequential process that only performs
latching of the state vector and a combinatorial
process, where the outputs are functions of the
sequential output r and other signals, these goals
can be achieved. Figure 4.3 shows a generic twoprocess circuit.[16].

pg. 5

3.1 Types of FPGA IN CYCLONES

Altera Cyclone II

Altera Cyclone III


Altera Cyclone IV GX 395

Altera Arria V GX.

Cyclone III device family contains eight family


members ranging from 5K to 120K logic elements
(LEs) available in a wide range of low-cost
packages.

3.2.1 How do Cyclone III FPGAs compare


to Cyclone II FPGAs?

3.1.1 What is the Cyclone series?


Altera's Cyclone series FPGAs provide the benefits
of programmable logic at price points competitive
with ASICs and ASSPs. Built from the ground up
based on extensive input from hundreds of
customers, these low-cost devices provide highvolume, application-focused features such as
embedded memory, external memory interfaces,
and clock management circuitry.

Photos of FPGA platforms

Compared to the previous generation built on the


90-nm process, the 65-nm Cyclone III device
family delivers 1.7x higher density, more than 3.5x
the embedded memory, and 2x more multipliers,
while lowering the cost per LE by 20 percent.
Cyclone III FPGAs consume 50 percent less (core)
power than Cyclone II FPGAs. Cyclone III FPGAs
also offer low-cost configuration options with
support for industry-standard commodity parallel
flash devices. Cyclone III FPGAs also support
higher speed memory interfaces and offer higher
I/O and PLL flexibility than Cyclone II FPGAs.

C.1. Cyclone III based platforms

FIG 7 (B) The Cyclone III board used on the


receiver side.
FIG 6 (A) The Cyclone III board used on the
transmitter side.

is a Cyclone III based FPGA and it exists in two


variants, (A) one
for transmitting and (B) one for receiving

is a Cyclone III based FPGA and it exists in two


variants, (A) one
for transmitting and (B) one for receiving.

3.2.2Cyclone IV GX based platform

3.2 What is the Cyclone III device family?


The Cyclone III device family is a low power, high
functionality, low cost family of FPGAs designed
to support a wide range of cost-sensitive highvolume applications. With this third generation in
the Cyclone series, Altera continues to deliver the
lowest development and system costs. The low-cost

pg. 6

some I/O, including one HDMI output. Photos of


the three different platforms can be seen in
appendix C. Table 4.1 shows a selection of
specifications of the different platforms.
Arria V GX based platform.
3.5 Serial communication between FPGAs

FIG 9 The Cyclone IV GX board with the clock


conditioner and a power supply.
THis is a Cyclone IV GX starter kit from Altera.
The FPGA in this platform has embedded
transceivers with corresponding connectors
on the board as well as a number of general I/O
pins. The third platform
3.3 The Cyclone IV device family
fers the following features:
Low-cost, low-power FPGA fabric:
6K to 150K logic elements
Up to 6.3 Mb of embedded memory
Up to 360 18 18 multipliers for DSP processing
intensive applications
Protocol bridging applications for under 1.5 W
total power

The system that is used for establishing the serial


communication between the multiple FPGA
systems is UART. The Block diagram of UART is
stands for "Baud Rate Generator" which controls
the speed of the data communication in RS232
channel.
Both receiver and sender side must work in the
same band ratio otherwise data will be lost.
BRG control the received data store initially at
received FIFO and the transmit Data FIFO transfer
the data through the transmitter Module. [2]
Smart Antenna in FPGA resource sharing may be
applied
to
this
structure.
The design space for FPGA resource sharing of
multi beam time delay elements is composed of the
polynomial order of the interpolator, sensor output
sample
rate.
.[3]
Micro blaze Processor Local Bus Interface module
is used here for connecting and accessing UART
module to the Processor as shown in this figure.

3.4 Altera Arria V GX

Fig 10 Block diagram architecture of each FPGA


System.
3.6 INTERFACE BETWEEN FPGA AND CPU

FIG 8: Altera Arria V GX.

In the first part of this section the electrical


interface between CPU and FPGA is described
and the challenges for a safe data transmission are
identified. After that, the previous FPGA design
(henceforth called old design) is studied and
further flaws are demonstrated. Finally, the
resulting set of problems is evolved from the
previous findings.

This is based on an Arria V GX FPGA, which


contains a lot of logic and arithmetic resources and

pg. 7

4.0 CONCLUSION
This paper presents a compact implementation of
fpga wireless communication
using different
devices of FPGA technology. And we made Earlier
technologies
like Bluetooth with secure
communication using secure wireless. Compared to
earlier techniques this paper proposes more
efficient secure communication with wireless
cryptographic techniques. And this paper contains
the types of the fpga like The first one (A) is a
Cyclone III based FPGA.
The second platform (B) is a Cyclone IV GX
starter kit from Altera.
The third platform (C) is based on an Arria V GX
FPGA. main factors in communication for wireless
techniques. And also i desired video processing
functions have been implemented, as well as the
baseband components. Based on theoretical studies
D-BPSK was chosen as modulation technique.
ACKNOWLEDGEMENTS
First of all I want to thank ALAH, and who always
offered their help with everything from to proofreading of our texts. And I also want to thank MY
LUCUTERER Dr Siti Zarina Binti Mohd . for being me examiner. In addition we would like to
thank everyone who has given me feedback during
this assignment and especially some of my class
mate who helped me with everything from opening
also grateful for all the free books to read my assignment like LIBRARY of the UTHM, IEEE,
Finally, we would like to thank my family they
supported for every think and some of my friends
and families.

using FPGAs, 2012 IEEE Aerospace Conference,


March, 2012.
[4] Dhirendra Kumar Tripathi, S.Arulmozhi
Nangai, and R. Muthaiah, FPGA Implementation
of Scalable Bandwidth Single Carrier Frequency
Domain Multiple Access Transceiver for The
Fourth Generation Wireless Communication,
Journal of Theoretical and Applied Information
Technology, vol. 28, no. 2, pp.8894, June 2011.
[5] Xuezheng Chu, and John McAllister,
Software-Defined Sphere Decoding for FPGABased MIMO Detection, IEEE Transactions On
Signal Processing, vol. 60, no. 11, pp. 6017-6026,
November 2012.
[6] S. Neuendorffer and F. Martinez-Vallina,
Building Zynq_R accelerators
with Vivado_R high level synthesis, in FPGA,
2013, pp. 12.
[7] Harikrishna, K. & Rao, T.R, FPGA based FFT
Algorithm
Implementation
in
WiMAX
Communications System IEEE International
Conference on Wireless VITAE. pp: 1-6. 2011.
[8] L. Gopal, D. Wong S.T, N. Zawanah, Design
of an FPGA-Based OFDM Transceiver for DVB-T
Standard, Computer Science and Automation
Engineering (CSAE), 2011 IEEE International
Conference on, vol. 3, pp. 193197, June 2011.
[9]
Jun Yang, Yin Dong, Ga Zhao, Weiping
Zhang, The Design of OFDM base-band data
transmission system based on FPGA. IEEE
International Conference on AIMSEC. Pp. 743
746. August 2011.
[10] The Application of FPGAs for
Wireless Base-Station Connectivity
WP450 (v1.1) September 29, 2015

5.0 REFERENCES
[I] S. Sau , C. Pal and A Chakrabarti "Design and
Implementation of Real
Time Secured RS232 Link for Multiple FPGA
Communication, Proc. Of
International Conference on Communication,
Computing & Security
,20 1 I, ISBN - 978- 1-4503-0464- 1.
[2] Real time communication between multiple
FPGA systems in multitasking environment using
RTOS

[11] DS180, 7 Series FPGAs Overview (Xilinx data


sheet) Sep 29, 2015.
[12]
International Journal of Engineering
Research and Applications (IJERA) ISSN: 22489622 www.ijera.com Vol. 3, Issue 4, Jul-Aug 2013,
pp.2404-2407
2404 | P a g e.
Fpga Secured Wireless Communication Using
Aes.

Paul, R.; Saha, S.; Sau, S.; Chakrabarti, A.


Devices, Circuits and Systems (ICDCS), 2012
International Conference on Year: 2012.
[3] Porcello, J., Designing and Implementing
OFDM
Communications for Advanced
Multifunction VA V Payloads

pg. 8

[13] A Highly-Configurable FPGA-Based Platform for Wireless Network Research.


By Man Cheuk Ng
Submitted to the Department of Electrical Engineering and Computer Science on May 20, 2011, in
partial ful_llment of the requirements for the degree of
Doctor of Philosophy in Computer Science
[14] Communications Specialties, Inc, "HDTV
Standards and Practices for Digital
Broadcasting" Communications Specialties, Inc,
[Online]. Available: http:
//www.commspecial.jp/assets/eduGuides/HDTV%
20Standards/index.htm. [Accessed:
Jan. 17, 2014].
[15]
International Journal of Computer
Applications (0975 8887) Volume 63 No.15,
February 2013
Implementation of a Wireless Communication
System A Review
[16] J. Gaisler, "A structured VHDL design
method," Gaisler Research AB, [Online].
Available:
http://www.gaisler.com/doc/vhdl2proc.pdf.
[Accessed: Dec.
18, 2013].
[17] International Telecommunication Union,
"Recommendation ITU-R BT.601-7 Studio
encoding parameters of digital television for
standard 4:3 and widescreen
16:9
aspect
ratios,"
International
Telecommunication Union, Mars 2011.
[Online].
Available
http://www.itu.int/dms_pubrec/itu-r/rec/bt/R-RECBT.
601-7-201103-I!!PDF-E.pdf [Accesssed: Dec. 18,
2013].
[18] System design of an FPGA and analog based
point-to-point wireless link
Masters thesis in Electrical Engineering
ARON SVENSSON
JONATHAN FLOD
Department of Microtechnology and Nanoscience
Microwave Electronics Laboratory
Chalmers University of Technology Gothenburg,
Sweden [2014]
[19] Tim Erjavec, "Introducing the Xilinx Targeted
Design Platform: Fulfilling the Programmable
Imperative," Xilinx, 2009. [Online]. Available
http://www.xilinx.com/
support/documentation/white_papers/wp306.pdf
[Accessed: Dec. 17, 2013]

Sensor Systems Based on FPGAs and Their Applications:


A Survey
Antonio de la Piedra 1;*, An Braeken 2 and
Abdellah Touhafi 1
[21] Zynq-7000 Extensible Processing Platform
Block Diagram and Product Features. Xilinx.
Available
online:
http://www.xilinx.com/products/silicondevices/soc/zynq-7000/index.htm
(accessed on 4 September 2012).
[22] Xilinx 7 Series Overview; Datasheet DS180;
Xilinx. Available online:
http://www.xilinx.com/support/documentation/data
sheets/ds180 7Series Overview.pdf (accessed
on 4 September 2012).
[23] SmartFusion Intelligent Mixed Signal FPGAs;
Actel. Available online:
http://www.actel.com/documents/SmartFusion
DS.pdf (accessed on 4 September 2012).
[24] M. J. Canet, J. Valls, V. Almenar, J. MarinRoig, FPGA implementation of an OFDM-based
WLAN
receiver,
Microprocessors
and
Microsystems, vol. 36, issue 3, pp. 232244, May
2012.
[25] International Journal of Innovative Research
in Computer
and Communication Engineering
(An ISO 3297: 2007 Certified Organization)
Vol. 2, Issue 4, April 2014
Copyright to IJIRCCE www.ijircce.com 3989
FPGA Implementation of Optimized Decimation
Filter
for Wireless Communication Receivers
[26] Design and FPGA implementation of a wireless
hyperchaotic communication system for
secure real-time image transmission
Sadoudi et al. EURASIP Journal on Image and
Video Processing 2013, 2013
[27] Sadoudi et al. EURASIP Journal on Image
and Video Processing 2013, 2013:43
Design and FPGA implementation of a wireless
hyperchaotic communication system for
secure real-time image transmission.
[28] "Modulation," in Wikipedia. [Online]. Available: http://en.wikipedia.org/wiki/
Modulation. [Accessed: Dec. 16, 2013].
[29] "Johnson-Nyquist noise," in Wikipedia.
[Online]. Available: http://en.wikipedia.

[20] Review

pg. 9

org/wiki/Johnson%E2%80%93Nyquist_noise.
[Accessed: Dec. 14, 2013].
[29] Proc. of1nt. Con/, on Advances in Recent
Technologies in Communication and Computing
2011
DESIGN AND FPGA IMPLEMENTA TlON OF
IMPROVED LIFTING SCHEME BASED DWT
FOR OFDM
SYSTEMS
Deepthi H S 1, Sumita Shankar Manure2, Cyril
Prasanna Raj p3, Sari a S Bhusare4 , U L Naik5.
[30] Design of an FPGA-Based OFDM-STBC
Transceiver for WiMAX 802.16e Standard.
2014 2ND INTERNATIONAL CONFERENCE ON
INFORMATION AND COMMUNICATION
TECHNOLOGY

pg. 10