FACULTY OF ELECTRICAL AND ELECTRONIC ENGINEERING

UNIVERSITI TUN HUSSEIN ONN MALAYSIA

PROGRAMMING ELECTRONICS
MEE 10501 MASTERS LABORATORY 1
INTRODUCTION TO QUARTUS II
Lab1 report
Table of Content
Answer of Questions ................................................................................................. 1
Design ........................................................................................................................ 2
Results ........................................................................Error! Bookmark not defined.
Result Analysis ........................................................................................................... 4
Conclusions................................................................................................................ 5

1. Answers
1. The device that is used in this lab was a field-programmable gate array (FPGA) which is
an integrated circuit designed to be configured by a customer or a designer after manufacturing.

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2.

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3. If the Entity given name is different from projects name there will be errors and it will not
compile therefore, we should make Entity name same with projects name
4. The way to see the logic circuit as our result in this experiment is shown below
a. First click tool menu
b. Select Net list viewer

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c. Then choose RTL viewer

d. Finally it can be seen easily the logic circuit
5. Timing simulation a Vector Waveform File In that file, you can indicate the I/O pin(s) and
after simulation you can see the waveform from these I/O pin(s) Functional Simulation simply
tests the logic "functional" operation of the circuit. There is no consideration for delay through
the internal logic or the routing delay paths associated with where the placer and the router
interconnect things. It simply allows you to see that what you think you are coding provides the
results you are intending. With Timing Simulation, the delay associated with the logic elements
and the interconnect routing are taken into consideration (based on the speed grade of the chip
selected).

Quartus II timing analyzer provide method of analyzing, debugging and validating the
performance and operation of the design. However, the procedure is to do time simulation is
shown below.

a. Click New design file

b.

Then choose University program vwf.

c. Click node finder

d. Then click Edit Menu
e. Set 40ns to n-time and Grid 10 ns
f. Select list
g. Copy the node found to select node
h. Click ok.
i.

finally click time simulation

7. SW0 connect to Pin, AB28 SW1 connect Pin AC28 and LEDG0 connected to Pin E21
8. Because after entering the desired pin numbers for all signals in the pin Planner, then it will be
compiled again to check and test circuit operation at the developing board.
9. Yes, the procedure of this lab sheet is using the right flow from create new project until test the
circuit on board.
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2.0 design
2.1 Light controller and half adder design;
Source code of the light controller
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Light IS
PORT (x1,x2:IN STD_LOGIC;
f:OUT STD_LOGIC);
END Light;
ARCHITECTURE LogicFunction OF Light IS
BEGIN
f<=(x1 AND NOT x2) OR (NOT x1 AND x2);
END LogicFunction
Truth table of the light controller

Table 1 Truth table for the light controller

2.2 Design of the half adder

With the help of half adder, we can design circuits that are capable of performing simple addition
with the help of logic gates.
let us first take a look at the addition of single bits.
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 10
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These are the least possible single-bit combinations. But the result for 1+1 is 10. Though this
problem can be solved with the help of an EXOR Gate, if you do care about the output, the sum
result must be re-written as a 2-bit output.
From the equation it is clear that this 1-bit adder can be easily implemented with the help of
EXOR Gate for the output SUM and an AND Gate for the carry. Take a look at the
implementation below.
2.3 Half adder source code
Library ieee;
Use ieee.std_logic_1164.all;
entity halfadder is
Port ( in1, in2: in std_logic;
sum, carry: out std_logic);
end halfadder;

Architecture rtl of halfadder is

begin
Sum <= in1 xor in2;
Carry <= in1 and in2;
End rtl;

Table 2 Truth table for the half adder

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2.4 Source code of the full adder

Library ieee;
Use ieee.std_logic_1164.all;
entity fulladder is
Port ( a, b, cin: in std_logic;
sum, carry: out std_logic);
end fulladder;
Architecture rtl of fulladder is
Signal n_sum,n_carry1,carry2:std_logic;
component halfadder is
port( in1, in2: in std_logic; sum, carry: out std_logic);
end component;

3.0 Result

begin

3.1 Result of the full adder circuit

U1 : halfadder port map(in1=>a, in2=>b, sum=>n_sum, carry=>n_carry1);
U2 : halfadder port map(in1=>n_sum, in2=>cin, sum=>sum, carry=>n_carry2);
Carry <= n_carry2 or n_carry1;
End rtl;

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Table 3 Truth table of the full adder

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2.5 SOURCE CODE OF RIPPLE CARE

Library ieee;
Use ieee.std_logic_1164.all;
entity ripple_carry is
port(A,B:in std_logic_vector(3 downto 0);
sum:out std_logic_vector(3 downto 0);
cout:out std_logic);
end ripple_carry;
architecture rtl of ripple_carry is
signal c:std_logic_vector(3 downto 1);
component fulladder is
port(a,b,cin:in std_logic;
sum,carry:out std_logic);
end component;
begin
u1:fulladder port map(a=>A(0),b=>B(0),sum=>sum(0),cin=>'0',carry=>c(1));
u2:fulladder port map(a=>A(1),b=>B(1),sum=>sum(1),cin=>c(1),carry=>c(2));
u3:fulladder port map(a=>A(2),b=>B(2),sum=>sum(2),cin=>c(2),carry=>c(3));
u4:fulladder port map(a=>A(3),b=>B(3),sum=>sum(3),cin=>c(3),carry=>cout);
end rtl;

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3.0 Result
3.1 Result of the activity one or Light controller

Figure 2 light controller RTL

Figure 3 light controller functional parameters

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3.2 Result two half adder result simulation

Figure 4light controller functional simulation

Figure 5 half adder RTL

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3.3 Result of the full adder

Result of the full adder circuit; This is our result so we add TWO circuits of halfadder then we
get one fulladder,
The full-adder circuit adds three one-bit binary numbers (a,b,Cin) and outputs two one-bit binary
numbers, a sum (S) and a carry (C). The full-adder is usually a component in a cascade of
adders. The carry input for the full-adder circuit is from the carry output from the circuit
"above" itself in the cascade. The carry output from the full adder is fed to another full adder
"below" itself in the cascade.

Figure 6 schematic diagram of the fulladder

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Figure 7 logic gate diagram of the fulladder circuit

3.4 Result of the ripple carry adder

Result of the ripple carry adder circuit; It is possible to create a logical circuit using multiple
full adders to add N-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous
adder. This kind of adder is called a ripple-carry adder, since each carry bit "ripples" to the next

Figure 7 schematic diagram of the ripple carry adder

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Figure 8 logic circuit of the ripple carry adder

3.5 Functional simulation of the ripple carries

Discussion and Analysis

Figure 9 functional simulation diagram for ripple carry adder

3.6 Timing simulation of the ripple carries

Figure 10 Timing simulation diagram for ripple carry adder

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4.0 Result analysis

In light controller, as the results of the truth table of the light controller shows, the two input
components x1 and x2 are representing two switches and the output F is representing a LED, so
if the either of the two inputs are on (ones), the lamp will be switched on, but if the both the two
inputs are off (zero), the LED will be switched off. As the truth table and source design of the
half adder shows, half adder is a circuit that contains two logic gates, AND gate and XOR gate
which whose results are carry and sum respectively. The half adder circuit is an incomplete
circuit because it contains only half function of the full adder, therefore it doesnt have the ability
to add more than two numbers and thats why it is called half adder. Whats more, after the
simulation results, the functional simulations and timing simulation of the light controller and
half adder circuits is made, and followed by pin assignment also followed by one step more of
compiling the circuit inside FPGA, that means testing whether the programming is done
correctly or not, which depends on how you assigned the corresponding pins of the computer and
programming device, in this lab it is FPGA. From the above full adder truth-table, the full adder
logic can be implemented. We can see that the output is an EXOR between the input A and the halfadder SUM output with B and CIN inputs. We must also note that the COUT will only be true if any of the
two inputs out of the three are HIGH. However, it can be can implemented a full adder circuit with the
help of two half adder circuits as shown below. The first will half adder will be used to add A and B to
produce a partial Sum. The second half adder logic can be used to add CIN to the Sum produced by the
first half adder to get the final S output. If any of the half adder logic produces a carry, there will be an
output carry. Thus, COUT will be an OR function of the half-adder Carry outputs. In addition, RippleCarry adder created and constructed by using full adder which connected in cascade form with carry
out-put from each full adder connected to the carry input of the next full adder in the chain. Figure
Ripple shows the interconnection of four full adder circuits to provide 4-bit Ripple-carry adder.

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5.0 Conclusions
In this lab report it has made two different activities the light controller working same like switch
and half adder which is adding two numbers then producing two different results the sum and
carry. Both of contains basic logic gates. In the case, of the light controller, the negative and
positive values of the two inputs x1 and x2 are ANDed two times, resulting f0 and f1 , then
ORed to produces F2 final output which representing the LED. Furthermore, to that its also
designed full adder and ripple carry circuits, that is based on the principal of the half adder
circuit. In case of the full adder it is designed two half adders connected to gather to form full
adder circuit that have the ability to adder more than the half adder logic gate, while the ripple
carry consists of four adders and two output gates.

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6.0 References
1. Monmasson, Eric, and Marcian N. Cirstea. "FPGA design methodology for industrial control
systemsA review." Industrial Electronics, IEEE Transactions on 54.4 (2007): 1824-1842.
2. Klingman, Ed. "FPGA programming step by step." Embedded Systems Programming 17.4
(2004): 29-37.
3. Andrews, David, Douglas Niehaus, and Peter Ashenden. "Programming models for hybrid
CPU/FPGA chips." Computer 37.1 (2004): 118-120.
4. Pellerin, David, and Scott Thibault. Practical fpga programming in c. Prentice Hall Press, 2005.
5. Thoidis, I. M., et al. "The circuit design of multiple-valued logic voltage-mode adders." Circuits
and Systems, 2001. ISCAS 2001. The 2001 IEEE International Symposium on. Vol. 4. IEEE,
2001.
6. Fayed, Ayman, and Magdy Bayoumi. "A low power 10-transistor full adder cell for embedded
architectures." Circuits and Systems, 2001. ISCAS 2001. The 2001 IEEE International
Symposium on. Vol. 4. IEEE, 2001.

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