Presenting

Intel PhD Fellowship Program

Key Contact

Sumeet Verma
Head - Higher Education and Entrepreneurship,
Intel South Asia
Email: sumeet.verma@intel.com

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Intel Higher Education

in India

The Intel PhD Fellowship

Program in India

A dynamic innovative economy needs a robust education system that encourages graduates to pursue technical degrees and

The Intel PhD Fellowship Program awards fellowships to exceptional PhD candidates pursuing cutting-edge research in focus areas

entrepreneurial paths. Recognizing this need, Intel Higher Education in India strives to nurture innovators through multiple

identied by Intel Technology India Pvt. Ltd. This is a prestigious and highly competitive program with a limited number of

platforms. We recognize that academia plays a pivotal role in nurturing high-quality talent and skills and promoting research and

fellowships awarded annually to Indian students to pursue PhD in reputed technology and research institutions in India.

innovation. The Intel Higher Education Program in India collaborates between Intel and leading engineering and research
institutions, universities and the government to work towards the advancement of university curricula, research engagements,
faculty developments and innovation. So far, Intels Higher Education program has reached over 2,35,000 students and 4,500

Recipients of the fellowship will work with their mentor to develop a deep understanding
of the technological issues facing the industry and stay at the forefront of solving the
most complex technological problems that lie ahead

faculty members across more than 750 institutions.

Intel Higher Education India

Highlights of
the Program

Curriculum
Development

Research
Programs

Recipients of the fellowship may be provided Internship opportunities at Intel

Technology India Pvt. Ltd.
Selected PhD candidates will be awarded a fellowship of up to Rs. 6,00,000/PA including
travel grant and contingency grant for a period of 4 years

Intel PhD Fellowship Program

Workforce
Development

Innovation and
Entrepreneurship

Stipend

Internship

Academic Research and

Mentoring

Grants

PhD Degree

Knowledge

Networking

landscape of architecture choice. However, architects today lack the ability to fully evaluate the
performance, power, complexity and cost tradeos involved. The choice between big or small general
purpose cores, ISA extensions, GPU ooad, FPGA ooad, new dedicated hardware IP integration, various
caching and memory technologies and on/o die interconnects for designs are usually made based on
time to market pressures, readily available IPs, product costs and the like. There is a critical need for the
capability to quickly pick a balance between these varied architecture options that best t the bill for the
target usage models.
The research challenges include:
The in-depth workload analysis with the end goal of building an architecture-independent
abstraction of the target workload domain
A framework that can use the this abstraction to model performance, power on all the applicable

Research Area

architecture options while making the right tradeos in modeling accuracy vs. modeling exibility
Extending the workload abstraction to include multiple dierent domains where there is a need for
one architecture to target multiple domains

Graphics
With rapid advancements in tablet, handheld and wearable, several new and disruptive usage models
leveraging Visual Computing have emerged. The usage models are posing fresh challenges in the area of

Focus Areas

visual computing both from a power as well as compute perspective. With the advent of retina class of
devices, there is an increasing ask towards higher pixel densities in displays. These displays consume a
signicantly high amount of power (next only to RF in a smartphone) in an increasingly power constrained

Parallel Computing

envelope. On the media aspect, smartphones and tablets have long surpassed the requirement of age-

Parallel Computing used to be the preserve of a small community interested in High Performance

old camera/videocam technologies. There is a widespread usage of video content leading to aggressive

Computing (HPC). But over the last few years, several important changes have taken place. One, the

ask on computing in power constrained handheld devices. With the advent of better visual eects in

increasing problems with power consumption have ended the era of ever-increasing clock frequency

gaming and other visual applications, there is an increased ask on 3D graphics as well. We are fast

and brought in the age of ever-increasing number of processor cores on a chip. Two, the low power of

witnessing erstwhile desktop-class performance requirements showing up in handheld devices. These

multi-core chips has enabled their use in all devices including smartphones. Three, the accelerated drop

asks have outpaced Moores law leading to increased eort towards increasing architectural eciency.

in semiconductor costs has made the democratization of HPC possible. Finally, data movement is

Technologies such as video decode/encode, video analytics, image enhancement and 3D rendering are

getting increasingly more expensive than computing: the so-called memory wall.
The research challenges in parallel computing include:
Designing suitable architectures for various application domains
Designing new algorithms that address the memory-wall issue and exploit the

being implemented in dedicated hardware (moving away from general purpose compute hardware).
While new visual quality algorithms are being implemented to cater to the demand of increased compute,
aggressive power-saving techniques such as ne grained power gating and near threshold voltage
technologies are being implemented to address the power challenge.

evolving architectures
Designing new programming paradigms and tools to enhance programmer productivity without
signicantly compromising on performance and low power

Sensing
The research focus will cover a broad range of sensing and sense-making technologies for cyber-physical
systems such as Internet of Things (IoT) and wearables. It will cover novel transducers, sensor-front-end

Architecture
The last decade has seen a resurgence of processors incorporating architectures very dierent from the
aggressive out-of-order and superscalar designs. New usages, domain specic frameworks and
workloads are exploding across datacenters and devices alike. Web 2.0, Hadoop, Media Transcode,
Machine Learning, Speech Recognition are few examples. This coupled with challenges in improving
single thread performance has lead system architects to look at dedicated hardware acceleration, FPGA

circuits, compression, feature-extraction, fusion, and classication algorithms of sensed data on devices
ranging from power-constrained wearables to cloud server farms. It will also cover power-ecient
hardware-software co-design for these algorithms. This topic can also include constrained optimization
algorithms for duty-cycling sensing devices and intelligent communication, and energy harvesting
protocols to extend battery life. It will also include dataset creation and dissemination of sensed data.
Finally, the topic can also include security and privacy issues related to the use of sensed data.

ooad and even programmable accelerators targeting specic domains. The dramatic increase in
programmability and the raw compute power of GPUs has resulted in yet another viable alternative for
some usage models. Orthogonally, technology advances in areas like memory (e.g. Phase Change NVM),
die stacking (e.g. through silicon Vias) and high BW interconnects (e.g. Optical) further expand the

Validation
Smartphone, tablet, client and server chip solutions with customizations are exploding the validation

coverage space. Aggressive RTL tape-in to product launch timelines require validation to cover the

Creating a continuous sensing and learning platform architectures

relevant validation space in signicantly shorter time and lesser cost. Pre-silicon coverage space is

Designing new methods of meshing multiple sensory data-streams into a more comprehensive

impacted by simulation, emulation speed and usage model understanding resulting in increased number
of silicon and platform collateral bugs. Key challenges for validation include dierent architectures, IP
integration and design for debug and validation silicon hooks impacting reuse of validation collaterals.

awareness of the context

Design of algorithms that leverage the device, device mesh and the cloud to create seamless,
transparent, and natural human-device interaction methods

Validation collaterals include test, debug, platform, scope and logic analyzer which are expensive and not
reusable as
architecture changes.

Communications
Wireless communication is an important part of mobile computing vision of Intel. Every device, starting

The research areas include:

from phones to energy meters are going to be connected through wireless networks. This means

Adaptive (based on test coverage) functional test generation ows for

exponential growth in data bandwidth requirements, which necessitates development of new wireless

pre-silicon/post-silicon environment
Pushing IP/integration bugs (RTL/Firmware/SW) upstream by seamless simulation to
FPGA/Emulation ows
Framework for use case validation from smartphone to server segments
Self-test ows for electrical parameters in the chip for reducing validation cost
Clock/architecture agnostic logic/electrical DFx (Debug visibility) IP

technologies to support 100 fold increase in data rates. To cater to these future needs, we are looking
for research in the following areas:
WIFI and cellular integrated networks
Heterogeneous networks
Mm wave technologies
Machine to machine communication and Internet of Things
Peer-to-peer networks

Power Management
Power management as a primary pillar in the architecture of all devices big and small has seen increasing
prominence over the last decade or so. We have already entered the era of dark silicon wherein multicore scaling is power limited and large areas of the chip have to be kept powered down dynamically and
eciently to maximize performance and battery life. Modern power management straddles several
abstraction layers in computer design across circuit and microarchitecture-level aspects, multi-core and
package-level power states, and operating system interfaces and application level APIs. New technology
trends such as 3D stacked memories, arrays of special purpose accelerators, sensor networks, fully
integrated ne-grained voltage regulators, and pervasive virtualization are creating hard challenges and
exciting research opportunities for power management experts to grapple with.

Perceptual Computing
Perceptual computing will fundamentally change how people interact with their PCs, tablets, phones and
wearable devices. Advances in this eld will result in intuitive, natural and engaging methods of
interacting with smart devices around us in our daily life. The aim of research in perceptual computing is
to add and build on sensory capabilities such as touch, gesture, visual understanding, motion and other
sensors to our devices and environment for creating new experiences and new user interfaces.
Important areas of focus are speech, hand and nger tracking, facial tracking/analysis, social signal
analysis and perceptual machine learning. Speech is a common and natural way to add interactivity to an
application or device in our environment. The complexities of languages, accents, ambient conditions,
etc. make this a ripe area for exploration and development of adaptive, context-sensitive algorithms for
speech recognition and speech-driven applications. Hand and nger tracking is fundamental to many
natural interaction modes. Ability to build a complex vocabulary of gestures, poses and intents is critical
to building a natural interface. Face detection and analysis is extremely useful in both interactive social
applications as well as for gaming and other communication applications. And, of course, combining the
sensory data to understand social signals in interactions; and using machine learning to continuously
improve the context awareness.
The research challenges in perceptual computing include:

Application Process

Select universities/institutes will be invited to submit a limited number of student

candidates for consideration

Eligibility

Intel will not accept direct applications from students

Nationality: Only Indian Nationals are eligible to submit applications to participate in the

Students must rst be nominated by the corresponding university/institute, the application

should be routed through the research guide

Intel PhD Fellowship Program

1st year PhD Students and Students in the beginning of 2nd year PhD can apply

Must be currently enrolled in a PhD program at selected universities/institutes with research problem
based on topics that are relevant to Intel (See Focus Areas in page 4-7)

Must retain full-time student status during the academic year(s) for which the fellowship is awarded

Must have successfully completed all qualifying examinations

Once selected, students may not defer the fellowship

Intel employees and their families are not eligible

The nomination should be accompanied by a brief research proposal pertaining to the

Doctoral thesis

A Curriculum Vitae (CV) including GPA (Bachelors, Masters, and PhD) to be submitted by the
candidate

Students should submit up to 3 letters of recommendation of which one must be from

the students research guide

Students should submit a cover letter to the Selection committee constituted by Intel
Technology India Pvt. Ltd. with the following information:
o Is the student willing to do an internship with Intel Technology India Pvt. Ltd. if an internship
is oered?
o Does the student have internship plans for next summer?
o Is the students advisor currently funded by Intel technology India Pvt. Ltd., or has he/she
been funded in the past?
o Expected date of graduation?
o Is the student working on one of the Focus Areas (see above)? Which one?
o Is the student in the general candidate pool or underrepresented?

Criteria of Selection

Nominations from universities will be screened to ensure that the overall eligibility criteria
are met

Selection is based on candidates overall potential for research excellence, degree to which
their technical interests align with the "Focus Areas", their progress till date, and
recommendations from their advisor and Head of Department

Selection is based on the student's academic excellence and ability to clearly articulate their
research interests

Payment of the fellowship award will be made directly to the university/institute

Key elements for selection: Candidates credentials, institutes credentials for the selected eld
of study, alignment with the Focus Area and academic research guides credentials

Aliations and Government Partnerships

Frequently Asked Questions (FAQs)

Intel will be keen to partner with any existing Government PhD/Doctoral Studies fellowship programs for further

1. What is Intel PhD Fellowship Program?

enrichment and expansion of the program.

Terms and Conditions

The Intel PhD Fellowship Program awards fellowships to exceptional PhD candidates pursuing cutting-edge
innovation in hi-technology elds. Intel Corporation has been oering this program in the US for more than two
decades and this prestigious program has become highly competitive with a limited number of fellowships awarded
annually. We at Intel Technology India Pvt. Ltd. (Intel), are pleased to bring this program to India to encourage a high

The student should have a rst class education credentials right from Higher Secondary and Secondary Schools

impact transformative research collaboration between academia and industry, to provide selected students an

1st year PhD Students and Students in the beginning of 2nd year PhD can apply

opportunity to work with the best minds in the selected areas of research.

Students have to be registered as full-time students in the institute where the PhD registration is sought

Intel Technology India pvt. Ltd. reserves the right not to grant any PhD Fellowship

Intel Technology India pvt. Ltd. reserves the right to have a discussion with the student, if deemed necessary

Intel PhD Fellowship Program is open for only the Focus Areas mentioned in page 4-7

directly with their mentors to develop a deeper understanding of relevant technical issues and contribute to solve the

The institute will intimate Intel on the date of ling of any patent related to any invention by the fellow recipient

complex technical problems facing the industry. Award recipients may be considered for internships and hiring

under this program

opportunities within the company.

2. What are the unique elements of this Program?

Each award recipient is assigned to an Intel technical mentor who is a respected leader in a said eld. Students work

The institute is free to publish any work developed by the fellow recipient, provided it sends Intel a written

Through the Research grant, the award recipients work closely with their respective mentors, meet and network with

intimation along with the work that will be published 30 days prior to such publication

top industry researchers at selected Intel campuses during the academic year immediately following the award. The

The Intel PhD fellowship can be taken in addition to the PhD scholarship that the student receives from other

goal of these sessions are to provide each student with an opportunity to showcase their research, identify potential

sources provided there are no violation of rules

industry-academic collaborations, and explore internship opportunities.

Intel will get the rst opportunity to consider the candidate for any employment opportunity, if any, within Intel

3. Can Students directly apply to Intel for PhD Fellowship Program?

No. Students cannot directly apply for the Intel PhD Fellowship Program. Intel will be inviting proposals from faculty
members of select technology institutions and applications are to be routed through the research guides.

4. When is the last date for submission of application forms? When will the results be declared?
Please check with an Intel Representative for detailed information on form submission and results declaration.

5. Can a Professor / Research guide apply for the Intel PhD Fellowship before identifying a student
for PhD?
Yes. A Professor / Research Guide from an institution selected by Intel for the Intel PhD Fellowship program can
submit a proposal without a student being identied. However, the research guide has to provide the details of the
student at a later date to Intel. The review committee will once again review the proposal, based on the details of the
students educational qualications and other credentials as per the terms and conditions of the Intel PhD fellowship
program, and make a decision on awarding the fellowship.

6. Are award recipients guaranteed a job in Intel?

No, the Intel PhD fellowship program will not guarantee a job at Intel to the award recipients. However, Intel may give
hiring preference to the award recipients if they chose to pursue their career with Intel.

7. Will Intel do a performance review of the Fellowship? How frequently?

Each award recipient shall be associated with a mentor from Intel who is an established researcher in a given domain.
The student shall be in touch with the Intel mentor on a regular basis during the tenure of the Fellowship.
Additionally, the candidate has to submit an annual progress report to the PhD Fellowship Committee for review.

Notes
8. Will Intel mentors be co-authors of research papers arising from the research through
Fellowships?
Yes, Intel Mentors can be co-authors to research papers at their discretion. As the focus of the Fellowship is to
encourage outstanding technical research, Intel will aim to publish the research papers in renowned publications and
conferences.

9. What will happen if an award recipient gets a better job oer and would like to discontinue the
Fellowship
It is not binding on the student to continue with the Fellowship. A student can apply for discontinuation of the
Fellowship by providing strong reasons justifying the same, recommendation and support of the research guide for the
discontinuation and sucient notice period before the Fellowship can be terminated.

10. What are the key elements for selection of a candidate?

The key selection criteria include:
a) Academic credentials of the students
b) Proven track record and expertise of the research guide in the area / domain
c) Engineering and research goals
d) Relevance of research topic

11. Can the Research Area and Guide be changed at a later date?
Yes. On the basis of adequate justication, the students research area and/ or research guide can be changed.
However, continuation of the fellowship will be subjected to further review by the Intel PhD Fellowship Committee

12. Can the scholarship be taken in addition to other scholarships that the student is receiving?
Yes. The Intel PhD Fellowship can be taken in addition to other scholarships, provided the Institutes own PhD program
rules and regulations permits it and the terms and conditions of the scholarship from other sources are not violated.

13. How do I send in my applications for the Intel PhD fellowship program?
Applications for the scheme should be routed through the research guide in the format provided by Intel with a
covering letter from the research guide. The application form duly completed with necessary support documents
should be emailed in PDF format to Intel

14. To whom should the applications be sent?

Applications should be sent by email to Ms. Naheed Hazarika at naheed.hazarika@intel.com.

Notes

Notes