Lec 1 - Fpga Design Flow

Faculty of Electrical and Electronic
Engineering
FPGA Technology and

Design Flow
Programmable Electronics
MEE 10203
Semester I, Session 2016/2017
OUTLINE
Overview of FPGA
Altera DE2 board
Design flow using Altera Quartus II
Programmable Electronics (MEE10203)
FPGA Technology and Design Flow | 2 of 77
TARGETS
You understand what is FPGA
You understand Altera DE2 board
You understand how to program FPGA
Write this questions and answer

them at the end of this talk!
OVERVIEW OF FPGA TECHNOLOGY
INTRODUCTION TO FPGA
Field programmable gate array
Consists of an array of programmable logic cells
surrounded by programmable interconnect
FPGA BLOCK DIAGRAM
Basic structure: configurable logic

block (CLB/LAB), IO pads and
routing channels (interconnection)
FPGA BLOCK DIAGRAM

Basic structure: configurable logic
block (CLB/LAB), IO pads and
routing channels (interconnection)
XILINX FPGA BLOCK DIAGRAM

Clock source
IO blocks
Configurable logic blocks

(CLB)
Specific logic blocks
Source: xilinx.com
ALTERA FPGA BLOCK DIAGRAM
Logic
Elements
(LEs)
Staggered
I/O Pads
Configuration
Flash Memory
JTAG &
Control
Circuitry
User Flash
Memory
FPGA CAPACITY XILINX

Features
Logic Cells
BlockRAM
DSP Slices
DSP Performance
(symmetric FIR)
Artix-7
215,000
13Mb
740
930GMACS
Kintex-7
480,000
34Mb
1,920
2,845GMACS
Virtex-7
2,000,000
68Mb
3,600
5,335GMACS
Spartan-6
150,000
4.8Mb
180
140GMACS
Virtex-6
760,000
38Mb
2,016
2,419GMACS
Transceiver Count
Transceiver Speed
Total Transceiver
Bandwidth (full
duplex)
Memory Interface
(DDR3)
PCI Express
Interface
Analog Mixed
Signal
(AMS)/XADC
Configuration AES
I/O Pins
I/O Voltage
16
6.6Gb/s
211Gb/s
32
12.5Gb/s
800Gb/s
96
28.05Gb/s
2,784Gb/s
8
3.2Gb/s
50Gb/s
72
11.18Gb/s
536Gb/s
1,066Mb/s
1,866Mb/s
1,866Mb/s
800Mb/s
1,066Mb/s
x4 Gen2
Gen2x8
Gen3x8
Gen1x1
Gen2x8
Yes
Yes
Yes
Yes
Yes
500
1.2V, 1.35V, 1.5V,
1.8V, 2.5V, 3.3V
-
Yes
500
1.2V, 1.35V, 1.5V,
1.8V, 2.5V, 3.3V
Yes
Yes
1,200
1.2V, 1.35V, 1.5V,
1.8V, 2.5V, 3.3V
Yes
Yes
576
1.2V, 1.5V, 1.8V,
2.5V, 3.3V
-
Yes
1,200
1.2V, 1.5V, 1.8V,
2.5V
Yes
EasyPath Cost
Reduction Solution
FPGA DEVICES
Depending on the FPGA vendors:
Xilinx: Spartan, Virtex, Artix, Kintex

Altera: Cyclone, Arria, Stratix
Lattice: iCE40, MachXO2, LatticeECP3
Actel: IGLOO, IGLOO2, ProASIC3, Fusion Mixed Signal
Xilinx.com
Altera.com
Actel.com
Latticesemi.com
Wide variety of devices for the target

embedded applications
ALTERA FPGAS
Different FPGAs for different target applications/markets
CYLCLONE
Low cost, low
power
STRATIX High
bandwidth, high
density for high end
applications
ARRIA Mid-range
transceiver-based
applications
For designers choose wisely!
XILINX FPGAS
Different FPGAs for different target applications/markets
For designers choose wisely!
PROCESS TECHNOLOGIES (1/2)

Process technologies:
The technologies used to built FPGA devices
Different technologies available:
SRAM: based on static memory technology.
In-system programmable and reprogrammable. Requires external boot
devices.
Antifuse: One-time programmable.
PROM: Programmable Read-Only Memory
technology. One-time programmable because
of plastic packaging.
PROCESS TECHNOLOGIES (2/2)

EPROM: Erasable Programmable Read-Only
Memory technology. One-time programmable
but with window, can be erased with ultraviolet
(UV) light.
EEPROM: Electrically Erasable Programmable
Read-Only Memory technology. Can be
erased, even in plastic packages.
Flash: Flash-erase EPROM technology. Can
be erased, even in plastic packages. Usually,
a flash cell is smaller than an equivalent
EEPROM cell and is therefore less expensive
to manufacture.
SRAM-BASED FPGAS
Lookup table
inside FPGAs
Dominant type of FPGA

Can be reprogrammed
multiple times
It is reprogrammed every
time its powered up (thus
PROM is needed to store
permanent
information/reprogram the
FPGA)
Larger size because of
many transistor per SRAM
cell
FLASH-BASED FPGAS
Non-volatile FPGAs
(programming will not
change when power off)
Less number of
programming cycles due
to oxide charge build up
in the floating gate
ANTIFUSE-BASED FPGAS
Antifuse structure
Blow the links to make connections during

programming
OTP one time programming
Do not require PROM (because the connection is
permanent once it is programmed)
Small area because antifuses take no silicon area
SRAM VS FLASH VS ANTIFUSE
Knowing detailed FPGA internal architectures help

designers to choose the best devices for their
embedded systems
Source: berkeley.edu
DESIGN TOOLS
Depending on the FPGA vendors:
Xilinx: VIVADO, ISE, EDK, Petalinux SDK

Altera: Quartus II, SoC Embedded Design Suite, DSP builder
Lattice: Diamond, iCEcube2, LatticeMicro System
Actel: Libero IDE/SoC
Quartus II from Altera

LiberoIDE from Actel

DES. TOOL LATTICE DIAMOND
Lattice Diamond
WHY USE FPGA?

Advantages:
efficient resource utilization
Support for very high complexity designs
Support for high frequency designs
Disadvantages:
no predictable timing
100% interconnect is very expensive
good CAE-tools for FPGA-development is strongly
recommended (free SW design tools is not enough for
design development, means more cost)
FPGA VS MICROCONTROLLER
FPGA:
Programmable logic elements running in a parallel
High configurability and flexibility for further design
optimization
High cost especially for high density logic
Higher power consumption
Microcontroller:
Based on a CPU architecture (executes a set of
instructions in sequential), thus quite slow
Less configurable
Cheaper
Low power consumption
REAL TIME PROCESSING

What is real time processing?
Camera surveillance (image/video processing,
etc.)
Robotic applications (obstacles detection, etc.)
Communication protocols (3G, 4G,
802.11b/g/n, etc.)
Why FPGA suitable for real time processing?
Support parallel processing capability for high
performance/throughput applications
ALTERA DE2 FPGA BOARD
ALTERA DE2 FPGA BOARD
FEATURES (1/2)
Altera Cyclone IV 4CE115 FPGA device
Altera Serial Configuration device EPCS64
USB Blaster (on board) for programming; both JTAG and
Active Serial (AS) programming modes are supported
2 MB SRAM
Two 64 MB SDRAM
8 MB Flash memory
SD Card socket
4 Push buttons
18 Slide switches
18 Red user LEDs
9 Green user LEDs
50 MHz oscillator for clock sources
FEATURES (2/2)
24-bit CD-quality audio CODEC with line-in, line-out, and
microphone-in jacks
VGA DAC (8-bit high-speed triple DACs) with VGA-out connector
TV Decoder (NTSC/PAL/SECAM) and TV-in connector
2 Gigabit Ethernet PHY with RJ45 connectors
USB Host/Slave Controller with USB type A and type B connectors
RS-232 transceiver and 9-pin connector
PS/2 mouse/keyboard connector
IR Receiver
2 SMA connectors for external clock input/output
One 40-pin Expansion Header with diode protection
One High Speed Mezzanine Card (HSMC) connector
16x2 LCD module
DE2 BOARD STRUCTURE
FPGA DEVICE IN DE2 BOARD
Cyclone IV EP4CE115F29 device

114,480 LEs (logic elements)
3,888 Kbits embedded memory
4 PLLs (phase locked loop)
Source: altera.com
MEMORY DEVICES
128 MB (32 M x 32 bit) SDRAM

2 MB (1 M x 16) SRAM
8 MB (4 M x 16) Flash with 8-bit mode
32 Kb EEPROM
CLOCK
Three 50 MHz oscillator clock inputs
SMA connectors (external clock input/output)
AUDIO
24-bit encoder/decoder (CODEC)
Line-in, line-out, and microphone-in jacks
DISPLAY
16x2 LCD module
SWITCHES AND INDICATORS

18 slide switches and 4 push-buttons switches
18 red and 9 green LEDs
Eight 7-segment displays
POWER
12 V DC input
Switching and step-down regulators LM3150MH
CONNECTORS
Two Ethernet 10/100/1000 Mbps ports

High Speed Mezzanine Card (HSMC)
Configurable I/O standards (voltage levels:3.3/2.5/1.8/1.5V)
USB type A and B
Provide host and device controllers compliant with USB 2.0
Support data transfer at full-speed and low-speed
PC driver available
40-pin expansion port
Configurable I/O standards (voltage levels: 3.3/2.5/1.8/1.5V)
VGA-out connector
VGA DAC (high speed triple DACs)
DB9 serial connector for RS-232 port with flow control
PS/2 mouse/keyboard
CONFIGURING FPGA DEVICE

JTAG and AS mode configuration
EPCS64 serial configuration device
On-board USB Blaster circuitry
FPGA DESIGN FLOW USING ALTERA

QUARTUS II
DE2 BOARD PROGRAMMING FLOW

Using HDL or
schematic
1
2
3
4
5
PROGRAMMING FLOW STEPS

Design Entry/RTL Coding
Design Specification
Behavioral or Structural Description of Design
RTL Simulation
Functional Simulation (Modelsim, Quartus II)
Verify Logic Model & Data Flow (No Timing
Delays)
LE
M512
M4K
I/O
Synthesis
Translate Design into Device Specific Primitives
Optimization to Meet Required Area & Performance Constraints
Precision Synthesis, Synplify/Synplify Pro, Design Compiler FPGA,
Quartus II
Source: altera.com
Place & Route
Map Primitives to Specific Locations inside

Target Technology with Reference to Area &
Performance Constraints
Specify Routing Resources to Be Used
SYNTHESIS STEP
VHDL Code for mux
case S is
when "00" => temp:=A;
when "01" => temp:=B;
when "10" => temp:=C;
when Others => temp:=D;
end case;
Convert HDL designs into equivalent logic

gates inside FPGA (in the form of LUT)
FITTING (PLACE AND ROUTE)
Place the logic gates (LUT) in a

specific location inside FPGA device
SCHEMATIC ENTRY
Using pre-designed logic blocks
Making connection between blocks
QUARTUS II MAIN DISPLAY
Latest Quartus II version: 14.0

NEW PROJECT
NEW PROJECT WIZARD
SPECIFY PROJECT DIRECTORY
ADDING EXISTING HDL FILES
SELECT TARGET FPGA DEVICE

Check the FPGA device name on the FPGA chip
PROJECT SUMMARY
PROJECT CREATED
CREATE NEW VHDL FILE

File > New, choose VHDL file
EXAMPLE OF VHDL FILE

LIBRARY ieee ;
USE ieee.std logic 1164.all ;
ENTITY light IS
PORT ( x1, x2 : IN STD LOGIC ;
f : OUT STD LOGIC ) ;
END light ;
ARCHITECTURE LogicFunction OF light IS
BEGIN
f <= (x1 AND NOT x2) OR (NOT x1 AND x2);
END LogicFunction ;
COMPILING VHDL DESIGNS

Click Processing > Start Compilation
The software will

perform synthesis,
place and route of
the VHDL designs
ERROR DURING COMPILATION

Double click the error to go directly to the related
line in VHDL code
PIN ASSIGNMENT
What?
Specify which signal in VHDL code to which
pin on the FPGA board
Click Assignment > Pins
AVAILABLE PINS
ENTITY light IS
PORT ( sys_clk, reset : IN STD_LOGIC ;
7_out : OUT STD_LOGIC_VECTOR(6 downto 0 ) ;
END light ;
Physical pins in
the DE2 board
Pin number from DE2

board datasheet
Pin assignment editors
in Quartus II
Signals in
VHDL code
(in ports
declaration)
COMPLETED PINS ASSIGNMENT

Example of completed pins assignment
SIMULATING THE DESIGN

Why?
To make sure the design is functionally correct
Click Files > New > Other Files
WAVEFORM EDITOR
Blank waveform editor
ADD SIGNALS TO WAVEFORM

Click Edit > Insert Node or Bus
ADDED SIGNALS
SPECIFYING INPUT SIGNALS
Setting
value for
clock signal
SETTING SIMULATION
Functional and timing simulations
Click Assignment >Setting > Simulator
SIMULATION STEPS
Processing > Generate Functional Simulation
Netlist (for functional simulation)
Processing > Start Simulation
SIMULATION RESULTS EXAMPLES
Functional simulation
Timing simulation
PROGRAMMING FPGA DEVICE

Two methods:
JTAG (passive serial)
AS (active serial)
In the active configuration schemes, the device controls the configuration
process and gets the configuration data from an external memory device. Active
serial (AS) and active parallel (AP) are active configuration schemes.
In the passive configuration schemes, the configuration device controls the
configuration process and supplies the configuration data. The configuration
device can be an external intelligent host, such as a PC, a microprocessor, or a
MAX series CPLD. Passive serial (PS), fast passive parallel (FPP), and JTAG
are passive configuration schemes.
JTAG PROGRAMMING (1/3)

From the Tools menu, select programmer
Click on Add File. Select filename.sof
Check Hardware Setup. Select your download
cable on Currently selected hardware (USBBlaster, ByteBlasterII, etc)
Select JTAG from Mode

Turn on Program/configure
Click Start
Check the results on the DE2 board
AS PROGRAMMING (1/3)
PROGRAMMING COMPLETED
TECHNICAL REFERENCES
Some links for further exploration:
Terasic.com
Altera.com
Fpga4fun.com
THANK YOU

Lec 1 - Fpga Design Flow

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Faculty of Electrical and Electronic

FPGA Technology and

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 2 of 77

Write this questions and answer

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 3 of 77

OVERVIEW OF FPGA TECHNOLOGY

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 5 of 77

FPGA BLOCK DIAGRAM

Basic structure: configurable logic

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 6 of 77

FPGA BLOCK DIAGRAM

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 7 of 77

XILINX FPGA BLOCK DIAGRAM

Configurable logic blocks

FPGA Technology and Design Flow | 8 of 77

ALTERA FPGA BLOCK DIAGRAM

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 9 of 77

FPGA CAPACITY XILINX

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 10 of 77

Xilinx: Spartan, Virtex, Artix, Kintex

Wide variety of devices for the target

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 11 of 77

For designers choose wisely!

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 12 of 77

For designers choose wisely!

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 13 of 77

PROCESS TECHNOLOGIES (1/2)

FPGA Technology and Design Flow | 14 of 77

PROCESS TECHNOLOGIES (2/2)

FPGA Technology and Design Flow | 15 of 77

Programmable Electronics (MEE10203)

Dominant type of FPGA

FPGA Technology and Design Flow | 16 of 77

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 17 of 77

Blow the links to make connections during

FPGA Technology and Design Flow | 18 of 77

SRAM VS FLASH VS ANTIFUSE

Knowing detailed FPGA internal architectures help

Programmable Electronics (MEE10203)

Xilinx: VIVADO, ISE, EDK, Petalinux SDK

Quartus II from Altera

LiberoIDE from Actel

DES. TOOL LATTICE DIAMOND

FPGA Technology and Design Flow | 21 of 77

WHY USE FPGA?

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 22 of 77

FPGA Technology and Design Flow | 23 of 77

REAL TIME PROCESSING

Programmable Electronics (MEE10203)

FPGA Technology and Design Flow | 24 of 77

ALTERA DE2 FPGA BOARD

ALTERA DE2 FPGA BOARD