CSCE2302: Computer Architecture Lab

Shahd Sherif
ID: 900140569
Mips Single Cycle Processor: Ori, Bne
October 21, 2016




Instruction

Op5:0

R-type

000000

10

lw

100011

00

sw

101011

00

beq

000100

01

addi

001000

00

j
ori

000010
001101

0
1

0
1

X
0

X
1

X
0

0
0

0
0

X
0

1
0

XX
10

bne

000101

01

ALUOp1:0
00
01
10
11

which RegWrite RegDst AluSrc Branch bne MemWrite MemtoReg Jump ALUOp1:

Meaning
Add
Subtract
or
Look at func




This is the drawing of which my edited code is based on. All is explained in the code in the
coming pages:


Here, in the processor module (line 22 and 24), I added a BNE and which wire. I sent which
to both the controller and datapath. I sent it to the controller as an output, so we can set a
value in it, and sent it to the datapath as an input to be used.

In the controller, I made which an output, and accidentally declared it as an input wire. The
code now doesnt contain that. Next, I sent which and bne to the maindec for initialization,
where they can finally take their values.

In the controller, pcsrc gets set to 1 if it is a beq opereation and the registers are equal, or if
it is a bne instruction and the registers are different (code has been since adjusted).

In the maindec, which, gets set to 1 if the instruction is an ori instruction, and bne gets set
to 1 if it is a bne instruction. Also, if it is an ori instruction, aluop gets set to 2b10, which
indicates oring as follows:




In line 101, if aluop is 10, which it will be in the case of ori, we will tell the alu to perform an
or operation. BNE, will perform subtraction as usual. Finally, in the datapath, I declared
which, zeroimm, and whichone as inputs. They are: the selection line of the mux which will
decide whether the sign extended immediate or the zero extended immediate will pass, the
zero extended immediate itself, and the result of this that I am talking about; respectively.

Here I call the zero extended module I created to extend the immediate and place it in
zeroimm as I stated before. Next, I build the mux and send to it the sign extended
immediate, the zero extended immediate, which as selection line, and whichone as the
output. Then I replace the original signim with which one in the larger mux that decides
what srcb is.


Lastly, that is the zero extention module.

Here is some proof that it detects BNE and Ori:

Here, the first instruction is one that isnt known by the main decoder, so the default is
11bx, and displaying the message idk this one yet. Next is a BNE instruction, and an ori
instruction.

Simmulation:

To verify the correctness, we can check to see if the sequence of instructions is correct.
First, we have an ori instruction (34088000), it puts 8000 in register 8 ($t0). So this means
ori is successfully implemented. We have another ori at 350a8001, which puts 8001 in
register a ($t2), which indeed is the right thing. Because 8000 or 8001 is 8001. Next, there is
a BEQ instruction which is not taken since 8000 is not equal to -32786. So we carry on to the
SLT instruction that says if -327695 is less than 8000 t3 is one. Of course, t3 will be zero, and
the next BNE instruction will be taken. Indeed this is the case, the j instruction is skipped,
and the next is a sub instruction (1485022) this shows that BNE and ori are working
correctly. The sub instructionsubtaracts 8001 with 8000, result in t2 should be 1, which it is:

then, another or instruction, which ors 8000 with ff which is indeed 80ff, again the ori
instruction is working properly. Next, we add t3 to t2 and place in t3, this should be two,
which worked. Next, a sub of 1-80ff, which yields ffff7f02 in T0. Finally we store this in 2+82.
Which is the address of 84, and as shown by the signal wd[31:0], it was indeed stored in the
memory.


Here is the simulation we were asked to hand in:

Here it is in tabular form:


In response to the question of what value is stored in 84 (0x54), the answer to this should
be evident by my proof that the test bench provided is incorrect.

The following picture is the value that should be stored in the memory, which it indeed is. It
is -33022.

This is the output in the console that says the simulation succeeded. The altered part of the
Tb is also shown below.


Machine Code and Code:

34088000
20098000
350a8001
11090005
0128582a
15600001
08000009
01485022
350800ff
016a5820
01484022
ad680052


Code: