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Main
memory
I/O
System
Bus
CPU
CPU
Registers
Structure
Internal
Bus
Control
Unit
CONTROL
UNIT
Sequencing
Logic
Control Unit
Registers and
Decoders
Control
Memory
ALU
Read
Memory
Write
N Words
Address
Data
Read
N1
I/O Module
Write
Address
M Ports
Internal
Data
Internal
Data
External
Data
Interrupt
Signals
External
Data
Address
Instructions
Data
Data
CPU
Interrupt
Signals
Control
Signals
Data
Processor
reads an
instruction
or a unit of
data from
memory
Processor
to
memory
Processor
writes a unit
of data to
memory
I/O to
processor
Processor
reads data
from an I/O
device via
an I/O
module
Processor
to I/O
I/O to or
from
memory
Processor
sends data
to the I/O
device
An I/O
module is
allowed to
exchange
data
directly with
memory
without
going
through the
processor
using direct
memory
access
Slide
4
Control
.
.
.
Address
.
.
.
Data
Handshaking,
direction,
transfer mode,
arbitration, ...
one bit (serial)
to several bytes;
may be shared
July 2004
What is a bus?
A Bus Is:
shared communication link
Processor
Input
Control
Datapath
Memory
Output
Busses
Advantages of Buses
Processer
I/O
Device
I/O
Device
Versatility:
New devices can be added easily
Peripherals can be moved between computer
systems that use the same bus standard
Low Cost:
A single set of wires is shared in multiple ways
I/O
Device
Memory
Disadvantage of Buses
Processor
I/O
Device
I/O
Device
I/O
Device
Memory
Control lines:
Signal requests and acknowledgments
Indicate what type of information is on the data lines
Data lines carry information between the source and the destination:
Data and Addresses
Complex commands
Bus
Master
Bus
Slave
request
action
Types of Busses
Processor-Memory Bus (design specific)
Short and high speed
PCI Bus
I/O Busses
Memory
I/O Devices
A Two-Bus System
Processor Memory Bus
Processor
Memory
Bus
Adaptor
I/O
Bus
Bus
Adaptor
Bus
Adaptor
I/O
Bus
I/O
Bus
I/O buses tap into the processor-memory bus via bus adaptors:
Processor-memory bus: mainly for processor-memory traffic
I/O buses: provide expansion slots for I/O devices
Apple Macintosh-II
NuBus: Processor, memory, and a few selected I/O devices
SCCI Bus: the rest of the I/O devices
A Three-Bus System
Processor Memory Bus
Processor
Memory
Bus
Adaptor
Backplane Bus
Bus
Adaptor
Bus
Adaptor
I/O Bus
I/O Bus
backside
cache
Bus
Adaptor
Backplane Bus
Bus
Adaptor
I/O Bus
I/O Bus
Memory bus
Caches
Graphics bus (for fast frame buffer)
I/O busses are connected to the backplane bus
Advantage:
Busses can run at different speeds
Much less overall loading!
Memory
Advantage: involves very little logic and can run very fast
Disadvantages:
Every device on the bus must run at the same clock rate
Asynchronous Bus:
It is not clocked
It can accommodate a wide range of devices
Busses so far
Master
Slave
Control Lines
Address Lines
Data Lines
Arbitration:
Obtaining Access to the Bus
Control: Master initiates requests
Bus
Master
Bus
Slave
Device N
Lowest
Priority
Device 2
Grant
Grant
Release
Request
wired-OR
Advantage: simple
Disadvantages:
Cannot assure fairness:
A low-priority device may be locked out indefinitely
The use of the daisy chain grant signal also limits the bus speed
Grant
Device 2
Device N
Req
Bus
Arbiter
A single point of failure (SPOF) is a part of a system that, if it fails, will stop the entire system from working. SPOFs are undesirable
in any system with a goal of high availability or reliability, be it a business practice, software application, or other industrial
system
Slide
37
CPU
Main
memory
Cache
System bus
I/O controller
Disk
I/O controller
I/O controller
Graphics
display
Network
Disk
July 2004
Slide
38
Interrupts
Main
memory
Cache
Memory bus
AGP
Bus
adapter
PCI bus
Intermediate
buses / ports
Bus
adapter
I/O bus
I/O controller
Graphics
display
Bus
adapter
I/O controller
Network
I/O controller
Disk
I/O controller
Disk
CD/DVD
July 2004
Point-to-Point Interconnect
Principal reason for change
was the electrical constraints
encountered with increasing
the frequency of wide
synchronous buses
Point-to-point interconnect
has lower latency, higher
data rate, and better
scalability
Latency is the time it takes for the data requested by the CPU to start arriving.
Bandwidth is the rate at which the data arrives..
Core
Core
PCIe
Memory
Chipset
PCIePCI
Bridge
PCIe
Memory
PCIe
PCIe
PCIe
Legacy
endpoint
PCIe
Switch
PCIe
endpoint
PCIe
PCIe
endpoint
PCIe
endpoint
From electronicdesign.com
Transaction
Data Link
Transaction layer
packets (TLP)
Data link layer
packets (DLLP)
Physical
Transaction
Data Link
Physical
I/O
Configuration
Message
Table 3.2
PCIe TLP Transaction Types
Address Space
Memory
I/O
Configuration
Message
Memory, I/O,
Configuration
TLP Type
Memory Read Request
Memory Read Lock Request
Memory Write Request
I/O Read Request
I/O Write Request
Config Type 0 Read Request
Config Type 0 Write Request
Config Type 1 Read Request
Config Type 1 Write Request
Message Request
Message Request with Data
Completion
Completion with Data
Completion Locked
Completion Locked with Data
Purpose
Transfer data to or from a location in the
system memory map.
Transfer data to or from a location in the
system memory map for legacy devices.
Transfer data to or from a location in the
configuration space of a PCIe device.
Provides in-band messaging and event
reporting.
QPI
QPI
I/O Hub
PCI Express
I/O device
DRAM
Core
D
DRAM
Core
C
I/O device
I/O device
DRAM
Core
B
I/O device
Core
A
DRAM
I/O Hub
Memory bus
Packets
Protocol
Protocol
Routing
Routing
Link
Physical
Flits
Phits
Link
Physical
COMPONENT A
Fwd Clk
Transmission Lanes
Reception Lanes
Rcv Clk
Rcv Clk
Reception Lanes
Transmission Lanes
Fwd Clk
Operate on the
level of the flit (flow
control unit)
Protocol Layer