Contents

1.Module Classification Information

2.Precautions in use of LCD Modules
3.General Specification
4.Absolute Maximum Ratings
5.Electrical Characteristics
6.Optical Characteristics
7.Interface Pin Function
8.Contour Drawing & Block Diagram
9.Function Description
10.Character Generator ROM Pattern
11.Instruction Table
12.Timing Characteristics
13.Initializing of LCM
14.Reliability
15.Backlight Information
16. Inspection specification
17. Material List of Components for RoHs

3 29

7.Interface Pin Function

Pin No. Symbol

Level

Description

VSS

0V

Ground

VDD

5.0V

VO

RS

H/L

H: DATA, L: Instruction code

R/W

H/L

H: Read(MPUModule) L: Write(MPUModule)

H,HL

DB0

H/L

Data bus line

DB1

H/L

Data bus line

DB2

H/L

Data bus line

10

DB3

H/L

Data bus line

11

DB4

H/L

Data bus line

12

DB5

H/L

Data bus line

13

DB6

H/L

Data bus line

14

DB7

H/L

Data bus line

15

LED +

16

LED

Supply Voltage for logic

(Variable) Operating voltage for LCD

Chip enable signal

8 29

VR
10K ~20K

Vdd
Vo
V ss

External contrast adjustm ent.

Bias and
Power Circuit

80 series
or
68 series

Com 1~16

C ontroller/Com Driver
H D44780
or
Equivalent

N.V.
Generator

M PU

RS
R /W
E
D B0~DB7

16X 2 LCD
Seg1~40
Seg41~80

Seg D river

M
CL1
CL2
V dd,V ss,V1~V5

O ptional

Character located
D D RA M address
D D RA M address

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F

10 29

9.Function Description
The LCD display Module is built in a LSI controller, the controller has two 8-bit registers, an
instruction register (IR) and a data register (DR).
The IR stores instruction codes, such as display clear and cursor shift, and address information for
display data RAM (DDRAM) and character generator (CGRAM). The IR can only be written from the
MPU. The DR temporarily stores data to be written or read from DDRAM or CGRAM. When
address information is written into the IR, then data is stored into the DR from DDRAM or CGRAM.
By the register selector (RS) signal, these two registers can be selected.
RS

R/W

Operation

IR write as an internal operation (display clear, etc.)

Read busy flag (DB7) and address counter (DB0 to DB7)

Write data to DDRAM or CGRAM (DR to DDRAM or CGRAM)

Read data from DDRAM or CGRAM (DDRAM or CGRAM to DR)

Busy Flag (BF)

When the busy flag is 1, the controller LSI is in the internal operation mode, and the next instruction
will not be accepted. When RS=0 and R/W=1, the busy flag is output to DB7. The next instruction
must be written after ensuring that the busy flag is 0.
Address Counter (AC)
The address counter (AC) assigns addresses to both DDRAM and CGRAM
Display Data RAM (DDRAM)
This DDRAM is used to store the display data represented in 8-bit character codes. Its extended
capacity is 808 bits or 80 characters. Below figure is the relationships between DDRAM addresses
and positions on the liquid crystal display.
High bits

Low bits
Example: DDRAM addresses 4E

AC
(hexadecimal)

AC6 AC5 AC4 AC3 AC2 AC1 AC0

11 29

Display position DDRAM address

1

10

11

12

13

14

15

16

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F
2-Line by 16-Character Display

Character Generator ROM (CGROM)

The CGROM generate 58 dot or 510 dot character patterns from 8-bit character codes. See Table 2.
Character Generator RAM (CGRAM)
In CGRAM, the user can rewrite character by program. For 58 dots, eight character patterns can be
written, and for 510 dots, four character patterns can be written.
Write into DDRAM the character code at the addresses shown as the left column of table 1. To show
the character patterns stored in CGRAM.

12 29

Relationship between CGRAM Addresses, Character Codes (DDRAM) and Character patterns
Table 1.
F o r 5 * 8 d o t c h a ra c te r p a tte rn s
C h a ra c te r C o d e s
( D D R A M d a ta )
7

H ig h

Low

* 0

* 0

C h a ra c te r P a tte rn s
( C G R A M d a ta )

C G R A M A d d re ss
5

Low
0 0
0 0
0 1
0 1
0 0 0 1 0
1 0
1 1
1 1
0 0
0 0
0 1
0 1
0 0 1
1 0
1 0
1 1
1 1
0 0
0 0

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*

H ig h

1
1
1
1

0
0
1
1

0
1
0
1

H ig h
* *
* *
* *
* *
* *
* *
* *
* *
* *
* *
* *
* *
* *
* *
* *
* *
* *

Low
0
0
0

0
0

0
0
0
0
0

0
0
0
0
0

0
0
0

0
0
0

C h a ra c te r
p a tte rn ( 1 )

0
0
0

C u rs o r p a tte rn

0
0
0

0
0
0

0
0
0

0
0
0

C h a ra c te r
p a tte rn ( 2 )

C u rs o r p a tte rn

F o r 5 * 1 0 d o t c h a ra c te r p a tte rn s
C h a ra c te r C o d e s
( D D R A M d a ta )
7

H ig h

Low

* 0

C h a ra c te r P a tte rn s
( C G R A M d a ta )

C G R A M A d d re ss
5

0
0
0
0
0
0
0
0
1
1
1

0
0
0
0
1
1
1
1
0
0
0

H ig h

0
0
1
1
0
0
1
1
0
0
1

0
1
0
1
0
1
0
1
0
1
0

*
*
*
*
*
*
*
*
*
*
*

Low

*
*
*
*
*
*
*
*
*
*
*

* 0
* 0
*
*
*
*
*
*
*
*
* 0

0
0
0

0
0

0
0

0
0
0

0
0

0
0
0

0
0
0

0
0
0
0

0
0
0
0

0
0
0
0

0
0
0
0
0

H ig h

: " H ig h "

13 29

2
Low

C h a ra c te r
p a tte rn

C u rs o r p a tte rn

10.Character Generator ROM Pattern

Upper
4 bit
Lower
4 bit

LLLL LLLH LLHL LLHH LHLL LHLH LHHL LHHH HLLL HLLH HLHL HLHH HHLL HHLH HHHL HHHH

LLLL

CG
RAM
(1)

LLLH

CG
RAM
(2)

LLHL

CG
RAM
(3)

LLHH

CG
RAM
(4)

LHLL

CG
RAM
(5)

LHLH

CG
RAM
(6)

LHHL

CG
RAM
(7)

LHHH

CG
RAM
(8)

HLLL

CG
RAM
(1)

HLLH

CG
RAM
(2)

HLHL

CG
RAM
(3)

HLHH

CG
RAM
(4)

HHLL

CG
RAM
(5)

HHLH

CG
RAM
(6)

HHHL

CG
RAM
(7)

HHHH

CG
RAM
(8)

14 29

11.Instruction Table
Instruction Code
Instruction

Execution time

Description

(fosc=270Khz)

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Clear Display

Write 00H to DDRAM and set

DDRAM address to 00H from AC

1.53ms

1.53ms

Return Home

Set DDRAM address to 00H from AC

and return cursor to its original position
if shifted. The contents of DDRAM are
not changed.

Entry Mode
Set

I/D

SH

Assign cursor moving direction and

enable the shift of entire display.

39s

Display
ON/OFF
Control

Set display (D), cursor (C), and blinking

of cursor (B) on/off control bit.

39s

Cursor or
Display Shift

control bit, and the direction, without

Function Set

Set CGRAM
Address
Set DDRAM
Address

Set cursor moving and display shift

S/C R/L

39s

changing of DDRAM data.

Set interface data length
(DL:8-bit/4-bit), numbers of display line
(N:2-line/1-line)and, display font type
(F:511 dots/58 dots)

39s

AC5 AC4 AC3 AC2 AC1 AC0 Set CGRAM address in address counter.

39s

DL

AC6 AC5 AC4 AC3 AC2 AC1 AC0 Set DDRAM address in address counter.

39s

Whether during internal operation or not

can be known by reading BF. The
AC6 AC5 AC4 AC3 AC2 AC1 AC0
contents of address counter can also be
read.

0s

Read Busy
Flag and
Address

BF

Write Data to
RAM

D7

D6

D5

D4

D3

D2

D1

D0

Write data into internal RAM

(DDRAM/CGRAM).

43s

Read Data
from RAM

D7

D6

D5

D4

D3

D2

D1

D0

Read data from internal RAM

(DDRAM/CGRAM).

43s

dont care

15 29

12.Timing Characteristics
12.1

Write Operation

Ta=25, VDD=5.0V
Item

Symbol

Min

Typ

Max

Unit

Enable cycle time

TC

1200

ns

Enable pulse width

TPW

140

ns

Enable rise/fall time

TR,TF

25

ns

Address set-up time (RS, R/W to E)

tAS

ns

Address hold time

tAH

10

ns

Data set-up time

tDSW

40

ns

tH

10

ns

Data hold time

16 29

12.2

Read Operation

Ta=25, VDD=5V
Item

Symbol

Min

Typ

Max

Unit

TC

1200

ns

TPW

140

ns

TR,TF

25

ns

Address set-up time (RS, R/W to E)

tAS

ns

Address hold time

tAH

10

ns

Data delay time

tDDR

100

ns

Data hold time

tH

10

ns

Enable cycle time

Enable pulse width (high level)
Enable rise/fall time

17 29

13.Initializing of LCM
Power on
Wait for more than 40 ms after VDD rises to 4.5 V
BF can not be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set
0
*
0
0
1
1
0
*
*
*
Wait for more than 39us
BF can not be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0
*
*
*
0
0
0
1
0
*
0
*
*
*
*
*
0
N F
*

Function set

Wait for more than 39 s

BF can not be checked before this instruction.

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0
0
*
*
* Function set
0
1
0
*
0
0
N F
*
*
*
*
*
*
0
Wait for more than 37us

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display ON/OFF control
0
0
*
* *
*
0
0
0
0
0
*
* *
*
1
D C B
0
Wait for more than 37 s
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Clear
0
0
0
*
*
*
*
0
0
0
0
1
0
*
*
*
*
0
0
0
Wait for more than 1.53ms
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Entry Mode Set
0
0
*
* *
*
0
0
0
0
0
* *
*
0
0
1
I/D SH *
Initialization ends

4-Bit Ineterface

18 29

Power on
Wait for more than 40 ms after VDDrises to 4.5 V
BF can not be checked before this instruction.

RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Function set
0 0 0 0 1 1 N F * *
Wait for more than 39us
BF can not be checked before this instruction.

RS R/WDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Function set
0 0 0 0 1 1 N F * *
Wait for more than 37us
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display ON/OFF control
0 0 0 0 0 0 1 B C D
Wait for more than 37 s
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Display Clear
0 0 0 0 0 0 0 0 0 1
Wait for more than 1.53ms
RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Entry Mode Set
0 0 0 0 0 0 0 1 I/D S
Initialization ends

8-Bit Ineterface

19 29

15.Backlight Information
Specification
PARAMETER

SYMBOL MIN

TYP

MAX

UNIT

TEST

Supply Current

ILED

12.8

16

20

mA

V=3.5V

Supply Voltage

3.4

3.5

3.6

Reverse Voltage

VR

IV

212

265

CD/M2 ILED=16mA

Luminous
Intensity

ILED16mA

LED Life Time

(For Reference

CONDITION

50K

only)

Hr.

25,50-60%RH,
(Note 1)

Color

White

Note: The LED of B/L is drive by current only, drive voltage is for reference only.
drive voltage can make driving current under safety area (current between
minimum and maximum).
Note 1:50K hours is only an estimate for reference.

2.Drive from pin15,pin16

B/L

LCM
ill never get Vee output from pin15)

21 29