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Lauren Donohoe

EE 310, Fall 2012, Section 6


Experiment 6 Report

INTRODUCTION
In this experiment we built and investigated a few different circuits that all contain an NMOS
amplifying transistor along with two complementary PMOS transistors set up as a current mirror and
acting as an active load. In the first week we chose a resistor value to design a PMOS current mirror
circuit which would provide a 100A bias current. This current mirror was then used for the rest of the
experiment as a constant current source and active load. Next, we used a NMOS transistor to create a
common source amplifier. We then adjusted the DC drain voltage and measured the amplifier gain. In
the second week of the experiment we used the same current mirror and bias conditions. First, we
connected the NMOS transistor in a common gate amplifier configuration and measured the circuits
gain. Comparing this gain and the previous one, we can find the body transconductance and body effect
parameter of the NMOS amplifying transistor. Last, we found a third configuration that we could use to
directly measure the body effect from the circuit and compared these measurements to the calculated
values we found previously.
In this experiment e will be using the parameters we found in experiment 4 for the MOSFET IC
chip to do various calculations. As I changed lab groups, I am going to use the parameters that I
measured originally and I will mention in the error analysis that I realize these values will not be exact,
as they vary for each IC chip, providing some error in the calculations done throughout this lab report.
The parameters found for the MOSFET IC chip in experiment 4 can be found in table 1 below.
Table 1: IC Chip MOSFET Parameters
Lab 6 Name
VTN /VTP
kn / k p
n /p
VAN /VAP
Lab 4 Name
Q1
VTN = 1.08 V
kn = 273 A/V2 n = 0.00524 V-1 VAN = 191 V
n2p
2
-1
Q2
VTP = -1.45 V
kp = 369 A/V
p = 0.08197 V VAP =12.2 V
p3p
Q3
VTP = -1.45 V
kp = 376 A/V2 p = 0.07940 V-1 VAP = 12.6 V
p1p
**Also the ratio W/L = 6 for PMOS and W/L = 3 for NMOS.
SCHEMATICS, DATA, and GRAPHS with DISUCSSION by Task
Task1
In task 1, we designed a current mirror to act as an active load. Once we had implemented this
current mirror/active load, we used it for each of the different amplifier configurations throughout the
lab. Due to the fact that we kept the same bias conditions for the different configurations throughout
the lab, comparisons of the gains measured on each will be more meaningful. To build this current
mirror/active load we needed two complementary PMOS devices and the reference resistor according
to the PMOS device parameters and the desired reference current. Given the following circuit
schematic, we were instructed to determine a value for R3 resulting in a DC drain current of 100A.
Schematic 1: Current Mirror/Active Load Schematic

Based on the device parameters from experiment 4, we needed to choose R3 such that the drain current
would be 100A. (Assuming the devices are matched, we need to find the necessary resistance so that
the drain current on the left will be 100A which will result in a drain current on the left that matches
that on the right. Since the devices are not exactly matched, but close, this means a current of around
100A on the left will result in a current of around 100A on the right.) In order to find the resistance
value needed, we first realized that the PMOS transistor Q3 must be operating in saturation since the
gate is tied to the drain the source to drain voltage and the source to gate voltage are the same, so for
negative VTP we know the saturation condition VSD > VSD(SAT) must be met. Since Q3 is operating in the
saturation region, we can use the saturation device equation (assuming the effect of is negligible) to
find the necessary source to gate voltage for a drain current of 100A. With this voltage and the desired
current, we can find a resistance for R3 using Ohms Law.
Calculations

To find the voltage drop across R3:

To find the resistance R3:

The previous calculation was done in the design proposal before lab, but when we put this resistor into
the circuit in lab, we realized that we had to adjust the resistor value to get closer to the desired current.
One of the reasons that we needed to make this adjustment is because in the calculation we took P to
be negligible (about 0). Since from lab 4 we know that P = 0.0794 V-1, this approximation that P = 0
resulted in some error in our calculation for R3. As a result, we had to tweak our value of R3 in order to

get ID3 100A (ID3 = 100A 5% as specified in the lab). Our actual measured resistance was R3 =
97.5k.
With this R3 in the circuit (as shown in schematic 1, above) we measured the current on the left
side of the current mirror to be ID3 = 97.9A. We then measured the voltage drop across the 50k
resistor to be 4.77V (and the actual resistance 49.7k) and used Ohms law to find the current on the
right side of the current mirror, ID2 = 95.976A. The results from Task 1 are summarized in Table 2
below.
Calculation

Table 2: Task 1 Data Summary


Desired ID Calculated R3 Actual R3
100A
80.34k
97.5k

Measured ID3
97.9A

Actual R50k
49.7k

Measured V50k
4.77V

ID2
95.976A

DISCUSSION

We attempted to design R3 in the given circuit configuration in order to have ID2 = 100A. As we
can see by the measurements of ID2, we achieved a current within about 4% error from the desired
100A. There are multiple reasons for this error. When we calculated the value for R3, we neglected the
effect if . When we put this calculated R3 into the circuit we found that we had to adjust the value to
get close to the desired current. As a result, we used a guess and check method for setting the
resistance which sets the current. As we checked the current for each resistor, we checked the current
on the left hand side of the mirror. In other words, we adjusted the value of R3 assuming the devices
were matched, thus, when we found a resistance for which the current on the left was pretty close, we
kept it, then measured the current on the right. We were not completely correct in assuming that the
devices are matched. While they are on the same IC chip and their parameters are close, they are not
exactly the same. What we could have done would be to use the ratio of the kp parameters from lab 4 to
find what the current on the right would be compared to the left, or measured the current on the right
rather than the left as we adjusted the resistance. Either of these approaches would have given us a
slightly closer current ID2 to the desired 100A.

Task2

In task 2, we consider adding a NMOS transistor to our current mirror. The addition of a third
MOSFET to this circuit allows for an amplifier circuit which uses the current mirror built in task 2 as an
active load. The important part of the following schematic for this task is the DC bias conditions.
Schematic 2: Common-Source Amplifier Circuit Schematic

Within this circuit we can see the current mirror set up in task 1. The left side of the current
mirror is unchanged, but the right side is now connected to the amplifying device, the current mirror
now acting as an active load. The current mirror sets VSG2 and therefore sets the current ID2 = ID3 for the
right side of the circuit. The purpose of R1 and R2 is to set VGS1 properly in order for the MOSFETs to all
operate in the saturation region. Using the saturation device equation, we can find the necessary VGS1 to
keep Q1 operating in saturation. Using this VGS1 and the instruction for 10A through R1 and R2, we can
find the resistor values.
Calculations:
Saturation region device equation for NMOS:

To find the voltage at the source of Q1:

To find the voltage at the gate of Q1:

The voltage at the gate is the voltage drop across R2

To find the resistance R2:

To find the voltage drop across R1:

To find the resistance R1:

The values above were calculated in the design proposal for week 1 of this experiment. In lab
during week 1, we built the circuit in schematic 2 (above). The actual measured resistances used can be
found in the summary table below.
Table 3: Task 2 Data Summary
Mirror ID2 = ID1
VGS1
VG1 = VR2
VR3
R2 (calculated) R1 (calculated) R1 (measured)
100A
1.685V
1.69V
8.31V
169k
831k
833.2k
*Note: There is no value for measured R2 in anticipation of task 3 we used a potentiometer for R3.
DISCUSSION
The error in these calculations is present, but is handled in the next task so that a slight variation
in these calculated resistances does not cause a huge difference to the circuit. It is important that the
resistances keep the gate voltage around the right value such that Q1 stays in the saturation region. The
calculated values for this task were done in the design proposal before the actual lab period, and as a
result, the resistance were calculated using ID1 = 100A rather than the actual measured value. This does
not cause a huge problem, but does make a slight difference in the resistance value calculations.
The interesting thing about these resistances is that it is important that they are close enough to
keep VGS1 within the saturation region range of Q1, but within that range, the values do not need to be
extremely specific because in the next task we replace R2 with a potentiometer so that we can readily
and easily adjust to the desired bias conditions.

Task3
In task 3 we used a potentiometer in place of R2 so that we could more easily achieve the
correct bias conditions. Once we placed a potentiometer for R2 in the circuit, we adjusted it such that
the DC drain voltage for Q1, the voltage marked VO on the schematic, was 5V. Using the voltmeter
function on the DMM, we adjusted the potentiometer such that the voltage VO = 4.95V.
Table 4: Task 3 Data
R2 (calculated) R1 (calculated)
169k
831k

R1 (actual, measured)
833.2k

R2(actual, measured)
2M pot
easily adjusted

VO desired
5V

VO measured
4.95V

We used our parameters from lab 4 and measurements taken before task 3 to calculated the
values we expect for VGS1, VGS2, and ID1 =ID2. (Since we had not included the effects of being nonzero in
our previous calculations, these numbers will be slightly different than the previously calculated ones.)
Then, with the DC bias conditions now set so that VO = 4.95V, we measured VGS1, VGS2, and ID1 =ID2. Both
the calculated values and the measured values for each can be found in the table along with the
calculations below.
Calculations
Calculating VGS2, (2 equations, 2 unknowns):

(Drain tied to gate onQ3)

97.9uA
And the other equation from the circuit:

Combining the two equations:

*Note, even if I used ID3 = 100A exactly, with these parameters and the first equation, this would give
VSG2 = .95V
Calculating ID2:

*Note, if this equation was used and


Finding VGS1:

, then ID2 = 103A.

4.944V

Table 5: DC Measured and Calculated Values for vO = 4.95V


VGS1
VSG2
Measured
1.49V
2.06V
Calculated
1.733V
0.9719V

VGS2 =-VSG2
-2.06V
-0.9719V

ID1 = ID2
89.1A
119.261A

Calculation
For measured ID1 = ID2:
Measured voltage across the 51 resistor: 4.5mV

Discussion
Comparing the theoretical values to the measured values, at first glance it appears there is a
large amount of error in our measurements. Upon further consideration there is likely a large amount of
error in our calculated values as well.

% Error in value of VGS1

% Error in value of VSG2

% Error in value of ID1

Rather than taking these percent errors and considering them as the amount of error in the
measured value, we should consider them as the difference between the measured and calculated
values. This is because the calculated value is basically a measured value, just measured in a different
way. We are comparing two different measurements. The one we are calling a measurement is the one

we measured in this lab directly from the circuit. With our lab equipment, there has to be some
imprecision in the measurements. On the other hand, what we are calling a calculation here is the
measurements of the device parameters, as well as measurements from earlier in this lab being taken
and used in equations to calculate other values. The error in these other measurements used within the
calculations propagates through the calculations leaving us with error in our calculated values.
Considering that the device parameters I used throughout this lab were the ones I measured on my IC
chip because I found out at the end of the lab that the chip we had used was not my new partners
original chip, the parameters being used may not even be the correct ones. This being said, the
measured values in this case may even be closer to what the actual values should be than the calculated
values.
At this point, we have set up the DC bias conditions where we want them for all of the following
circuits. We know the DC values that we are concerned about, and from now on we are only concerned
with ac signals. In the following tasks, we take the DC bias conditions that we have set up at this point
and we apply different ac configurations to measure different ac signal gains and other ac signal
parameters.

Task4
In this task, we will use the amplifying device in the common-source configuration with the
amplifying input to the gate and output measured at the drain of the device, making the source
common. The schematic for this common-source amplifying circuit can be found below (also above in
Task 2 where we considered the DC biasing for the same circuit).
Schematic 2: Common-Source Amplifier Circuit Schematic

This schematic shows a common-source amplifier with an active load (the current mirror we
built in task 1). For this common-source amplifier, we first calculated the small signal gain using the
small signal ac model. The small signal model, as well as the calculations for the small signal gain, the
circuit input resistance, and the circuit output resistance can be found below.
The ac small signal equivalent circuit model for this common-source amplifier configuration
includes only one dependent source, because the capacitor at the source acts as an ac short to ground.
Therefore, the body and the source are both tied to ac ground, or in other words the body is tied to the

source. This means that we do not need a second dependent current source to represent the body
effect in this small signal model.
Diagram 1: Common-Source Amplifier Small Signal Model

Calculations
Finding necessary small signal parameters:

Need VDS1 for gm1:

Finding voltage gain vo/vi:


()(
)

(-

)(
((-

)
)(

)
)(

- 40.6486
Finding input resistance Rin:

Finding output resistance Rout:


After turning off the independent source, the circuit simplifies because there is no voltage dropped
across R1 and R2. The source and gate are therefore at the same potential, resulting in zero current
supplied by the dependent source.
Diagram 2: Small Signal Model with Independent Source Deactivated

Table 6: Summary of Calculated Results for Common-Source Amplifier

- 40.6486 V/V

In the lab we used the function generator to supply a 1kHz, 50mVpp triangle wave. We then used
the oscilloscope to measure both the ac input provided by the function generator ( ) and the output of
the amplifier, marked on the schematic. In the capture below, we measured on channel 2 and
on channel 1 using a 10x probe.
Oscilloscope Capture 1: Small Signal Gain for Common-Source Amplifier

Using the peak to peak amplitude measurements from the oscilloscope capture above, we can
calculate the ac small signal gain for this common-source amplifier. As we can see from the oscilloscope
capture, the output has the shape of the input, but inverted. This means that the output is the negative
of the input scaled by some amount. The calculation for the small signal gain Av follows. (As a note, the
value for is represented as a negative value since it is opposite the input. In this case there the
amplitudes of the signals are being divided and the units cancel, it does not matter that we are using the
peak to peak value versus the peak amplitude, as long as we are consistent.)
Calculation

MULTISIM SIMULATION
By modeling the common-source amplifier circuit in Multisim, we are able to compare the
previous calculated and measured to a third small signal voltage gain the simulated value. To create a
model in order to simulate the small signal voltage gain for this amplifier, first I took two PMOS
transistors and an NMOS transistor and entered all of my parameters from lab 4 into the correct
MOSFET.
The parameter in the device models built into Multisim called KP means K prime which is what
we have been calling either kn or kp. In order to enter these values correctly, I used the Kn and Kp
parameters from experiment 4, along with the width to length ratios to find kn and kp. The calculation
used to find kn and kp can be found below along with the values needed for the simulation device
models. I built the rest of the circuit around the three transistors, including all of the components from
schematic 2, the schematic for the common-source amplifier.
Example Calculation of kp:

Example Calculation of kn:

The third equation yields:


for

Schematic 3: Multisim Schematic for Common-Source Amplifier Circuitry

I first checked the DC bias conditions using the three probes that can be found on the schematic
capture. I then added a virtual Agilent function generator to supply . Using the virtual Tektronix
oscilloscope I measured on channel 1 and on channel 2.
Oscilloscope Capture 2: Multisim Virtual Capture

Using the simulated peak to peak amplitude measurements from the oscilloscope capture
above, we can calculate the simulated ac small signal gain. Again, the outputs shape is negative that of
the input. The calculation for the simulated small signal gain Av follows.

Calculation

Table 7: Small Signal Voltage Gain for Common-Source Amplifier


Calculated
Measured
- 40.6486 V/V
- 40.05 V/V

Simulated
- 53.4 V/V

DISCUSSION
In a comparison of the theoretical calculated gain to the measured gain, we can see a pretty
small amount of error for this common-source configuration.

Thus, we can see that the calculated and measured values for the common-source gain are a
pretty close match. The small amount of discrepancy in the difference between the calculated and
measured values can be attributed to some problems with both of the values. The problem with the
measured value is the imprecision in our measurement due to the old equipment. The calculated value
is based on some simplifications and approximations that help us to arrive at a small signal model and
set of equations to explain the operation of the circuit more simply. In addition, the MOSFET parameters
used in these equations are not the exact parameters for the IC chip that we used, as mentioned earlier.
The combination of these two issues does create some significant error in our calculated value.
On the other hand, in a comparison of the measured value to the theoretical value of the
common-source gain, there is a slightly larger amount of error.

While the measured value was only about 1.5% off from the calculated value, the simulated
value is a little farther away with 25% error from the measured value. Some of this error can of course
be contributed to the error in our measurement mentioned above, but since the measured and
calculated values were closer, and this simulated value is slightly farther off, there is probably more
error in the simulated value than the measured one. There are a few aspects of the simulation that may
have lead to the difference in the simulated value from the other two. One of the main problems is that
in lab we used a potentiometer to adjust VO, while in the Multisim schematic we used the resistor values

that we measured. This approach of using the resistor values from lab in the schematic was in an
attempt to closely match the circuit values from lab with the simulation.
As you can see from the probes in the Multisim schematic capture, both the current on the right
side and the voltage VO are closer to the desired values in the simulation than they were in the actual
circuit! This on the other hand makes me want to believe that the simulated value is closer to what the
actual value should be and that we carried though the same error in our calculated and measured values
that made them so close. Rethinking the calculated value, we used the measured current on the right
hand side to calculate ro1 and ro2, which we then used to calculate the gain. This means that our currents
that were a little farther from the desired value carried through our calculation offsetting both our
calculated and measured values by relatively the same amount.
With a calculated output resistance
of
, if any load was connected at the output
of this circuit, either the load would have to have a very large resistance, or the loading effect would
have to be taken into consideration. When measuring either a DC or ac voltage signal at the output of
this circuit, this output resistance would have a non-negligible effect that will cause error in a
measurement if not taken into consideration. If the circuit is imagined as a source, supplying the voltage
vO (total value), than this resistance Rout must be considered as an internal resistance. In order for Rout to
not have a significant impact on a measurement on the voltage across any load connected at the Vo, that
load must have a very large resistance.

Task5
This time, without changing the DC bias conditions, we will use the amplifying device in the
common-gate configuration with the amplifying input to the source and output measured at the drain
of the device, making the gate common. The only changes that we made to the circuit from task 4 are
moving the ac input from the gate to the source, and connecting the gate to ac ground through the
capacitor. The schematic for this common-gate amplifying circuit can be found below.
Schematic 4: Common-Gate Amplifier Circuit Schematic

This schematic shows a common-gate amplifier with an active load (the current mirror we built in task
1). For this common-gate amplifier, similar to task 4, we first calculated the small signal gain using the
small signal ac model. The small signal model, as well as the calculations for the small signal gain, the
circuit input resistance, and the circuit output resistance can be found below.

The ac small signal equivalent circuit model for this common-gate amplifier configuration
includes two dependent sources, the second dependent current source to represent the body effect in
this small signal model. We are instructed to assume a value = 0.25 for this calculation.
Diagram 3: Common-Gate Amplifier Small Signal Model

Calculations
Recalling necessary small signal parameters:

Finding voltage gain vo/vi:

Finding input resistance Rin:

Finding output resistance Rout:


After turning off the independent source, the circuit simplifies since there is no voltage drop across the
51 resistor. The source, body, and gate are then at the same potential, resulting in zero current
supplied by either of the dependent sources.
Diagram 4: Small Signal Model with Independent Source Deactivated

Table 8: Summary of Calculated Results for Common-Gate Amplifier

V/V

In the lab we used the function generator to supply a 1kHz, 30mVpp triangle wave with 50 load
impedance. Again, as we did for common-source amplifier in task 4, we used the oscilloscope to
measure both the ac input provided by the function generator ( ) and the output of the amplifier,
marked on schematic the schematic above. In the capture below, we measured on channel 1 and
on channel 2 using a 10x probe.
Oscilloscope Capture 3: Small Signal Gain for Common-Gate Amplifier

Using the peak to peak amplitude measurements from the oscilloscope capture, we can
calculate the ac small signal gain for this common-gate amplifier. From the oscilloscope capture, the
output has the same shape as the input, meaning the gain will be positive. The calculation for the small
signal gain Av follows.
Calculation

Table 9: Small Signal Voltage Gain for Common-Gate Amplifier


Calculated
Measured
50.871 V/V*
86.27 V/V
*Gain calculated with = 0.25
DISCUSSION
Comparing the calculated and measured values for the gain of this common-gate amplifier, we
find quite a bit more error than there was in the values for the common-source configuration.

There are a number of sources of this error that can be explained. First, there is definitely some
imprecision on the measured value, and by some, I mean a lot. When we were measuring the gain with
the oscilloscope, while the input stayed relatively stable, the output voltage was all over the place. The
value jumped around a lot, but the value we used was the one on the oscilloscope capture from that
moment. Outside of that exact capture, the value for Vo was jumping around between what would result
in a gain anywhere from about 50 to 90. Thus, the oscilloscope was the first problem that contributed to
the large difference between our calculated and measured values.
The next issue that contributed to the large amount of error was in our calculations. Our
calculated value is probably pretty far off from what it should be for two reasons. The first reason is that
the parameters from lab 4 are not the correct ones for the IC chip that we used in this lab, as mentioned
before. As we use these parameters in all of the calculations, the difference in the parameters from lab 4
from the actual ones for the chip we are working with propagates through the calculations and causes
our calculated value to have some error. The second reason for error in our calculations is our
assumption that = 0.25. In the next two tasks, we will measure a value for , and we will see that this
was not a great assumption. Since the gain is directly affected by the value for , our assumption of too
small a value gave us too small a calculated gain. Had we assumed a slightly larger value for , we would
have gotten a larger gain, closer to the measured value.

Table 10: Summary of Results for CS and CG Comparison

Common-Source

measured
- 40.05 V/V

Common-Gate

86.27 V/V

calculated
- 40.6486 V/V
V/V

The circuits for task 4 and task 5 are exactly the same DC-wise. The difference is in the ac part of
the schematics. This means that for both circuits we have amplifiers that are set up with the same DC
bias conditions. The difference is that the ac small signal voltage gain is set up with a common-source
amplifier in task 4 and with a common-gate amplifier in task 5. Now that we have found the small signal
model and done the calculations for each, we can compare the results.
As we got the same expression for Rout for both configurations, and the expression depended
only on the DC bias conditions, the value for Rout was the same for both the common-source and
common-gate configurations. On the other hand, our expressions and values for Rin were different for
each configuration. As we learned in class, the common-gate configuration should have a small
resistance relative to the other configurations. This appears to be true of our calculations for Rin.
Comparing the small signal voltage gains for the two different configurations, we can see trends
similar among both the measured and calculated values. While the common-source gain is negative, the
common-gate gain is positive. This is one important difference; the common-source amplifier has an
inverting gain while the common-gate amplifier does not. Another important difference to note is that
the gain for the common-gate configuration is larger in magnitude than that of the common-source
configuration. This is a result of the body effect. As we can see in the small signal model, there are now
two dependent current sources rather than only one, as there was for the common-source
configuration. As this second dependent current source supplies a current based on the value for the
body effect parameter, the larger magnitude gain for the common-gate than the common-source
configuration is directly related to the value of the body effect parameter . For this common-gate
amplifier, the body effect enhanced the small signal voltage gain.

Task6
In task 6, we used the gain equations that we found and values that we measured in the
previous two tasks to calculate values for the body transconductance (
) and the body effect
parameter () of the NMOS amplifying device at the bias conditions we established in tasks 1-3.
Table 11: Summary of Different Amplifier Configuration Measurements
CommonSource
Common-Gate
- 40.05 V/V
86.27 V/V
(-

)(

Using these two equations, we can find a way to deduce the value for from the two measured
gains. We need one equation for in terms of both the measured common-source and common-drain
values.

Calculation:
We can simplify the equation

and we know
(-

)(

);

thus,

Plugging in the measured values we get

86.21 = 40.05

Using the relation

and our value for

based on the bias conditions,

we can find the body transconductance of the NMOS device,

Table 12: Summary of Values Calculated in Task 7


-1

1.15

These calculated values for body transconductance and the body effect parameter are based on
our measurements in tasks 4 and 5. After we have completed task 7, we will compare the values we

calculate from another set of measurements and compare the methods by which we came to both sets
of values.
Task7
In task 7, we are asked to develop an alternative test circuit for directly measuring the body
effect, without changing the DC bias conditions. In order to accomplish this, we will use basically the
same circuit that we already had and again only change the ac signals. The only change that we made to
the circuit from task 4 and 5 was that we connected the input to both the gate and the source of the
amplifying device. The schematic for this common-gate amplifying circuit can be found below.
Schematic 4: Directly Measuring the Body Effect Circuit Schematic

REASONING BEHIND TASK 7 CIRCUIT:


The purpose for this test circuit is to be able to directly measure the body effect. Using the same
DC bias conditions, we have consistency for comparing our experimental result to the result we
calculated in task 6 using the common-source and common-gate configurations with the same DC bias
conditions. In order for this to be possible, we need to rearrange the ac configuration such that the
output voltage is directly proportional to the small signal body transconductance of the NMOS device,
. This test circuit therefore needs to have an ac configuration such that
and
at
the same time. As we will see in our analysis, this results in only one dependent current source in the
small signal model, which will mean that our small signal voltage gain will be directly proportional to .
This condition that
and
can be achieved by connecting both the gate and the source
terminals of the NMOS amplifying device to the same small signal voltage input and keeping the output
at the drain terminal.
The ac small signal equivalent circuit model for this configuration includes only one dependent
source. The dependent source represents the body effect in this small signal model is present, but the
other one is not. This is because we set
, so the dependent current is then also zero, making the
second dependent source equivalently an open circuit in this case.

Diagram 5: Direct Body Effect Measurement Configuration, Small Signal Model

For this circuit, similar to task 4 and 5, we first calculated the small signal gain using the small
signal ac model. The calculation for the small signal gain can be found below.
Calculation
Recalling necessary small signal parameters:

Finding voltage gain vo/vi:

Using this equation, we can take the measurement from the circuit and relate it directly to . In
the lab we used the function generator to supply a 1kHz, 30mVpp triangle wave with 50 load
impedance. We used the oscilloscope to measure both the ac input from the function generator ( )
and the output of the amplifier, marked on schematic the schematic above. In the capture below, we
measured on channel 1 and on channel 2 using a 10x probe.
Oscilloscope Capture 4: Small Signal Gain for Common-Gate Amplifier

Using the peak to peak amplitude measurements from the oscilloscope capture, we can
calculate the ac small signal gain for this amplifier configuration. From the oscilloscope capture, the
output has the same shape as the input, meaning the gain will be positive. The calculation for the small
signal gain Av follows.
Calculations

Using the equation found above, this voltage gain can be used to find :

An important note, looking at the equation with the * at the end, we can see the direct
dependence of the gain on the value of . Since the term
is very small, the gain equation could be
approximated as

, from which we can see the gains direct

proportionality to .
Table 13: Summary of Body Effect Results
Task 6
Task 7

1.15
1.12

0.3633 k-1
0.35 k-1

DISCUSSION
In tasks 6 and 7, we used two different approaches to come to the same results values for
both the for the body transconductance (
) and the body effect parameter () of the NMOS
amplifying device at the bias conditions we established in tasks 1-3. First, in task 6, we used our
measurements of the common-source and common-gate small signal voltage gains from task 4 and task
5 respectively, along with the equations we found for the corresponding gains. Using a combination of
the gain equations from the common-source and common-gate small signal models, we were able to
plug in our two measured gain values and determine a value for the body effect parameter .
Next, in task 7, we changed the ac configuration of our circuit to a form from which we could
directly extract a value for from only one measurement of the gain. We connected the ac input to both
the gate and the source and measured the gain. Using the small signal model for this circuit, we found
an equation in which the gain is directly proportional to . Using our measurement of the gain we
directly calculated a value for . In both tasks 6 and 7, after we found , we used our value for to
calculate a value for
for the NMOS amplifying device using the
that we found using our DC bias
conditions. (This is one of the reasons why it was important that our design for our test circuit to directly
measure had the same DC bias conditions as the other configurations throughout this lab.)
Comparing these two methods for obtaining a value for , the second approach taken in task 7
was the preferable approach from the standpoints of both measurement accuracy and simplicity. The
approach in task 7 was preferable for measurement accuracy because only one measurement is taken.
For the approach in task 6, we took two separate measurements (in our case during two separate
weeks,) on two different circuit configurations in order to determine a value for . With the better
approach in task 7, we only take one measurement on one circuit configuration and using this one
measurement we are able to determine a value for . From the standpoint of measurement accuracy,
taking less separate measurements results in less chance for error.

Even though we are asked to actually think of a configuration to use for task 7 and given the
configurations used for task 6, from a standpoint of simplicity, the approach taken in task 7 is the
simpler one. Once we have an understanding of the configuration that we need to use, taking one
measurement and using one equation to find a value for is simpler than the approach taken in task 6.
In a comparison of the values for found from both approaches, it is apparent that the
approach taken does not make a huge difference in the calculated value. (As a note, a comparison of the
values for from both approaches suffices since the values for
was calculated in the same way.
Multiplying the corresponding by the value of
, which is the same for both as it only depends on
the DC bias conditions which are unchanged, the value for
depends only on the value of .)

The values for found with both approaches were within


of each other. As mentioned
above, the reason for this difference is likely an effect of the two different approaches used to come by
the values. Taking two separate measurements on two circuits configured in different ways, on two
separate lab days, definitely creates the possibility for some error. As the approach taken in task 7 was
the more simplistic and better from the standpoint of measurement accuracy, the value for found in
task 7 is probably slightly better than that found from the approach in task 6.
SUMMARY AND CONCLUSIONS
In summary, in the first week of this experiment we created a current mirror that would act as
an active load for each of the circuits throughout the rest of the lab. Then, we set up an NMOS transistor
as an amplifying device. We used a resistor and a potentiometer to make sure the MOSFETS were all
operating in the saturation region and to set the DC bias conditions for all of the circuits in this
experiment. We measured the small signal voltage gain of the amplifier in the common-source (CS)
configuration and found the associated small signal model and equations. In the second week of the
experiment, we measured the small signal voltage gain for the common-gate (CG) configuration and
again found the associated small signal model and equations.
Next, we used both the CS and CG measured gains and small signal model gain equations to
extract a value for the body effect parameter . In the last part of the experiment, we changed the
configuration of our circuit so that with only one measurement we could find a small signal model and
an equation that would produce a value for .
In conclusion, we found in the experimental results that the configuration characteristics do in
fact agree with what we learned in class. We found from the characteristics of both the calculations and
the measurements that the common-source small signal gain is negative, while the common-gate small
signal gain is positive. We also found that the magnitudes of the small signal voltage gains were both
greater than 1, the gain of the common-gate configuration being slightly larger than that of the
common-source configuration due to the body effect. We also saw that relative to that of the CS
configuration, the Rin for the CG configuration is much smaller. The neat part of this experiment was
getting to physically see all the aspects of the different amplifier configurations that we were simply told
about in lecture.