15MVD0096 Testing Assignment 2

ECE-508 VLSI TESTING &
TESTABILITY
ASSIGNMENT NO. 02
Submitted By: -
TEJAS P. KOSHATWAR
(Reg. No. 15MVD0096)
M. Tech VLSI Design

2015-16
SCHOOL OF ELECTRONICS ENGINEERING

VIT UNIVERSITY
VELLORE-632014, TAMILNADU, INDIA
ASSIGNMENT NO. 02
Objective:- To generate test pattern and simulate respective design.
Aim:1. Generate test patterns for various iscas85 combination circuit by exploring various options
2.
3.
4.
5.
provided in the manual. Explore the concepts leaned in theory and tabulate the summary of
results. Provide the inference.
Explore various option provided in the fsim and summary must be tabulated and provide the
inference.
Repeat the Task 1 and Task 2 for scan inserted sequential circuits (iscas89_scan)
Use Hope (sequential fault simulator) to simulate sequential circuits (ISCAS89) and summary
must be tabulated and provide the inference
Now consider the circuit which you have considered for assignment 1. Describe the same in
bench format netlist. Perform the task 1 and 2.
Description :Atalanta is Automatic Test Pattern Generator for stuck-at faults in combinational circuits.
Command format is
SYNOPSIS: atalanta [options] circuit_file [> outfile]
OPTIONS: Several options are available for atalanta.If an option is not specified, the default
value is used.
-A :- Diagnostic mode Atalanta derives all test patterns for each fault. In this option, all
unspecified inputs are left unknown, and fault simulation is not performed.
(default: Normal test generation mode)
-D n :- Diagnostic mode Atalanta derives n test patterns for each fault. In this option, all
unspecified inputs are left unknown, and fault simulation is not performed. If both -A and -D
option are specified, -D option is applied. (default: Normal test generation mode)
-b n:- The number of maximum backtrackings for the FAN algorithm phase 1. (default: -b 10)
-B n:- If -B n (n>0) option is specified, atalanta generates test patterns in two phases. In phase 1,
static unique path sensitization is employed. If the test generation for a target fault is aborted in
phase 1, the test generation is tried in phase 2. In phase 2, dynamic unique path sensitization is
employed. If n=0, phase 2 is not performed. If n>0, phase 2 test generation is performed with the
backtrack limit of n.
(default: -B 0, i.e., phase 2 is not performed.)
-f fn:- Faults are read from the file fn. This option is available only for ISCAS89 netlist format.
(default: faults are generated internally.)
-h f
Displays the fault list format
-h g
Displays the on-line user's guide.
-h n
Displays an example netlist format.
-h t
Displays an example test pattern file.
-h a
Displays the entire on-line manual file. (default: no manual is displayed)
-H
HOPE, which is a parallel fault fault simulator, is employed for fault simulation. In this
option, three logic values (0, 1 and X), instead of two logic values (0 and 1), are employed. Due
to the embedding of the unknown logic value and the paralle fault fault simulation algorithm, the
test generation time is slower than the default mode.)
(default: FSIM, which is a parallel pattern fault simulator is employed, and two logic values are
used.)
-l fn
Log file is created.(default: no logfile is created)
-L
Static learning is performed. (default: no learning)
-c n
Atalanta compacts test patterns using two different methods: reverse order compaction
and shuffling compaction. First, test patterns are applied in the reverse order and fault simulated
(reverse order compaction). Second, test patterns are shuffled randomly and fault simulated
(shuffling compaction). During the fault simulations, all the test patterns which do not detect a
new fault are eliminated. The option -c n specifies the limit of shuffling compaction. If n>0,
shuffling compaction is terminated if n consecutive shuffling do not drop a test pattern. If n=0,
shuffling compaction is not included and compaction is done only by the reverse order fault
simulation. (default: -c 2)
-N
Test compaction is not performed. (default: -c 2)
-r n
Random Pattern Testing (RPT) Session is included before deterministic test pattern
generation session. The RPT session stops if any n consecutive packets of 32 random patterns do
not detect any new fault. If n=0, the RPT session is not included. (default: -r 16)
-s n
Initial seed for the random number generator (random()).
If n=0, the initial seed is the current time. (default: -s 0)

-t fn Test patterns are put into the file "fn".(default: *.test for a circuit named *.bench)
-u
Atalanta prints out all aborted fauts in a file. The name of this file is <ckt>.ufaults. In
default, all identified redundant faults are not included in the file, but you can include them using
the option -v. Note that atalanta does not update a fault file if on already exists in the run
directory. This fault list file can be directly read by atalanta or hope. (default: no file is created)
-U fn The same as -u, but atalanta writes aborted faults to the given file name. (default: no file
is created)
-v
Atalanta prints out all identified redundant faults as well aborted fauts in a file. If -U fn
option is not given, Atalanta prints out the faults in a default file, <ckt>.ufaults. (default: no file
is created)
-Z
Atalanta derives one test pattern for each fault. In this option, no fault simulation is
performed during the entire test generation (including random pattern test generation session,
deterministic test generation session and test compaction session). All unspecified inputs are left
unknown.
-0, -1, -X, -R: During test generation, some inputs can be unspecified. Atalanta provides various
options to set these unspecified inputs into a certain value. The options are described below.
-0
Unspecified inputs are set to logic 0.
-1
Unspecified inputs are set to logic 1.
-R
Unspecified inputs are set to logic 0 or logic 1 randomly.
-X
Unspecified inputs are left to unknown (X).
(default: -R)
OUTPUTS: In default mode, one file is created. The summary of the test pattern generation is
reported to the standard output and the test patterns are stored in the circuit_name.test file. If -l
option is specified, atalanta creates a log file. The log file contains more detailed information
on the test pattern generation result.
Thus , as per above options various commands are applied to the circuit and result is tabulated as
follows:TASK ONE
Apply various option to same circuit file here circuit consider is c3540.bench
Command
atalanta -r
16 -R -s 0
-b 10 -B 20
-c
2
-t
c3540.test
c3540.benc
h
atalanta -r
16 -R -s 0
-b 10 -B 20
-c
0
-t
c3540.test
c3540.benc
h
atalanta -r
16 -R -s 0
-b 10 -B 20
-N
-t
c3540.test
c3540.benc
h
atalanta -r
16 -R -s 0
-b 10 -B 20
-Z
-t
c3540.test
c3540.benc
h
Test
pattern
Genratio
n mode
Test pattern
Compaction
mode
Number
of
shuffles
Pattern
Generated
before
compaction
Pattern
Generated
after
compaction
Fault
coverage
Number
of
collapsed
faults
RPT +
DTPG +
TC
REVERSE
+SHUFFLE
14
252
146
96.004%
3428
RPT +
DTPG +
TC
REVERSE
245
96.004%
3428
RPT +
DTPG +
TC
NONE
NONE
254
96.004%
3428
DTPG +
TC
NONE
NONE
3288
95.916%
3428
254
3288
176
1) For given Combinational Circuit containing 3 PIs, 2 POs, 5 FOs. Each

circuit has at least 1 AND GATE, OR GATE, NOR GATE, NAND GATE,
INVERTER, write the circuit in bench format.
Generate the Test pattern using atalanta tool and simulate in fsim.
1) Write a Bench code of Combinational Circuit:
Bench file for design:
#ckt
#4 inputs
#2 outputs
#10 gates
INPUT(A)
INPUT(B)
INPUT(C)
INPUT(D)
OUTPUT(Y)
OUTPUT(Z)
E = NOT(A)
F = AND(A,B)
G = NAND(B,C)
H = OR(C,D)
J = NOR(F,G)
K = AND(G,H)
M = NOT(J)
Y = AND(E,M)
Z = OR(K,W)
W = NOT(M)
2) Generated Test using atalanta tool:

1:
2:
3:
4:
5:
6:
0011
0110
0100
1111
0001
1010
11
01
10
00
11
01
3) Log Report:
*******************************************************
*
*
*
Welcome to fsim (version 1.2)
*
*
*
*
Dong S. Ha (ha@vt.edu)
*
*
Web: http://www.ee.vt.edu/ha
*
* Virginia Polytechnic Institute & State University *
*
*
*******************************************************
******
SUMMARY OF FAULT SIMULATION RESULTS
******
1. Circuit structure
Name of the circuit
: ckt.bench
Number of primary inputs
: 4
Number of primary outputs
: 2
Number of gates
: 10
Level of the circuit
: 5
2. Simulation parameters
Simulation mode
: file (ckt.test)
3. Simulation results
Number of test patterns applied
Fault coverage
Number of collapsed faults
Number of detected faults
Number of undetected faults
:
:
:
:
:
4. Memory used
: 40665 Kbytes
5. CPU time
Initialization
Fault simulation
Total
: 0.000 secs
: 0.000 secs
: 0.000 secs
6
96.429 %
28
27
1
nference:
Command:
1. atalanta assi.test assi.bench >assi.txt
This command will generate the test patterns for the input bench file. And the
results will be store in the output text file.
2. fsim -t assi.test -l assi.log assi.bench
This command will apply generated test patterns to the input bench file and it
will do fault simulation. Log file will show the fault simulation results.
3.
Simulation results:
Fault coverage
:
:
:
:
:
6
96.429 %
28
27
1
2) In ISCAS85 use 5 different bench file of combinational and observe the

variation in generated test pattern results using different commands of
atalanta and fsim.
1. C17
a) Generated Test using atalanta tool:
test
test
test
test
test
test
1:
2:
3:
4:
5:
6:
10000
00001
01111
01010
11110
11100
00
01
00
11
10
11
7
3
5
5
1
1
faults
faults
faults
faults
faults
faults
detected
detected
detected
detected
detected
detected
b)
Log Report:
******
Name of the circuit
: c17
: 5
: 2
Number of gates
: 6
: 3
******
Simulation mode
: file (c17.test)
Fault coverage
:
:
:
:
:
4. Memory used
: 10305 Kbytes
5. CPU time
Initialization
Fault simulation
Total
: 0.000 secs
: 0.000 secs
: 0.000 secs
c) Inference
Simulation results
Fault coverage
2. C432
6
100.000 %
22
22
0
:6
: 100.000 %
: 22
: 22
:0
d) Generated Test using atalanta tool:

test
1:
detected
test
2:
detected
test
3:
detected
test
4:
detected
test
5:
detected
101100011101001101011010000011100000 1011001
72 faults
100010111001001101010010110000001000 1111010
27 faults
011100100000101010110110000101111110 1010000
24 faults
000000110000101110110111000110110001 0011011
54 faults
001100010100110010100101011111011100 1111011
13 faults
test
6: 001111001101111110000110001001111101 1101110
27 faults
detected
test
7: 001001100110110111110010010111010100 1101101
36 faults
detected
test
8: 100001101110111001111110000110110011 1011101
20
faults
continue
e)
Log Report:
******
Name of the circuit
: c432
: 36
: 7
Number of gates
: 160
: 17
f)
******
Simulation mode
: file (c432.test)
Fault coverage
:
:
:
:
:
4. Memory used
: 12148 Kbytes
5. CPU time
Initialization
Fault simulation
Total
: 0.000 secs
: 0.000 secs
: 0.000 secs
48
99.237 %
524
520
4
List of undetected faults:

9 /1
12->7 /1
13->6 /0
6 /0
1 /0
g) Inference
Fault coverage
: 48
: 99.237 %
: 524
: 520
: 4
3. C1908
h) Generated Test using atalanta tool:
test
1: 100011110001000100001110111000110
506 faults detected
test
2: 110011011110011101001111010011010
225 faults detected
test
3: 000101100110000110100000100110110
157 faults detected
test
4: 100111011100100011000001011001111
81 faults detected
test
5: 110000101010000010001000010110110
90 faults detected
test
6: 001100111110100010101101111011000
67 faults detected
continue
i)
j)
1000001111101100111010001
1100111110111001000000011
0001101011001000010000000
1001100110110010110110111
1100000011011000101110111
0011100001111010010111110
Log Report:
Name of the circuit
Number of gates
:
:
:
:
:
Simulation mode
: file (c1908.test)
Fault coverage
:
:
:
:
:
4. Memory used
: 41050 Kbytes
5. CPU time
Initialization
Fault simulation
Tot
: 0.000 secs
: 0.000 secs
List of undetected faults:
c1908
33
25
880
40
119
99.521 %
1879
1870
9
99->2800 /1
1163 /1
1167 /1
313->2384 /1
313->2384 /1
608->898 /1
612->897 /1
303->926 /1
338->926 /1
k) Inference
Fault coverage
:
:
:
:
:
119
99.521 %
1879
1870
9
4. C1908
l)
Generated Test using atalanta tool:

test
1:
01011110101010111111110111111011111111001101000000101111011111010101
11010101000010111010001011111110011101000001010101001100110001010100
10111101101101110001101011111110101001011101011011011110110110110001
00000000000000011110101001010
01010011001100010101001011110110110111000110101111111010100101110101
10110111111110000000001110110100111111001111110111111111110011000110
0001 612 faults detected
test
2:
11000110001000101011101011000101100101010110001110000110110011000000
10100100011100000110110010010110010001001001000101111110001111011001
00011010111111010001000010001001011010010000111011101101000100111011
10010110010010010100000010000
01011111100011110110010001101011111101000100001000100101101001000011
10111011000110000011100011001110110011001111110100111100010000101110
0001 280 faults detected
test
3:
00101111101011111101001100100110111100110010100100110001000111111111
10001101000101010111110111101011101000101001001010111100100000110101
10100000010000101000011010000011111110100000110011110100010010100101
10011000000110111001111111110
10101111001000001101011010000001000010100001101000001111111010000011
00111101000000001100110011000110111100011110011111001111110100101110
0001 222
continue
m) Log Report:
Name of the circuit
Number of gates
:
:
:
:
:
Simulation mode
: file (c2670.test)
Fault coverage
:
:
:
:
:
4. Memory used
: 41779 Kbytes
5. CPU time
Initialization
Fault simulation
Total
: 0.000 secs
: 0.000 secs
: 0.000 secs
n) List of undetected faults:

3870->3876
3875 /0
3870 /1
3859->3869
3864->3869
3869 /0
3864 /1
3859 /0
3858 /0
3857 /0
3843->3852
3840->3852
3852 /0
3436 /1
3507 /1
3836 /1
3418 /1
3488 /1
3834 /1
2403 /1
3634 /1
2656 /1
3661 /1
2376 /1
3599 /1
o) Inference
/1
/1
/1
/1
/1
c2670
233
140
1193
32
113
95.741 %
2747
2630
117

Fault coverage
:
:
:
:
: 113
95.741 %
2747
2630
117
3) In ISCAS89 use 5 different bench file for sequential circuit and observe
the variation in generated test pattern results using different commands
of hope.
1. S298
a) Summary;
******
SUMMARY OF SIMULATION RESULTS
Name of circuit
Number of combinational gates
Number of flip-flops
******
:
:
:
:
:
:
s298
3
6
119
14
9
2. Simulator input parameters

Simulation mode
Initial random number generator seed
: random
: 1458534134
Fault coverage
:
:
:
:
:
4. Memory used
: 21053 Kbytes
5. CPU time
Initialization
Fault simulation
Total
: 0.000 secs
: 0.000 secs
: 0.000 secs
224
0.971 %
103
1
102
b) List of undetected faults:

1. G96->G95 /1
2. G83 /1
3. G108->G97 /1
4. G93 /1
5. G95 /0
6. G13->G83 /0
7. G96->G85 /0
8. G91->G85 /0
9. G79 /1
10. G108->G116 /1
11. G14->G74 /1 .
c) Fault Detection:
test
test
test
test
test
test
test
test
test
test
1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
001
001
001
111
001
110
001
100
101
000
xxxxxx
xxxxxx
xxxxxx
xxxxxx
xxxxxx
100001
100001
100001
100001
100001
0
0
0
0
0
0
0
0
0
0
faults
faults
faults
faults
faults
faults
faults
faults
faults
faults
detected
detected
detected
detected
detected
detected
detected
detected
detected
detected
2. S382
d) Summary;
******
Name of circuit
******
:
:
:
:
:
:
s382
3
6
158
21
9

Simulation mode
: random
: 1458533506
Fault coverage
:
:
:
:
:
224
0.000 %
350
0
350
4. Memory used
: 20185 Kbytes
5. CPU time
Initialization
Fault simulation
Total
: 0.000 secs
: 0.000 secs
: 0.000 secs
e) List of undetected faults:

1.
2.
3.
4.
5.
6.
7.
8.
TCOMBVNODE4VOR2NF /1
TCOMBVNODE4VOR1NF /1
TCOMBVNQA->TCOMBVNODE3 /1
TCOMBVNQB->TCOMBVNODE3 /1
CLRB->TCOMBVNODE4VOR2NF /0 potentially detected
C3_Q2->TCOMBVNODE4VOR2NF /0
CLRB->TCOMBVNODE4VOR1NF /0 potentially detected
TCOMBVNFM->TCOMBVNODE4VOR1NF /0
f) Fault Detection:
test
test
test
test
test
test
test
test
test
test
1:
2:
3:
4:
5:
6:
7:
8:
9:
10:
110
101
110
101
001
010
110
011
100
011
xxxxxx
xxxxxx
011000
011000
011000
011000
011000
011000
011000
011000
0
0
0
0
0
0
0
0
0
0
faults
faults
faults
faults
faults
faults
faults
faults
faults
faults
detected
detected
detected
detected
detected
detected
detected
detected
detected
detected
3. S400
g) Summary;
******
Name of circuit
******
:
:
:
:
:
:
s400
3
6
162
21
9

Simulation mode
: random
: 1458533533
Fault coverage
: 224
: 0.000 %
: 373

: 0
: 373
4. Memory used
: 34832 Kbytes
5. CPU time
Initialization
Fault simulation
Total
: 0.000 secs
: 0.000 secs
: 0.000 secs
h) List of undetected faults:

1. TCOMB_RA1VOR1NF /1
2. TCOMB_RA1 /1
3. OLATCH_FEL->TCOMB_RA1VOR2NF /0
4. C3_Q3->TCOMB_RA1VOR2NF /0
6. OLATCH_FEL->TCOMB_RA1VOR1NF /0
h) Fault Detection:
test
1: 011 xxxxxx
test
2: 010 100001
test
3: 101 100001
test
4: 100 100001
test
5: 100 100001
test
6: 000 100001
test
7: 001 100001
test
8: 101 100001
test
9: 001 100001
test
10: 100 100001
0 faults detected
faults detected
faults detected
faults detected
faults detected
faults detected
faults detected
faults detected
faults detected
faults detected
0
0
0
0
0
0
0
0
0
4. S526
i)
Summary;
******
Name of circuit
******
:
:
:
:
:
:
s526
3
6
193
21
9

Simulation mode
: random
: 1458533586
: 224
Fault coverage
:
:
:
:
0.000 %
507
0
507
4. Memory used
: 14643 Kbytes
5. CPU time
Initialization
Fault simulation
Total
: 0.000 secs
: 0.017 secs
: 0.017 secs
j) List of undetected faults:

1.
2.
3.
4.
5.
6.
7.
8.
G12->G175 /1 potentially detected

G177->G176 /1
G164 /1
G165 /1
G166 /1
G189->G178 /1
G178 /0
G173 /1
k) Fault Detection:
test
1: 001
test
2: 111
test
3: 000
test
4: 010
test
5: 000
test
6: 101
test
7: 101
test
8: 111
test
9: 010
test
10: 111
xxxxxx
xxxxxx
xxxxxx
100001
100001
100001
100001
100001
100001
100001
0
0
0
0
0
0
0
0
0
0
faults
faults
faults
faults
faults
faults
faults
faults
faults
faults
detected
detected
detected
detected
detected
detected
detected
detected
detected
detected
4) In iscas89_scan use 5 different scan file of sequential circuit and

observe the variation in generated test pattern results using different
commands of atalanta and fsim.
1)
S27
a)

test
test
test
1: 0110010 0010
2: 1101010 1101
3: 0000000 1000
10 faults detected
12 faults detected
5 faults detected
test
test
test
b)
4: 1011000 0010
5: 0110110 1000
6: 1001101 1101
3 faults detected
1 faults detected
1 faults detected
Log Report:
Name of the circuit
Number of gates
:
:
:
:
:
s27
7
4
11
6
Simulation mode
: file (s27.test)
Fault coverage
:
:
:
:
:
4. Memory used
: 35467 Kbytes
5. CPU time
Initialization
Fault simulation
Total
: 0.000 secs
: 0.000 secs
: 0.000 secs
6
100.000 %
32
32
0
c) List of undetected faults: Null
d) Inference:
Fault coverage
:6
: 100.000 %
: 32
: 32
:0
2) S208
e)

test
1: 0110101111111111110 0000000000
45 faults detected
test
test
test
test
test
test
test
test
test
f)
2:
3:
4:
5:
6:
7:
8:
9:
10:
1011000101000000000
1011100000001110100
0000100001111110111
1010101001110100110
1010010010111110000
1010010011000001000
1000110000010001010
0011001100110110001
0001111110111010010
1000000000
0100000000
0000100000
1100001100
0001001000
1000001000
1100000000
0000000000
0000000000
Log Report:
Name of the circuit
Number of gates
31
21
19
12
10
8
3
7
5
:
:
:
:
:
faults
faults
faults
faults
faults
faults
faults
faults
faults
detected
detected
detected
detected
detected
detected
detected
detected
detected
s208
19
10
96
14
Simulation mode
: file (s208.test)
Fault coverage
:
:
:
:
:
4. Memory used
: 32673 Kbytes
5. CPU time
Initialization
Fault simulation
Total
: 0.000 secs
: 0.000 secs
: 0.000 secs
32
100.000 %
215
215
0
g) List of undetected faults: Null
h) Inference:
Fault coverage
3) S282
i)
: 32
: 100.000 %
: 215
: 215
: 0
test
faults
test
faults
test
faults
test
faults
test
faults
j)
1: 010101010010101010100011
detected
2: 110111010101001111100111
detected
3: 001010000000100000110101
detected
4: 010111011000001001010011
detected
5: 000011000000100110101011
detected
100101000000000100000110000
96
010101100000001000000110100
45
000011000101000000000110000
17
001101010101000100110110010
40
000111010101000000000110000
17
Log Report:
Name of the circuit
Number of gates
:
:
:
:
:
s382
24
27
158
9
Simulation mode
: file (s382.test)
Fault coverage
:
:
:
:
:
4. Memory used
: 15159 Kbytes
5. CPU time
Initialization
Fault simulation
Total
: 0.000 secs
: 0.000 secs
: 0.000 secs
k) List of undetected faults: Null
l) Inference:
: 30
Fault coverage
: 100.000 %
: 399
: 399
:0
4) S349
m)
30
100.000 %
399
399
0
test
faults
test
faults
test
faults
test
faults
test
faults
n)
1: 101010101110110010010110
detected
2: 000111001111011110000100
detected
3: 001001011111011100011111
detected
4: 110010011101000000100111
detected
5: 000011000000001100100110
detected
00011011001101111100000100
69
01000011101000100110001100
68
01000111011110101110001000
18
11111110101111111100000010
27
01100110100011001100010111
38
Log Report:
Name of the circuit
Number of gates
:
:
:
:
:
s349
24
26
170
20
Simulation mode
: file (s349.test)
Fault coverage
:
:
:
:
:
4. Memory used
: 40665 Kbytes
5. CPU time
Initialization
Fault simulation
Total
: 0.000 secs
: 0.000 secs
: 0.000 secs
o) List of undetected faults:

CNTVG1VG2VOR1NF /1
READY->CNTVG3VD1 /0
p) Inference
Fault coverage
: 25
: 99.429 %
: 350
25
99.429 %
350
348
2

: 348
:2
Final Conclusion:
For combinational circuit fsim is used fault simulation and atalanta for
test pattern generation.
For sequential circuit hope is used for fault simulation and atalanta for
test pattern generation.
Various test patterns are generated using different different options in
atalanta and percentage of fault coverage is studied.
Externally faults are inserted in combinational circuit and increased in
fault coverage is observed.

15MVD0096 Testing Assignment 2

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15MVD0096 Testing Assignment 2

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ECE-508 VLSI TESTING &

M. Tech VLSI Design

SCHOOL OF ELECTRONICS ENGINEERING

Displays the fault list format

Displays the on-line user's guide.

Displays an example netlist format.

Displays an example test pattern file.

Displays the entire on-line manual file. (default: no manual is displayed)

Log file is created.(default: no logfile is created)

Static learning is performed. (default: no learning)

Test compaction is not performed. (default: -c 2)

Initial seed for the random number generator (random()).

If n=0, the initial seed is the current time. (default: -s 0)

Unspecified inputs are set to logic 0.

Unspecified inputs are set to logic 1.

Unspecified inputs are set to logic 0 or logic 1 randomly.

Unspecified inputs are left to unknown (X).

1) For given Combinational Circuit containing 3 PIs, 2 POs, 5 FOs. Each

1) Write a Bench code of Combinational Circuit:

Bench file for design:

2) Generated Test using atalanta tool:

2) In ISCAS85 use 5 different bench file of combinational and observe the

d) Generated Test using atalanta tool:

List of undetected faults:

List of undetected faults:

Generated Test using atalanta tool:

n) List of undetected faults:

Number of test patterns applied

2. Simulator input parameters

b) List of undetected faults:

2. Simulator input parameters

e) List of undetected faults:

2. Simulator input parameters

Number of detected faults

h) List of undetected faults:

2. Simulator input parameters

j) List of undetected faults:

G12->G175 /1 potentially detected

4) In iscas89_scan use 5 different scan file of sequential circuit and

Generated Test using atalanta tool:

c) List of undetected faults: Null

Generated Test using atalanta tool:

g) List of undetected faults: Null

Generated Test using atalanta tool:

k) List of undetected faults: Null

Generated Test using atalanta tool:

o) List of undetected faults:

Number of detected faults

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