SCHOOL OF ELECTRONICS ENGINEERING

DEPARTMENT OF MICRO AND NANOELECTRONICS

M.TECH. VLSI DESIGN
MID-TERM EXAMINATION - APRIL 2016
VLSI TESTING AND TESTABILITY
ANSWER ALL QUESTIONS
Time: 1 Hours.

1.

Max. Marks: 50

Show that the two faults a s-a-0 and c s-a-1 are equivalent in the circuit of Figure 1.

(5)

Figure 1
2.

(10)
Soln:

3.

Solution:

(10)

4.

5.

(a) We know that transistor stuck-open faults can turn a combinational CMOS gate into a (10)
sequential one. Can a stuck-open fault occur to nMOS gates, i.e., can a stuck-open
transistor or line in a combinational nMOS gate force it to possess a sequential behavior?
Give reasons.
(b) Give a switch-level implementation of the 2-input XNOR gate, and list all possible
transistor stuck-open faults which need two-pattern tests. Find the respective tests.
a) What is the number of inputs to the combinational block C1? 200
(15)
b) What is the number of outputs of the combinational block C1? 150
c) To scan set S1=1, S2=1 B=0.
Length of the scan path is 200 + 72 + 24 + 150 + 20 = 466
Hence we need 466 cycles to initialize all registers.
d) We need to read out registers R5, R2 and R3. These can be read out by
setting
S1=1, S2=1, B=0.
Cycles needed 24 + 150 + 20 = 194
e) What is the minimum number of clock cycles to test only the block C1 and what
should be the values of the control signals S1, S2, B.
We will configure scan such that C3 is bypassed. Thus during scan S1=1, B=1,
S2=x. During test application S1=0, S2=x, B=x.
First test will be loaded using 200 cycles. Subsequent to that we will read the
result and at the same time load the test. This will require max{200, 150+20} =
200 cycles.
Finally we will read the result out using 150+20 = 170 cycles.
Hence total cycles: 200+1 + (200+1)x109 + 170 = 22280 cycles.

f) What is the minimum number of clock cycles to test only the block C2 and what
should be the values of the control signals S1, S2, B.
For loading and application the control signal will be set same as above, i.e. during
scan S1=1, B=1, S2=x and during test application S1=0, S2=x, B=x.
Loading the first test will require 200+150 cycles. Reading the result and loading
the test same time will require max{350, 20} = 350 cycles.
Hence total cycles: 350+1 + (350+1)x24 + 20 = 351x25+20 = 8795 cycles
g) What is the minimum number of clock cycles to test the block C1 and C2 and what
should be the values of the control signals S1, S2, B. Note this is less than the sum
of the clock cycles to test C1 alone and C2 alone.

During scan S1=1, B=1, S2=x and during test application S1=0, S2=x, B=x
We will start testing both C1 and C2, when C2 is tested, we will continue testing
C1.
Number of cycles: 350+1 (350+1)x24 + (200+1)x85 + 170 = 26030
h) What is the minimum number of clock cycles to test only the block C3 and what
should be the values of the control signals S1, S2, B. Note to test this block you will
have to use BIST and 10 scan vectors and before invoking BIST mode for this, R4
and R5 must be initialized.
The basic idea is to initialize R4 and R5 using S1=1, S2=1, B=0 using 200+72+24
= 296 cycles.
Next, start BIST by setting S1=x, S2=0, B=1. This is done for 55000 cycles.
Following this result of BIST are read and another 10 tests are applied. For this
during scan S1=1, S2=1, B=0 and for application S1=x S2=0 B=0.
Number of cycles for this last part is (max{272, 194} + 1)x10 + 194.
Total test time is 58220.

i) What is the minimum test application time to test all three combinational blocks.
Calculate the total number of test cycles.
The best strategy is to start BIST as early as possible. This requires the first two
steps of the method for testing C3 - which will require 55296 cycles.
Doing a simple back of the envelop calculation you will find that during the 55000
BIST cycles when C3 is being BISTed, C1 and C2 can be fully tested. In fact we
will have to wait for the BIST to finish. Thus we will still need to apply another
10 vectors to test C2. Thus the total cycles will be same as for the case to test
C2, i.e. 58220.