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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 56, NO. 5, MAY 2009
I. I NTRODUCTION
Manuscript received October 31, 2008; revised January 20, 2009. Current
version published May 15, 2009. This work was supported in part by the
National Science Council, Taiwan, under Grant NSC 97-2220-E-110-006. This
paper was recommended by Associate Editor A.-Y. Wu.
The authors are with the Department of Computer Science and Engineering, National Sun Yat-sen University, Kaohsiung 80424, Taiwan (e-mail:
srkuang@cse.nsysu.edu.tw).
Digital Object Identifier 10.1109/TCSII.2009.2019334
Fig. 1.
KUANG et al.: MODIFIED BOOTH MULTIPLIERS WITH A REGULAR PARTIAL PRODUCT ARRAY
405
TABLE I
MBE TABLE
n2
ai 2i
i=0
B = bn1 2n1 +
n2
bi 2i .
(1)
i=0
n/21
B=
i=0
n/21
2i
mi 2
(2)
i=0
(3)
(4)
406
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 56, NO. 5, MAY 2009
TABLE III
TRUTH TABLE FOR NEW SIGN EXTENSION BITS
Fig. 4.
(8)
1 = s0 di = 2
(9)
0 = s0 di .
According to (3) and (4), i0 and ci can be produced by one
NOR gate and one AOI gate, respectively. Moreover, they are
generated no later than other partial product bits.
To further remove the additional partial product row PPn/2
[i.e., PP4 in Fig. 1(b)], we combine the ci for i = n/2 1 with
the partial product bit pi1 to produce a new partial product
bit i1 and a new carry di . Then, the carry di can be incorporated into the sign extension bits of PP0 . However, if i1 and
di are produced by adding ci and pi1 , their arrival delays will
probably be larger than other partial product bits. Therefore,
we directly produce i1 and di for i = n/2 1 from A, B, and
the outputs of the Booth encoder
(i.e., negi , twoi , and onei ), as
shown in Table II, where
and denote the Exclusive-OR and
Exclusive-NOR operations, respectively. The logic expressions
of i1 and di can be written as
i1 = onei + twoi a0 = (onei + ) (twoi + a0 )
(5)
=
a1 ,
a1 ,
if a0 b2i+1 = 0
otherwise.
(7)
(10)
(11)
(12)
KUANG et al.: MODIFIED BOOTH MULTIPLIERS WITH A REGULAR PARTIAL PRODUCT ARRAY
407
TABLE IV
EXPERIMENTAL RESULTS OF MBE MULTIPLIERS
Fig. 5.
where
= (b2n+1 b2n a0 + b2n+1 b2n )
(13)
= b2n+1 a1 a0 + b2n+1 a1 .
(14)
408
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 56, NO. 5, MAY 2009