Ref35 PDF

Mixed-Signal Testing &
DfT Techniques
Outline
z
z
z
z
z
May, 2002
Mixed-Signal Test Problems

Mixed-Signal DfT Techniques
IEEE Standard for a Mixed-Signal Test Bus
DSP-Based Mixed-Signal Testing
DSP-Based Mixed-Signal SoC Self-Testing
J.L. Huang, EE/GIEE, NTU
Mixed-Signal Test Problems
The Role of Testing

z
The role of testing is to detect whether

something went wrong.
Diagnosis, on the other hand, tries to
determine exactly what went wrong & where
the process has to be altered.
Test objectives
Design verification
Ensure product quality
Diagnosis & repair
May, 2002
What are we after?

z
z
z
May, 2002
Design errors
Fabrication errors (caused by human errors)
Fabrication defects (caused by imperfect
manufacturing process)
Physical failures
Costs of Testing
z
Design for testability (DFT)

Chip area overhead and yield reduction
Performance overhead
Test development
Test generation and fault simulation
Test programming and debugging
Manufacturing test
Automatic test equipment (ATE) capital cost
Test center operational cost
May, 2002
Components of an ATE
z
z
Powerful computer
Powerful 32-bit Digital Signal Processor
(DSP) for analog testing
Test Program
written in high-level language) running on the
computer
z
Probe Head
actually touches the bare or packaged chip to
perform fault detection experiments

z
Probe Card or Membrane Probe

contains electronics to measure signals on chip pin
or pad
May, 2002
Automated Test Equipment Cost

z
z
Tester cost = b + (m x)
Other cost factors
Tester depreciation
Tester maintenance cost
Test operation cost
Tester segments
Base cost
Cost per pin
Pin count
K$
High-performance ASIC/MPU
250 400
2,700 6,000
512
Mixed-Signal
250 350
3,000 18,000
128 192
DfT Tester
100 350
150 650
512 2500
Low-end C / ASIC
200 350
1,200 2,500
256 1,024
Commodity Memory
200+
800 1,000
1,024
RF
200+
~50,000
32
[ITRS 2001]
May, 2002
Storage Video
Audio
Mixed-Signal System-on-Chip
A
n
a
l
o
g
Digital
system
Interface
Sensors / Transmission
media
Actuators
z
May, 2002
Analog/mixed-signal circuitries are essential in

real-world systems.
Mixed-Signal vs. Digital Testing

Digital
Analog
Test signal
Single type
Multiple types
Response analysis
Direct interpretation
Need mathematical
post-processing
Measurement
requirement
Low-precision
High-precision
Fault model
Mainly catastrophic
Both catastrophic and

parametric
Fault-free response
Binary vectors
Tolerance range in
multi-dim. space
May, 2002
10
Analog/Mixed-Signal Testing Problems

z
z
Size not a problem.

Much harder analog device modeling
No widely-accepted analog fault model.
Infinite signal range.
Tolerances depend on process and measurement
z
May, 2002
error.
Tester (ATE) introduces measurement error.
Digital / analog substrate coupling noise.
Absolute component tolerances +/- 20%, relative
+/- 0.1%.
Multiple analog fault model mandatory.
No unique signal flow direction.

11
Current Status
z
Specification-based (functional) tests

Tractable and does not need an analog fault
model.
Long test time.
Expensive ATE.
Long test development time: application, setup
dependent.
z
May, 2002
Structural ATPG used for digital, just

beginning to be used for analog (exists)
Separate test for functionality and timing
impossible.
12
The Challenges
z
ATE cost problem

Pin inductance (expensive probing)
Multi-GHz frequencies
High pin count (1024)
High-speed serial interfaces are gaining

growing popularity.
High speed, differential, low voltage swing, large
numbers of pin counts.

z
May, 2002
Analog effects appear as digital clock speeds

increase and reach fundamental limits.
13
Solutions?
z
Employ DfT techniques to limit the functional

test performance envelope in production by
Reducing I/O data rate requirements,
Enabling low pin count testing, and
Reducing the dependence on expensive
instruments.
z
May, 2002
Structural testing methodoloty.
14
Mixed-Signal DfT Techniques
Fundamental Issue of Analog

Measurement* - Precision
z
Definition
Measurement sample deviation relative to
measurement mean, e.g. standard deviation (MEAS)

of a set of measurements
z
Sources of imprecision: various noise
Basic technique to increase precision:

integration
the more samples averaged, the better
*S. Sunter, ITC tutorial #15, 1999
May, 2002
16
Fundamental Issue of Analog

Measurement* - Accuracy
z
Definition
Measurement mean relative to true mean, e.g.
average measurement error (MEAS - 0)

z
Sources of inaccuracy: systematic errors
Basic technique to increase accuracy:

substraction
e.g. measure with/without stimulus, inverted/non-
inverted
*S. Sunter, ITC tutorial #15, 1999
May, 2002
17
Reconfiguration Techniques
z
Bypass to gain accessibility of internal nodes
Analog
function
Analog
function
sel1
sel2
Loop around for back-to-back testing
voice
Modulator
RF
sel2
voice
Demodulator
Downconverter
RF
sel1
May, 2002
18
A DfT Technique for SC Filters
C2
2
1
C1
1
v1
2
1
C4
In mission mode:
1
2
In test mode, bypass a filter

stage by converting it to an allpass gain stage
2
1
[Soma VTS94]
v2
Open grounding switches

Close signal path switches
v2 = -(C1 / C2||C4) v1
z
May, 2002
Gated 2-phase clock signals
19
SW Opamp Design [Huertas VTS96]

Test
SW opamp
V+
V-
With additional inputs: Test, VT
VT
Test = 1: unit buffer

Test = 0: regular opamp
Test=1
Test=0
+
-
V+
V-
VT
VT is connected to the output of
+
-
previous stage
z
In test mode
Test = 0 for stage under test
Test = 1 for others
z
V+
Test
V+
Test
V-
VVT
Stage#1
May, 2002
V+
Test
V-
VT
Stage#2
Switches are inserted on small signal

path to reduce performance
degradation
VT
Stage#3
20
Oscillation BIST [Kaminska VTS96]

z
Oscillator
Analog CUT plus added circuitry

become an oscillator in test mode
Oscillation induced through positive
feedback
Analog
CUT
Defects cause deviations in

Oscillation frequency
Oscillation amplitude
Added
circuitry
Very sensitive to process variations

Causes yield loss
Freq.
counter
May, 2002
21
Analog Checksum [Chatterjee D&T96]

z
Analog
CUT
z
+
May, 2002
Sum the voltages at selected

internal nodes
Fault effects appear as error
voltage
Error voltage
22
Built-in Current Sensor

Vdd
z
Current
sensor
Current
signature
CUT
Insert current sensor between CUT and

Vdd (Vss)
Use current signature to make pass/fail
decision
Compare to:
DC threshold (on-chip or off-chip)
Expected spectrum (off-chip)
Cons: resistance in Vdd Path
Vss
May, 2002
23
Analog Output Response Compaction

[Bertrand EDTC 97]
!Ci
Ci
Analog
CUT
z
z
May, 2002
Analog
signature
Opamp-based integrator for analog signal compaction

Suffer fault aliasing problem
24
Subband Filtering [Abraham ITC99]

Signature generation /
comparison
Sampled
CUT
response
Subband
filter
Pass
comparison
Pass
comparison
Pros
Subband filtering requires relatively less
hardware
More immune from fault aliasing problems
z
Cons
Requires on-chip ADC
May, 2002
25
IEEE Standard for a MixedSignal Test Bus
Test Board with Mixed-Signal Parts
May, 2002
The introduction of analog components to 1149.1

compliant chip introduces new problems.
The ability to isolate faulty interconnects on the
analog I/O pins does not exist!!
27
Scope of the Standard

z
Interconnect test
Testing for opens and shorts
among the interconnections

in a PCA (Printed Circuit
Assembly).
z
Parametric test
Making analog characterization measurements.
Testing for presence and value of discrete components in a
PCA.
z
Internal test
Testing the internal circuitry of the mixed-signal component
itself regardless of whether it is part of a PCA.

Not mandatory.
May, 2002
28
Feature Overview
z
Capabilities
Continuous-time voltage, current access via two analog pins.
Measure R, L, C, gain, etc. with < 1% error.
True differential access, and other options.
1149.1 compliant
The idea is to include a set of digitally-controllable

analog boundary cells that can perform the following
four functions:
Disconnect the I/O pin from the analog core.
Set the I/O pin at a logic high or low level.
Detect the logic level present on the I/O pin.
Connect the I/O pin to a two-wire analog test bus.
May, 2002
29
A Minimally Configured 1149.4-Conformant

Component
Analog boundary
module (ABM)
Boundary-scan path
A
B
M
Digital boundary
module (DBM)
AB2
AB1
Core
Circuit
A
B
M
Test bus interface

circuit (TBIC)
VH
VL
VG
Analog pins
VH
VL
VG
Analog Test
Access Port
(ATAP)
AT1
AT2
Test Access
Port (TAP)
TDI
TDO
TMS
TCK
May, 2002
Test Control Circuitry

TAP controller
Instruction Register & decoder
30
Required Test Functions for Analog Pins

z
Isolation
Connect to core.
Disconnected from core (CD state).
Perform tests equivalent to 1149.1

Drive pins Vmax, Vmin (DC).
Compare VPIN to pins VTH.
Facilitate analog parametric tests

Deliver analog ground (VG) via power rail.
Deliver current to pin via AT1 pin and AB1 bus.
Monitor pins voltage via AB2 bus and AT2 pin.
May, 2002
31
Test Access Port (TAP) Pins

z
z
z
TCK test clock

TMS test mode select
TDI test data in
Instruction or scan data
TDO test data out

Test results or for next chip
May, 2002
TRST optional reset
32
Analog TAP pins

z
AT1 stimulus current bus

At least capable of conveying 100 A
May be any combination of AC and DC
DC 10 KHz minimum bandwidth
Sufficient for state-of-the-art ATE to achieve < 1% error
Convey response output (optional)

z
AT2 resultant voltage bus

At least capable of conveying 100 mV
Range: (VSS - 100 mV) to (VDD + 100 mV)
Ensures that protection diodes are not partially activated.
Convey stimulus input (optional)

z
May, 2002
AT1N, AT2N inverted pins for differential

testing.
33
1149.4 Board-Level View
TMS
TCK
TDI
TDI
TDO
TDI
TDO
TDI
TDO
TDO
AT1
AT2
May, 2002
34
Test Register Architecture

TBIC
ABMs
DBMs
Boundary Scan Register

Design-Specific
Test Data Register(s)
Bypass Register
MUX
TDI
Instruction Register
Test control
circuitry
Instruction
Decoder
TMS
TAP
Controller
TCK
May, 2002
O/P
stage
TDO
Control signals
for register enables,
internal re-configuration,
MUX selection, etc.
35
ABM Switching Architecture
May, 2002
36
Possible Control Structure for ABM
May, 2002
37
TBIC Switching Architecture
May, 2002
38
TBIC Sample Implementation of the

Control Structure
May, 2002
39
Virtual Probing
May, 2002
40
Extended Interconnect Measurement

Measurement One
May, 2002
41
Extended Interconnect Measurement

Measurement Two
May, 2002
42
Network Measurement
May, 2002
43
Connectivity of Residual Elements
May, 2002
44
Testing the Analog Core
May, 2002
45
DSP-Based Mixed-Signal
Testing
Analog Test Setup

DC
RMS
filter
CUT
CUT
PEAK
ATE
(etc.)
DC
(etc.)
z
z
May, 2002
Low test throughput.

Less flexibility.
47
DSP-Based Analog Testing

Synthesizer
RAM DAC
Digitizer
Analog
CUT
ADC RAM
synchronization
DSP/Vector processor
ATE
z
Flexible
single setup for multiple types of tests
z
z
May, 2002
High throughput.
Performance limited by ADC/DAC.
48
Test Waveform Synthesis

z
Test signal
digitized sinusoid
digitized multi-tone
pseudo random
May, 2002
49
Output Response Digitization

z
Response analysis:
FFT
IEEE 1057 sinewave fitting
cross-correlation / auto-correlation
May, 2002
50
DSP-based vs. analog ATE

z
z
z
z
z
May, 2002
Increased test throughput

Reduced switching & settling time
Device response is memorized and analyzed
for different parameters
Software DSP doesnt have to be real-time
Performance limited by ADC/DAC
51
DSP-Based Mixed-Signal
SoC Self-Testing
New Opportunities
z
Utilize on-chip DSP capabilities to facilitate

mixed-signal testing.
Test the digital parts first.
May, 2002
On-chip ATE!!
53
DSP-Based Self-Testing of Analog

Components
z
DSP-based BIST on-chip

Analog
tester
DAC
ADC
Relieve the need of expensive
ATE
DUT
Practical
issues
Synchronization
ADC
Synchronization
Test quality limited by
DAC/ADC
Digital
signal processing
DAC/ADC are not always
Memory
available,
and must be tested
first
Digital signal processing
DSP-based ATE
May, 2002
Analog
CUT
DSP/Processor core
Reduce external noise

z
DAC
Memory
SOC
54
The Delta-Sigma Modulation

Analog input
Digital output
Delta-sigma
modulation
fo
z
Hz
fs >> 2fo
modulation
noise
fo
Hz
High sampling rate (fs >> 2fo), low output amplitude resolution
Average output tracks input value
Allows the use of relatively imperfect components

Suitable for VLSI implementation
May, 2002
55
MADBIST - Mixed Analog-Digital BIST

Testing ADC first!!
ADC
DAC
analog sig. gen.
z
Build a precision analog signal generator into the DAC:

z
z
DSP
high frequency, pulse density modulated single bit-stream

using modulation technique
producing high-quality analog sinusoidal/multitone signal
Could perform SNR, FR and IMD tests for ADC

Ref: Toner & Roberts, ITC93, VTS94
May, 2002
56
Multiple Test Phases......

P1
Analog
oscilator
A/D
DSP
D/A
A/D
DSP
high-rsl.
D/A
(scaling)
A/D
DSP
P0: Testing DSP

P1: Testing ADC
P2: Testing DAC
P2
OR
P1+P2
P3: Testing analog

blocks
P3
May, 2002
D/A
analog
block
A/D
DSP
57
Delta-sigma Modulation Based Signal

Generation [Roberts]
Digital signal processing
N-bit Software
delta-sigma
modulator
N-bit
DAC
N-bit DAC
o/p levels
1+ bit in DAC 6dB SNR gain
How to measure the DAC output levels using on-chip

resources?
May, 2002
58
Delta-Sigma Modulation Based

BIST Architecture
ATE
Test stimuli
& spec.
Pass/fail ?
May, 2002
ATE
DUT DUT
Software
modulator
Programmable
core + memory
Response
analysis
1-bit
1-bitDAC
DAC
&&LPF
LPF
1-bit
1-bit
modulator
modulator
Analog
Analog
CUT
CUT
59
Pesudo-Random Testing
P
R x[n]
P
G
D/A
Device
Under
Test
A/D
y[n]
Cross-correlation
delayed
by
m samples
Computing
the
Average
x[n-m]
E{x[n-m]y[n]}
Digital white noise stimulus

Testing multiple specs. in one test session
Effective dynamic testing
Ref: Pan & Cheng, ICCAD95

May, 2002
60
Pseudo-Random Testing
P
R x[n]
P
G
D/A
Device
Under
Test
A/D
y[n]
Auto-correlation
Computing
the
Average
E{y[n]y[n]}
Ref: Pan & Cheng, ICCAD95
May, 2002
61
Automatic Mapping of Tolerance Range

observation space
specification space
mapping of
tolerance range
z
Tools for automatic mapping of tolerance range from

the given specs. to the observation space are needed
Perfect mapping may not be possible
Objective: minimize misclassification
May, 2002
62
Conclusion
Although expected to lag leading-edge device

performance and complexity, DfT techniques
are essential to reduce dependence on
expensive ATE.
Need more research into the area of structure

testing.
No proven alternative to performance-based
analog testing exists.
May, 2002
64
May, 2002
65

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Mixed-Signal Testing &

Mixed-Signal Test Problems

J.L. Huang, EE/GIEE, NTU

Mixed-Signal Test Problems

The Role of Testing

The role of testing is to detect whether

J.L. Huang, EE/GIEE, NTU

What are we after?

J.L. Huang, EE/GIEE, NTU

Design for testability (DFT)

J.L. Huang, EE/GIEE, NTU

perform fault detection experiments

Probe Card or Membrane Probe

J.L. Huang, EE/GIEE, NTU

Automated Test Equipment Cost

Cost per pin

J.L. Huang, EE/GIEE, NTU

Analog/mixed-signal circuitries are essential in

Mixed-Signal vs. Digital Testing

Both catastrophic and

J.L. Huang, EE/GIEE, NTU

Analog/Mixed-Signal Testing Problems

Size not a problem.

No unique signal flow direction.

Specification-based (functional) tests

Structural ATPG used for digital, just

ATE cost problem

High-speed serial interfaces are gaining

numbers of pin counts.

Analog effects appear as digital clock speeds

Employ DfT techniques to limit the functional

Structural testing methodoloty.

J.L. Huang, EE/GIEE, NTU

Mixed-Signal DfT Techniques

Fundamental Issue of Analog

measurement mean, e.g. standard deviation (MEAS)

Sources of imprecision: various noise

Basic technique to increase precision:

J.L. Huang, EE/GIEE, NTU

Fundamental Issue of Analog

average measurement error (MEAS - 0)

Sources of inaccuracy: systematic errors

Basic technique to increase accuracy:

J.L. Huang, EE/GIEE, NTU

Bypass to gain accessibility of internal nodes

Loop around for back-to-back testing

J.L. Huang, EE/GIEE, NTU

A DfT Technique for SC Filters

In test mode, bypass a filter

Open grounding switches

Gated 2-phase clock signals

J.L. Huang, EE/GIEE, NTU

SW Opamp Design [Huertas VTS96]

With additional inputs: Test, VT

Test = 1: unit buffer

VT is connected to the output of

Switches are inserted on small signal

J.L. Huang, EE/GIEE, NTU

Oscillation BIST [Kaminska VTS96]

Analog CUT plus added circuitry

Defects cause deviations in

Very sensitive to process variations

J.L. Huang, EE/GIEE, NTU