Beruflich Dokumente
Kultur Dokumente
Chapter 5
CMOS Circuit and Logic Design
Jin-Fu Li
Hierarchical design
Architecture level
RTL/logic gate level
Circuit level
Layout level
Fanin
The fanin of any complex gate is defined as the number of
Fanout
The fanout of a complex gate is defined as the number of
Fanout=N
Fanin=N
Rp
n
( mnC
+ C r + kC g )
Cr = routing capacitance
k = the fanout
m = fanin of gate
Cg = gate capacitance of a minimum-sized inverter
Cd = source/drain capacitance of a minimum-sized
inverter
m=3, k=4
Cr
mnCd
kCg
=
=
Rp
( mnC
n
Rp
( mnrC
n
R pC g
n
+ C r + kC g )
+ q ( k ) C g + kC g )
( mnr + q ( k ) + k )
= R g C g mr +
R pC g
n
q (k ) +
R pC g
n
Separate delay into internal delay and external delay caused by fanouts
t dr = tint r + k toutput r
tint r = R p C g mr
toutput r =
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R pC g
n
q(k )
(1 +
)
k
EE613 VLSI Design
Rn
= m
( mnrC
n
= R n C g m r + mk
2
= t int f + k t output
+ q ( k ) C g + kC g )
RnC g
n
(1 +
q (k )
)
k
t dr = t df
Rp
Rn
( mnrC g + q ( k )C g + kC g ) = m
( mnrC g + q ( k )C g + kC g )
n
n
R p = mR n
Hence we must design Wp = Wn , thus the delay time is
t df = t dr
Rn
=
( m 2 nrC g + mq ( k )C g + mkC g )
n
t f nand = m
Assume :
n=4
kC g = C L
Rn nand =
q(k ) = 0
m(0.02 m + kC g )
rC g = Cd = 0.005 pf
A
B
C
D
A
B
C
D
Delay (ns)
Delay (ns)
10.0 ns
ND4-Fall 10.0 ns
NR4-Fall
NR4-Rise
ND4-Rise
tinternal-f
(ns)
INV
ND2
ND3
ND4
ND8
NR2
NR3
NR4
NR8
.08
.2
.41
.68
2.44
.135
.14
.145
.19
toutput-f
(ns/pf)
1.7
3.1
4.4
5.7
10.98
1.75
1.83
1.88
1.8
tinternal-r
(ns)
.08
.15
.2
.25
.38
.25
.52
.9
3.35
toutput-r
(ns/pf)
2.1
2.1
2.1
2.1
2.2
4.1
6.2
8.2
16.4
10
GATE
Rn ( )
INV
ND2
ND3
ND4
NR2
NR3
NR4
7.1K
6.3K
6.0K
5.9K
7.3K
7.4K
7.5K
Rp ( )
8.5K
8.6K
8.7K
8.8K
8.4K
8.4K
8.4K
11
CL
Approach 1
CL
Approach 2
Approach 3
CL
12
Delay
Stage 1ns
Delay
Stage 2ns
1
ND8->INV
2.82
ND8
falling
3.37
INV
rising
6.2
(6.5)
2
ND4->NR2
.88
ND4
falling
4.36
NR2
rising
5.24
(5.26)
3
ND2->NR2
ND2->INV
.31
ND2
falling
.4
NR2
rising
Delay
Stage 3ns
.31
ND2
falling
Delay
Stage 4ns
2.17
INV
rising
Total Delay
(SPICE) ns
3.19
(3.46)
13
14
Vss
Vss
15
Vdd
z
z
a
b
a
b
Vss
Vss
16
a
b
Vdd
Vss
Vss
b
17
Design procedure
Draw two dual graphs to P transistor tree and N
transistor tree
Find all Euler paths that cover the graph
Find a P and an N Euler path that have identical
labeling
If not found, break the gate in the minimum
numbers of places to achieve step 3
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D
Z
I1
I3
I1
I2
A
Z
C
D
A
I3
Vss
I2
A
Z
19
Vdd
Vss
A
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D
20
Z
Z
Vdd
B
A
Vss
A
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B
Z
B
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21
Vdd
Vss
z
22
E
Vdd
E
D
C
E
B
Vss
Vdd
P
Vss
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Wp
Dnp
Wn
a
WVss
24
Vdd
Vss
a
Vss
a
25
Vss
26
Routing channels
Vss
27
P-transistors
poly gates
N-transistors
Vss supply
substrate contacts
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a
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30
31
F
A<0>
F
A<1>
A<2>
A<3>
Vss
clk A<3> A<2> A<1> A<0>
32
Vdd
Right
Wrong
Vss
A
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D
EE613 VLSI Design
D
33
34
35
c
a
z
-c
b
c
-c
36
F
n
VL
Time
n
2
(VDD | VTp |) 2
VTn = VTp = VT
p
VOL =
(VDD VT )
2n
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37
inputs
evaluate
clk
precharge
clk
clk
clk
Z=(A+B).C
C
A
Y=ABC
B
B
clk
C
clk
38
A
C
1
B
C1
C2
1
0
A
C2
C1
clk=1
CVDD = (C + C1 + C2 )VA
C
VA =
VDD
C + C1 + C2
If for example
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C1 = C2 = 0.5C
39
clock
N1
N2
N1
inputs
N Logic
N Logic
T d1
Erroneous State
N2
clock
T d2
40
-clk
Z
clk
A
B
C
D
E
41
-B
-A
OUT
OUT
OUT
B
B
A
Complementary
Single-polarity
Cross-coupled
42
A
B
C
D
E
clk
43
weak p device
inputs
N-logic
Block
clk
inputs
clk
Static version
N-logic
Block
Latched version
44
clk
N-logic
A5
C2
A4
C3
A3
C4
A2
C5
A1
C6
A0
C7
C1
N-logic
N-logic
N-logic
45
-clk
clk
to futher P blocks
inputs
stable
during
clk=1
N-logic
P-logic
other P blocks
other N blocks
clk
N-logic
other N blocks
other P blocks
-clk
clk
to futher P blocks
inputs
stable
during
clk=1
N-logic
P-logic
other P blocks
N-logic
other N blocks
46
47
F
-F
Q
-Q
Differential
Inputs
nMOS
Combinational
Network
d
e
Basic version
-d
-e
c -b
-c
-a
A particular function
48
clock
-Q
clock
-Q
Differential
Inputs
Q
nMOS
Combinational
Network
-d
-d
-c
-c
-b
-b
-a
clock
clock
Clocked version
49
inputs
Combinational Logic
current
state
bits
next
state
bits
Q D
Q D
Q D
clock
50
10 ns
C1
inputs
C2
outputs
D Q
D Q
D Q
D Q
D Q
D Q
C1
C2
outputs
inputs
D Q
D Q
D Q
A pipeline system
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51
clock
Setup Time (Ts)
Data
Hold Time (Th)
Q
Clock-to-Q Delay (Tq)
52
clk
0
1
Q
D
S
clk
clk
0
D
Q
S
clk
D
Q
53
clk
D
0
1
QM
S
clk
0
1
D
Q
S
clk
QM
Q
master
slave
54
clk=0
clk=1
master
slave
55
D
Q
clk
clk
56
D
K
J
clk
QN
Q
QN
-clk
clk
J=K=0; Q=D
JN=KN=1; A=QN, B=1; D=AN=Q
J K clk Q QN
J=0;K=1
0
0
1
1
0
1
0
1
Q
0
1
QN
QN
1
0
Q
J=1; K=1
KN=0, JN=0; A=1, B=Q; D=QN
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Tq
Combinational Logic
Td
Ts
Reg.
B
Latch
A
Tq
Combinational Logic
Td
Ts
Latch
B
clock
clock
A
Latch
A Tq
Combinational Logic Ts
Tda
Latch
B
Combinational Logic
Tdb
Latch
C
clock
58
Similarly,
59
Din Pad
in
in
Din
Pad
t = t
t = t+
60
Td
Td
D
When Td
When
> T , Din should become high earlier and Q can become high
Td < T , Din should retain at high longer and Q can be still at high
T
Din
D
TS T
Td
Din
D
Td
Th = Td T
TS = Td T
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Th
61
q1
Tdq
Logic
D Q
Tdl
M1
clk
d2
M2
Tdc
delay
delay
T c1
T c2
clk
T c1
T c2
New data
New Data
Tdc
TC
62
clk
clk
-clk
clk
-Q
D
-clk
clk
-clk
Q
clk
-clk
-clk
D
-clk
clk
clk
clk
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-clk
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63
clk-in
clk
clk
Buffers Necessary for
Large Loads
-clk
-clk
64
(5ns)
FF
(5ns)
CL3
FF
FF
FF
CL1
clk3
clk2
-2ns
0ns
-2ns
clk1
clk
A
7ns B
clk
clk1
clk2
clk3
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B
A
C
B
D
C
65
D
clk
1.
2.
-clk
-clk
clk
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clk
-clk
-clk
Q
clk
clk
-clk
Vss
67
-D
clk
Q1
Q1
-Q1
clk
Latch 1
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Q2
-Q2
clk
Q2
-D
clk
Latch 2
69
-Q2
Q
-Q
-Q1
Q1
clk
Latch 1
clk
Latch 1 enabled
Q2=-Q2=low
Latch 2 enabled
Q1=-Q1=high
70
-reset
Q
clk
-clk
-clk
clk
clk
-clk
D
-clk
clk
-reset
Q
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71
-reset
Q
clk
-clk
-clk
clk
D
-clk
clk
-clk
-set
72
clk
-Q
-clk
clk
-clk
-clk
clk
-Q
D
-clk
clk
-clk
-clk
clk
clk
73
L2
Logic
L2 opaque
clock
L1 opaque
L1 transparent
L2 transparent
74
CLK
Dn
CLK
Xn
Qn
Xn-1
Qn-1
Qn-1
CLK
-Q
75
CLK
CLK
Q
Dn
CLK
Xn
Qn
Xn-1
Qn-1
Qn-1
-Q
76
CLK
CLK
X
77
CLK
D
B
CLK
-Q
A
D
A
-Q
tf
tr
78
clock
chip
chip
clock pad
PLL
clock pad
clock route
clock route
dclk
dclk
output pad
output pad
dclk+dpad
clock
dclk
dclk+dpad
clock
T1
T2
data out
dclk
T2=Clock-to-Q delay
+output buffer delay
T2
data out
79
clock
chip
PLL
/4
clock pad
clock
clock route
clock
PLL
PLL
bus
dclk
system clock
output pad
dclk+dpad
clock
2.
dclk
80
U
Phase Detector
reference clock fn
Charge Pump
Filter
VCO
Vc
nxfn
Vdd
Low-pass filter
Vc
D
81
clk
clk
Q
UP
NOP
clkext
R
EE613 VLSI Design
clk
DN
clkext
82
Pref
Out
Out
D
D
Vrefn
Nref
83
Out
TG
NC1
NC2
84
Delay cell
fVCO
V
Control voltage
V-I converter
tin+t
Control voltage
85
Low-pass filter
Phase Detector
Vc
VCO
fout
fin
fout
fin
D
86
Delay cell
Delay cell
Delay cell
V-I converter
Shift register
VC
Generated clock
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87
NP-Domino Logic
Allow pipelined system architecture
clk
-clk
nMOS
pMOS
Logic
Logic
-clk
clk
clk section
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88
-clk section
-clk
clk
nMOS
pMOS
Logic
Logic
clk
-clk
89
-clk
section
clk
section
section
clk
A
B
C
a0
a2
a1
b0
b2
b1
c0
b1
b2
90
Logic
clock
delay
Tc1
clock
Tc1
Td2
old data
new data
91
Lock-up Latch
Lock-up latch
Logic
clock
delay
Contra-data-direction clock
Logic
delay
clock
92
Two-Phase Clocking
Dynamic register
-ph1
-ph2
Q
ph1
ph2
ph1
ph2
ph1=1,ph2=0
C1
C2
C1
C2
ph1=0,ph2=1
93
Two-Phase Clocking
ph1=1,ph2=1
C1
C2
94
Two-Phase Clocking
ph1
ph1
ph2
ph2
95
Clock Distribution
Vdd=5V
Creg=2000pF (20K register bits @ 0.1pF)
Tclk=10ns
Trise/fall=1ns
Ipeak=Cdv/dt=(2000px5)/1n=10A
Pd=CVdd2f=2000px25x100=5W
96
Clock Distribution
97
clock
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98
99
100
C2
CA
-clkp
Vout
clkn
-clkn
C3
CB
C4
Gnd
Clock
101
Types of pads
Pad-limited pad
PAD
PAD
I/O circuitry
I/O circuitry
102
PAD
PAD
103
OE
P
OE
OUT
PAD
N
data
OUT
Bidirectional pad
PAD
104
Vin
VT-
VT+
VDD
1.
2.
3.
105
Vin
VT+
VTTime
Schmitt trigger turns a signal with a very slow transition into a signal with a sharp
transition
106
VFP
P3
P2
Vin
Vout
N2
VFN
N3
N1
Vin = VT +
3. Then VFN
= VTn
= VT + VTn
107