7)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Universidad Mayor De San Andres
entity kar is
Port ( j,k,clk: in std_logic;
Q,Qn: out buffer std_logic:= 1);
end kar;
architecture Behavioral of kar is
begin
process (j,k,clk)
begin
if clkevent and clk =1 then
if j=0 and k=0 then
Q<=Q;
Qn<=Qn;
ELSIF j=0 AND K=1 THEN
Q<=0;
Qn<=1;
ELSIF j=1 AND K=0 THEN
Q<=1;
Qn<=0;
ELSIF j=1 AND K=1 THEN
Q<=not Q;
Qn<=not Qn;
End if;
End if;
End process;
end Behavioral;

8)

Y1)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Universidad Mayor De San Andres
entity kar is
Port ( a,b: in std_logic;
Q: out buffer std_logic:= 0);
end kar;
architecture Behavioral of kar is
begin
process (a,b)
begin
if bevent and b =1 then
if a=0 then
Q<=Q;
ELSIF a=1 then
Q<=not Q;
Qn<=not Qn;
End if;
End if;
End process;
end Behavioral;
Y2)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Universidad Mayor De San Andres
entity kar is
Port (a,b,k: in std_logic;
Q: out buffer std_logic:= 0);
end kar;
architecture Behavioral of kar is
begin
process (a,b,k)
begin
if aevent and a=1 then
if b=0 and k=1 then
Q<=0;
ELSIF j=1 AND K=1 THEN
Q<=not Q;
End if;
End if;
End process;
end Behavioral;

y3)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Universidad Mayor De San Andres

entity kar is
Port ( a,b: in std_logic;
Q: out std_logic);
end kar;
architecture Behavioral of kar is
begin
process (a,b)
begin
if a=1 then ;
Q<=b;
End if;
End process;
end Behavioral;
y4)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Universidad Mayor De San Andres
entity kar is
Port ( a,b,s: in std_logic;
Q: out std_logic);
end kar;
architecture Behavioral of kar is
begin
process (a,b,s)
begin
if aevent and a =1 then
if s<=0 and b=1 then
Q<=0;
ELSIF s=1 AND b=0 THEN
Q<=1;
End if;
End if;
End process;
end Behavioral;

3)
library ieee;
use ieee.std_logic_1164.all;
entity JK_MS is
port (J, K, C: in std_logic;

Q, NO_Q: out std_logic);

End JK_MS;
Architecture comp of JK_MS is
signal
Y, Q_I: std_logic;
begin
process (C, J, K) variable entradas: std_logic_vector
(2 downto 1);
begin
if (C = 1) then
entradas := J & K;
case entradas
is when
01 => Y <= 0; when
10 => Y <= 1; when
11 => Y <=not Q_I;
when others =>null; -- o Y <= Q_I;
end case;
else
Q_I <= Y;
end if;
end process;
Q <= Q_I;
NO_Q <= notQ_I;
End comp;

2)
library ieee;
useieee.std_logic_1164.all;
entity SRlatch is
port(S, R: in std_logic;
Q, NO_Q: outstd_logic);
End SRlatch;

Architecture behave of SRlatch is

begin
process(S, R)
begin
assert(S = 0 orR = 0)
report
Error: S y R estn a 1
severity error;
if(S = 1)then
Q <= 1; NO_Q <= 0;
Elsif (R = 1) then
Q <= 0; NO_Q <= 1;
end if;
end process;
end behav;

9)
Flip flop sr
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity SR_FF is
PORT( S,R,CLOCK: in std_logic;
Q, QBAR: out std_logic);

end SR_FF;
Architecture behavioral of SR_FF is
begin
PROCESS(CLOCK)
variable tmp: std_logic;
begin
if(CLOCK='1' and CLOCK'EVENT) then
if(S='0' and R='0')then
tmp:=tmp;
elsif(S='1' and R='1')then
tmp:='Z';
elsif(S='0' and R='1')then
tmp:='0';
else tmp:='1';
end if;
end if;
Q <= tmp;
QBAR <= not tmp;
end PROCESS;
end behavioral;
flip flop D
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity D_FF is
PORT( D,CLOCK: in std_logic;
Q: out std_logic);
end D_FF;
architecture behavioral of D_FF is
begin
process(CLOCK)
begin
if(CLOCK='1' and CLOCK'EVENT) then
Q<=D;
end if;
end process;
end behavioral;
flip flop t
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity T_FF is
port( T: in std_logic;
Clock: in std_logic;
Q: out std_logic);
end T_FF;
architecture Behavioral of T_FF is
signal tmp: std_logic;
begin
process (Clock)

begin
if Clock'event and Clock='1' then
if T='0' then
tmp <= tmp;
elsif T='1' then
tmp <= not (tmp);
end if;
end if;
end process;
Q <= tmp;
end Behavioral;
flip flop jk
library ieee;
use ieee. std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;
entity JK_FF is
PORT( J,K,CLOCK: in std_logic;
Q, QB: out std_logic);
end JK_FF;
Architecture behavioral of JK_FF is
begin
PROCESS(CLOCK)
variable TMP: std_logic;
begin
if(CLOCK='1' and CLOCK'EVENT) then
if(J='0' and K='0')then
TMP:=TMP;
elsif(J='1' and K='1')then
TMP:= not TMP;
elsif(J='0' and K='1')then
TMP:='0';
Else TMP:='1';
end if;
end if;
Q<=TMP;
Q<=not TMP;
end PROCESS;
end behavioral;