Beruflich Dokumente
Kultur Dokumente
Goclse
D.A.Goclse
Fundamentals of HDL
ISBN 9788184314052
All rights reserved with Technical Publications. No port of this book should be
reproduced in any form, Electronic, Mechonicol, Photocopy or ony information storage and
retrievol system without prior permis.sion in writing, from Technical Publications, Pvne.
Published by :
Tuchnical Publications rune"
# 1, Amit Residency, 412, Shaniwar Peth, Pun - 411 030, Ind"...
Printer :
Ale<t DTPrintm
Sr.no. 10/3,Sinlw51d Ro1d,
l\.nt 41 1 041
Copyrighted material
Table of Contents
1.1WhyHDL?........................................................................................... 1-1
1.2 A Brief History of HDL ......... .... ... ........................ ...... ...... .................. ... 1 - 2
1.2.1 A Brief History of VHDL . . .. . .... . . .. . ....... . . . ..... . . . . .. . .. . .. . ... . . . ..... 1 - 2
1.2.2 A Brief History of Verilog HDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . 1 - 3
1.3 Structure of the HDL Module ................ ........ ....... ..... ........ ....... ........ .... 1 - 3
1.3.1 Structure of the VHDL Module . . . . . . . . . . . . . . . .. . . . .. . . . . . . . . . . . . . . . . . .. .. . . . . . . 1 - 3
1-4
1.3.1.1 Package. .
1.3.1.2 Entity . . . . .
1 -5
1.3.1.3 Architecture . .
1- 7
1.3.1.4 Configuration. .
1-8
1.3.2 Structure of the Verilog Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - 9
1 - 12
1 -13
1 -14
1.4.1.SOperatorPrecedence .
1 - 14
1.4.2 Operators in Verilog HDL ..... . . . ............ . .... . ....... . . . .. . . . . .. . ...... . 1 -15
1.4.2.1 Boolean Logical Operators. . . .
1-15
1 -1 6
1 -16
1 - 16
1 - 17
1 - 17
1 - 17
1 - 18
Copyrighted material
1-22
1.5.1.3AccessTypes .
1-25
1.5.1.4FileType . . ..
1-25
1.5.1.50therTypes. . .
1- 26
1.5.2 Verilog Data Type.. . . . . .. . .. ...... .. .. ..... . .............. . . ..... . ......... 1 - 27
1.5.2.1 Nets (Wire) and Registers . . . . . .
1-27
1.5.2.2 Abstract Data Types : integer, real time . . . . . . . . . . . . . . . . . . . 1- 28
1.5.2.3 Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1- 29
1.8 Brief Comparison of VHDL and Verilog ...... ... ........ ............................ 1 - 38
1.9 Summary of Operators in VHDL and Verilog ......... ............................ 1 - 39
Review Questions ........... ............................ ............................................. 1 - 41
2.3 Data Type - Vectors ..................................... ........ ...... ....... ...... ............. 2 - 8
Review Questions .............. .......................................................... ......... ...2 - 26
Copyrighted ma erial
3 - 14
3- 20
3 - 21
3- 21
3-23
3-23
3 - 24
3 - 24
. . . . . . . . . . . . . . . . . . . 4-40
Copyrighted material
4 - 41
4 -42
4 -43
5.2.3 Examples of Procedures and Tasks....... . .. . ... . ... . .. .. . . . ..... ........ . ..... 5 - 4
Copyrighted material
6.4 Mixed-Type Description Examples ... ..... ........ .. .... .. ..... ....... .......... ...... 6 - 12
Review Questions ....... ........ ........ .... ........... ......... .............. ..... ,,
6 - 24
7 - 17
8.3 Mapping Process and always in the Hardware Domain ........... ......... 8 - 11
8.3.1 Mapping the Signal-Assignment Statement to Gate-level. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 11
8.3.2 Mapping the Variable-Assignment Statement to Gate-Level Synthesis. . . . . . . . . . . . . . . . . 8 15
8.3.3 Mapping Logical Operators . . . . . . . .. . . . . . . .. . . . . . . . . . . . . . . . . . . . . .. . . . . . .. . . . . 8 16
8.3.4 Mapping the IF Statement .. .. . . . .. . .. . . . . .. . .. . .. . . .. .. . . . . .. . . . . . . .. 8 -19
8.3.5 Mapping the Case Statement. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . 8 31
8.3.6 Mapping the Loop Statement .. . ... . .. . . .. . . .. . ... ..... . . ....... . . . . . ... . . . . . . 8 37
8.3.7 Mapping Procedure or Task.. ... . .. . . . . . . .. . . . . . .. . . . . .. . . . . .. . .. .. .. . ... . . .. 8 38
8.3.8 Mapping the Function Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 40
A 1 VHDL Standard s .. . ... .,, ..... ........ .,, .... ......... ................. ... ,, .. .. A - 1
A.2 Predefined Packages ... ........ ... ........ ... ....... .. ..... ... ...... ............... ........... A - 2
A.2.1 Standard . . . . ... . .. . .. . . . . . .. . ... . . . .. . . . ...... . .. . .. . ..... . .. . . . .. . .. . . . . A 2
A.2.2 TEXTIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A 4
A.2.3 STD LOGIC 1164 .. .. . . . . . .. . . .. . .. . .. . . .. .... . .. . .. .. ... . . .. .. ....... . .. A 5
B-5
B.13 VHDL Code for Dual Priority Encoder ............ .......................... ....... B - 30
B.14 VHDL code for Ones Counter........................................................ B - 33
B 14 1 Behavioral VHDL Code for a 32-bit Ones Counter . .
8-33
8.14.2 Structural VHDL Code for a 32-bit Ones Counter . .. . ... . . . ..... . .. . .. .. .. . .. .. .. B - 34
B.15 VHDL Code for Binary to Gray Code Converter ... .............. ............ B - 38
B.16 VHDL Code for Gray to Binary Code Converter ............................. B - 40
B.17 VHDL Code for Latch ...................................... .............. .................. B - 42
B.18 VHDL Code for Flip-Flop ..... ........ ............ ........ ................................ B - 43
B.18.1 VHDL Code for a D Flip-Flop using IF-THEN Statement . . . . . . . . . . . . . . . . . . . . . . . . . . B 43
Copyrighted material
B-53
B-54
B.19.4.4 VHDL Code for a Left-to-Right Shift Register with an Enable Input.
B - 55
8.19.5 VHDL Code for a 4-bit Parallel Access Shift Register ... . . . . . . . ............ . .. . ... B - 55
B.19.5.1 Using Sequential Statements . . . . . . . . . . . .
B - 55
B.19.5.2 Hierarchical Code for a 4-bit Parallel Access Shift Register. . . . . . . . . . . B - 57
8.19.6 8-bit Shift-Left Register with Positive-Edge Clock.
Asynchronous Parallel Load, SeriallN, and Serial OUT . .. . . . . .. . .. . . . . . . . . . . . . . . . B - 60
B.19.7 8-bit Shift-Left Registe:r with Positive-Edge Clock.
Synchronous Parallel Load, Serial IN. and Serial OUT . .. .. .. . .. .. ...... . . ..... ... B - 61
8.19.8 8-bit Shift-Left/Shift-Right Register with Positive-Edge Clock, Serial IN, and Parallel OUT B - 62
.. ... .. .. ........................... B - 70
B.21.1 VHDL Code for Mealy-type State Machines .. . .. . . . .. .... .. .. . . . .. . ... . . . . ... . . B - 72
Copyrighted material
B.22 VHDL Code for Guessing Game ... ....... ........... .. ........... ....... ............ B - 80
8.23 VHDL Code for Traffic Light Controller ........................................... B - 85
B.24 More Examples ................................................. .... ........ .................. B - 89
3.25 VHDL Code to Display Hex Key Input on the LCD Display ........... B - 107
B.26 VHDL Code to Display Message on the LCD Display .. ......... ........ B - 114
B.27 VHDL Code to Display Key Input on the LED Display .................. B - 120
B.28 VHDL Code to Display Message on the Multiplexed LED Display B - 122
B.29 VHDL Code for Stepper Motor Interfacing ...... ..... .............. ... ..... ... B - 124
iRPJ'O&It~IY
~~fiiw~~~<~~g-1
C.1 Gate Level Modeling .......... ................................................................. C - 1
C.2 Data Flow Modeling ........ ... .......... ........................................... ........ .... C - 6
C.3 Behavioral Modeling .... .......................................... ............. ................ C - 7
C.4 Description of D-Latch .... ........ ........... ................... .............................. C - 8
C.5 Description of Flip-Flops ......... ................... ......... ................................ C - 8
C.6 Description of Sequential Circuits ..................................................... C - 11
C.6.1 Description of Mealy Circuit .. . .. .. .. . ... ..... ... .. .. .. .. .. . . . . . . . ... C - 11
C.6.2 Description of Moore Circuit .. . . . .. . .. . .......... . ..... ... .............. .... . C - 13
Copyrighted material
4. Write a model for ALU. : Refer Section B.8 and Listing C.6.
5 . Develop the HDL code for the following
listing 3.2. 3.3, 3.4, 3.5. 4.16, 4 .18 and 4.19.
6. Design 4-bit binary, BCD counters (Synchronous reset and Asynchronous reset) and "any
sequence" counters. : Refer Section B.20, C.6, C.7 and Listing 3.6, 4.24, 4.26, 6.8. 7.8, 7.9.
7. Write HDL code to display messages on the given seven segment display and LCD and
accepting Hex key pad input data. : Refer Section B.25, B.26, B.27, B.28.
8.
Write HDL code to control speed, direction of Stepper motor. : Refer Section B.29.
9. Write HDL code to generate different waveforms (Sine, Square, Triangle, Ramp etc.,) using
DAC change the frequency and amplitude. : Refer Section C.8.
I 0.
Copyngh1ed f"'ater al
Listing 2 .1 : HDL code for AND-OR circuit - VHDL and Verilog ...... ..... .................................. 2 - 1
Listing 2 .2 : HDL code for holf-odder-VHDL and Verilog ................ ........... . ......................... 2 6
Listing 2.3 : HDL code of o 2 x 1 mulliplexer VHDL ond Verilog . ......................................... 2 - 7
Listing 2.4 : HDL code of o 4 x l mvlliplexer - VHDL and Verilog ... ..................................... 2 - 10
Lisling 2.5 : HDL code for o 2 x 2 unsigned combinational array m ultiplier
VHDL and Verilog. ........................................................................................ 2 13
Lisling 2 .6 : HDL code for a D-lolch.VHDL and Veri log . ...................................................... 2 - 15
Lisling 2.7 : HDL code of o 2 x 2 magnitude comparator - VHDL and Verilog ....................... 2 - 19
Listing 2 .8 : 4-bit ripple-corry odder case slvdy - VHDL ond Verilog ..................................... 2 - 20
Listing 2 .9 : 4-bil cony-lookahead odder - VHDL and Verilog . ............................................. 2 - 23
Listing 3 .1 : Example of on HDL behoviorol description- VHDL and Verilog ............ ................ 3 - 2
Listing 3.2 : VHDL code for behavioral description o f D-Lolch using va riable - assignment
statements - .................................................................................................. 3 - 10
Listing 3.3 : VHDL code for behaviora l description of D-Lotch using signal-assignment
stotemenls .. .. .. .. . .. .. .. . .. .. .. .. .. . .. . .. .. .. .. .. . ... .. .. . .. . . .. .. . .. . .. .. . .. .. . .. . .. .. . .. .. .. .. ..
. 3 - 11
~~~twtft~m fi!m:;nwt~~iih'i&iWli$ii.5W
Gopyngh' !Cl rr
M
rial
Listing 3 .5 : HDL code for o positive edge-triggered JK fl ip-flop using the case
stotement-VHDL end Verilog .........................................................................
3 . 16
Listing 3.6 : HDL code for a 3-bit binary counter using the cose statement................ ..... ....... 3 . 18
Listing 3. 7 : Verilog description for o 4-bit priority encoder .................................................. 3 21
l isting 3.8 : HDL code for colculoting the foctoriol of positive integers-VHDL end Verilog .... 3 26
listing 3.9 : 4x4-bit booth algorithm- VHDL and Verilog .................................................... 3 - 33
.... ............ 4. 58
Copyrighted material
listing 4.27 : .HDl d escription o f N-bit memory word using genero te .... ..................... ........... 4 60
listing 4 .28 : HDl descrip""n o f N-bit reg ister using VHDl ond Verilog . ............................ 4 61
listing 4.29 : HDl description o f N-bit left shift register ........................................... ............ 4 62
listing 5.1 : HD l description of o full odder using procedure ond tosk-VH Dl ond Verilog ...... 5 - 4
l isting 5.2 : HD l description of on N-bit ripple corry odder using procedure ond toskVHDl ond Verilog ........................................................................................... 5 - 6
listing 5.3 : HDl code for converting on unsigned binary to on intege r using procedu re ond tosk
....................................................................................................... 5 - 8
listing 5.4 : HDl code for converting o fraction binary to reol using procedure ond tosk ........ 5 - 10
listing 5.5 : VHDl code for converting on unsigned integ er to binary using p rocedure ........... 5 - 12
listing 5.6 : VHDL code for converting o signed b inary to integer using procedure ................ 5 - 14
listing 5.7 : VHDL code for converting on intege r to signed binory using procedure ............... 5 - 15
listing 5.8 : HDl code for signed vector multip lication using procedure ond tosk .................. 5 - 17
listing 5.9 : HDL function to find the greater of two signed numbers .................................... 5 24
listing 5.10: VHDL functio n to describe the edge trigger D flip-flop .......... ........................... 5 26
listing 5.11 : Verilog function thot calcula tes loctoriol of o number .......................... ............ 5 27
l isting 5.12 : VHDL code for reading ond processing a text file containing integer numbers . .. 5 33
listing 5.13 : VHDL code for reading ond processing o text file containing reol numbers ........ 5 35
listing 5.14 : VHDL code for reading o string of chorocters into on orroy .............................. 5 - 36
l isting 5.1 5 : HDl code for writing integer numbers too file ........... .................................... . 5 - 37
listing 5. 16 : VHDl code for finding the percentage morks for o porticulor student. ............... 5 . 38
listing 5. 17: Verilog code for storing y = x
.................. 6 - 7
. .................................. 6 11
..................... 6 . 20
Copyrighted material
4 ......................... 8 13
Listing 8 .1 8 : Struclurol Veri log code for the logic diagram in Fig . 8 .1 5 (b) . ..... .................... 8 14
Listing 8 .19 : VHDL voriobie-ossignment statement ........................ .................... ................. 8 15
Listing 8 .20 : Mopping logical opera tors In HDL ............................................... ...... ,.......... 8 17
Listing 8.21 : Example of if-else statement... ...................................................................... 8 19
Listing 8 .22 : Example of if-else statement ........................................................ ................. 8 19
Listing 8 .23 : Example of comparison using if-else sta tement ...................................... ........ 8 20
Copyrighted material
Copyrighted material
Introduction
1.1 Why HDL?
We are familiar with the design of a digital system. The basic steps involved in
this process are,
a. Specify the desired behaviour of the circuit.
b. Synthesize the circuit.
c. Implement the circuit.
d. Test the circuit to check whether the desired specifications meet.
But as the size and complexity of digital systems increase, they can not be
designed manually; their design becomes highly complex. At their most detailed level,
they may consists of millions of elements, i.e. transistors or logic gates. So Computer
Aided Design (CAD) tools are used in the design of such systems. One such a tool is
a Hardware Description Language (HDL).
HDL describes the hardware of digital systems. This description is in textual form.
The Boolean expressions, logic diagrams and digital circuits (simple and complex) can
be represented using HDL.
The HDL provides the digital designer with a means of describing a digital
system at a wide range of levels of abstraction and at the same time,
provides access to computer-aided design tools to aid in the design process
at these levels.
The HDL, represents digital systems in the form of documentation which can
be understood by human as well as computers.
The HDL makes it easy to exchange the ideas between the designers.
(1 - 1)
Copyrighted material
Fundamentals of HDL
1-2
Introduction
Copyrighted material
Fundamentals of HDL
1.3
Introduction
Package (optional)
Entity
Architecture
Configuration (optional)
The Fig. 1.1 shows the relationship of these basic blocks of VHDL program. A
design may include any number of package, entity, architecture and configuration
Copyrighted material
14
Fundamental s of HDL
Introduction
declarations. It is important to note that the entity and archit~ture blocks are
compulsorily required; however, the package and configuration blocks are optional.
Package
Configuration
Fig. 1.1 Relationship of VHDL design units
1.3.1.1 Package
There are some declarations which are common across many design units. A
package is a convenient mechanism to store and share such declarations. It is an
optional design unit. A set of declarations contained in a package declaration may be
shared by many design units. It defines items that can be made visible to other design
units. A package is represented by :
Package declaration
Package declaration
It defines the interface to the package. The syntax of a package declaration is given
below.
PACKAGE package_name IS
type
subtype
constant
signal
variable
subprogram
file
alise
component
attribute
declarations
declarations
declarations
d eclarations
declarations
declarations
declarations
declarations
declarations
declarations
Copyrighted material
15
Fundamentals of HDL
Introduction
attribute
specifications
disconnection specifications
use clauses
END package_name;
The items declared in a package declaration can be accessed by other design units
by. using the 'library' and 'use' clauses. This is explained in the further section. The
example of package declaration is given below.
package MUX 4-to-l_package is
component MUX 4-to-1
IN STD_LOGIC;
IN STD_LOGIC_VECTOR (1downto 0)
OUT STD_LOGIC;
and component;
and MUX 4-to-l_package;
Fig. 1.2 Package declaration for 4-to-1 multiplexer
Package body
It contains the details of a package, that is the behavior of the subprograms and
the values of the deferred constants which are declared in a package declaration. The
package body may contain other declarations. The syntax of it is as given below.
package body package_name is
subprogram bodies
complete constant declarations
subprogram declarations
type and subtype declarations
file and alias declarations
use clauses
and package_name;
The name of the package must be same as the name of its corresponding package
declaration. If the package declaration does not have any subprogram or deferred
constant declarations, a package body is not necessary.
1.3.1.2 Entity
modelled using an entity de<;laration and atleast one architecture body. An entity X,
when used in another entity Y, becomes a component for the entity Y. Entity gives
interfacing between device and the other peripherals. An entity usually has one or
more ports, which are analogous to the pins on a schematic symbol. All information
Copyrighted material
1-6
Fundamentals of HDL
Introduction
must flow into and out of the entity through the ports. Each port must contain name,
data flow direction and type.
The syntax of a VHDL entity declaration is as shown below.
entity entity_name is
port (
signal_names
mode
The ports can be declared in four types which specify the signal
direction.
in
out
inout
buffer
The signal is an output from the entity and its value can also be
read inside the entity's architecture.
For example, there is a system having its inputs and outputs like rd, wr, ADD,
x, y, z, ad, al. The entity for this can be written as shown below.
entity gate_logic is
port (
wr
rd
: in std_logic;
: In std_logic;
ad
ADD
x,y,z
: out std_logic;
Copyrighted material
Fundamentals of HDL
al
1-7
Introduction
);
end gate_logic ;
Here rd, wr are inputs to the system so they are input ports. The ad is also input
signal but it is 8 bit so it is defined as vector (7 downto 0). It means 7 is assigned to
MSB of your signal and 0 is assigned to LSB of your signal. Similarly x, y, z are
output signals so they are defined as output ports. The al is coming out and is
defined as buffer signal, so that you can also read this signal.
1.3.1.3 Architecture
Declarations
begin
concurrent statements;
sequential statements;
end architecture_name;
To design any system, first we have to write the entity. In the architecture, we
write architecture_name for that entity. In declaration part, types, signals, constants,
function definitions, procedure definitions, component definitions etc. can be declared.
The variables can also be declared here. VHDL variables are similar to signals, except
that they usually do not have physical significance in a circuit. A variable declaration
is similar to a signal declaration, except that the 'variable' keyword is used as shown
below.
variable variable_names : variables_type;
Copyrighted material
1. 8
Fundamentals of HDL
Introduction
Example:
process (a,b)
begin
if a 'O' an d b
c< = o:
else
Sequential --+-- + ---t
c < = '1';
statements
end if:
end process;
end gate;
='O' the n
1.3.1.4 Co nfiguration
2. The language is case insensitive. Le. the uppercase an d lowercase letters are
considered as same.
3. The name should start with an alphabet letter and can include the special
char::.crer underscore LJ.
4. The name of the ports must be followed by a colon (:).
5. The architecture body starts with the predefined word begin, followed by
statements that detail the relationship between the outputs and inputs.
6. The comment should begin with two hyphens (--).
7. Leaving the blank spaces between two words or at the beginning of the line
are allowed.
8. Leaving the blank line(s) is allowed in the module.
Copyrighted material
Fundamentals of HDL
1-9
Introduction
The <module name> is an identifier that uniquely names the module. The module
name is user selected . It should start with alphabetical letter and it can include the
special character underscore (j. In contrast to VHDL, Verilog is a case sensitive. The
<port list> is a list of input, inout and output ports which are used to connect to other
modules. The <declares> section specifies data objects as registers, memories and wires
as wells as procedural constructs such as functions and tasks.
The Listing. 1.1 shows the example Verilog code. This code is the description for
the logic circuit shown in the Fig. 1.3.
....
I R;
endmodule
Copyrighted material
Fundamentals of HDL
Introduction
1 -10
1n contrast to VHDL, in Verilog, input and output port signal types are implicitly
declared. We can declare more than one input or output on the same line using a
comma (,) to separate each input as shown in the Listing 1.1.
Important points to remember while representing any module using Verilog HDL.
1. Each statement
2. The blank lines are allowed in the module and also spaces between the words
or at the begi1ming of the line are allowed.
3. The language is case sensitive. i.!?. the uppercase and lowercase letters are
considered as different.
4. The function of a circuit is indicated by the text between two slashes (I/) and
the end of the line which is interpreted as a comment.
5. Verilog uses about 100 keywords. All must be given in lowercase.
6. Identifiers are the names given to variables. With these names, they can be
referred in the design. They consist of alphanumeric characters and underscore
(-). They can not start with a number.
7. The input and output keywords are used for declaring inputs and outputs.
The keyword inout is used for a signal that is both, an input and an output.
8. Internal connections within the circuit are declared with the keyword wire.
Note :
The ke}"vords are highlighted by printing them in bold. But it is not the
requirement of Verilog HDL.
1.4 Operators
U$
HDL has an extensive list of operators to perform a wide variety of functions. Let
:.ee the operators in VHDL and Verilog HDL.
Logical
Relational
Arithmetic
Copyrighted material
Fundamentals of HDL
Introduction
1 - 11
Logical operators, when combined with signals and/or variables, are used to
create combinational logic. VHDL provides the logical operators as shown in the
Table 1.1.
Operator
AND
OR
NANO
NOR
XOR
XNOR
NOT
Equivalent Logic
=V=C>=D-
=D=lD-=)[>--I>--
Operand Type
Result Type
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
These operators are defined for the types bit:' std_logic and Boolean, and for
one-dimensi011al arrays of these types (for example, an array of type bit_vector or
std_logic_vector).
The effects of the logical operators are defined in the follow ing tables. The symbol
T represents TRUE for type BOOLEAN, '1' for type BIT; the symbol F represents
FALSE for type BOOLEAN, 'O' for type BIT.
Copyrighted material
Fundamentals of
HDL
1 12
Introduction
A and B
A or B
A xor B
Anand B
A nor B
not A
Description
Operand Type
Result Type
Equality
Any type
Boolean
I=
Inequality
Any type
Boolean
<
Less than
Boolean
<=
Boolean
Greater than
Boolean
Boolean
>
>=
Table 1.2
The following statement demonstrates the use of some of the above relational
operators :
if (A/= B) then ...
If A is greater than B, the value of the expression (A > B) is true (1); otherwise it
is false (0).
Note : The operands of each relational operator must be of the same type. The
result type of each relational operator is the predefined type Boolean.
Copyrighted material
Fundamentals of HDL
1 -13
Introduction
Operation
Operands (A or
B) Type
Result Type
Addition
A+B
A numeric
B numeric
numeric
Subtraction
A-B
A numeric
B numeric
numeric
Multiplication
AxB
A integer or real
B integer or real
Same as A
Multiplication
A xB
A physical
B integer or real
Same as A
Multiplication
A xB
A integer or real
B physical
Same as B
Division
A +B
A integer or real
B integer or real
Same as A
Division
A +B
A integer or real
B physical
Same as B
Division
A +B
A physical
B integer or real
Same as A
mod
Modulus
A mod B
A only integer
B only integer
integer
rem
Remainder
A rem B
A only integer
B only integer
integer
abs
Absolute
abs (A)
A numeric
.
.
&
..
Concatenation
(A & B)
positive numeric
A numeric or
array
B numeric or
array
Exponent
A B
A real or integer
B only integer
Same as A
Same as A
Copyrighted material
Fundamentals of HDL
1 -14
Introduction
These operators shift or rotate the bits of the operand right or left by some
specified number of bit positions. There are two types of shift operators : Logic shift
operator and arithmetic shift operator. When logical shift operator is used, the vacant
positions created due to shift operation are filled with zeros. On the other hand, when
arithmetic right shift operator is used the vacant positions created due to shift
operation are filled with MSB (sign bit). The arithmetic left shift is same as the logical
left shift.
The Table 1.4 shows the shift and rotate operators supported in VHDL. To
understand the function of these operators, assume that operand A is the 4-bit vector
with value 1101.
Operator
Operation
Description
Operand A
Operand A after
before operation
operation
sll
A sll 1
110 1
10 10
Sil
A sll 2
110 1
0 100
srl
A Sri 1
110 1
0 110
srl
A Sri 2
110 1
0 0 11
sla
A sla 1
110 1
10 10
sra
A sra 1
1 10 1
1 110
rol
A rol 1
110 1
10 11
ror
A ror 1
110 1
1 110
Note:
Shift left by 1 bit performs multiplication by two while shift right by 1 bit
performs division by two.
With rotate operation we can restore the original contents after one complete
cyclic rotation. This is not the case with shift operation.
The precedence of operators is shown in Table 1.5. The operators belongs to same
row have the same precedence level. Operators are listed in order of decreasing
precedence.
Copyrighted material
Fundamentals of HDL
1 -15
Type
Introduction
Operators
-. abs
Miscellaneous operators
Multiplying operators
I mod rem
Sign
Adding operators
- &
Relational operators
Logical operators
and
or nand nor
Table 1.5
Operators of higher precedence are associated with their operands before operators
of lower precedence. For a sequence of operators wi~ the same precedence level, the
operators are associated with their operands in textual order, from left to right. The
precedence of an operator is fixed and may not be changed by the user, but
parentheses can be used to control the association of operators and operands.
Boolean Logical
Bitwise logical
Relational
Binary Arithmetic
Unary Arithm etic
Other
Logical operators operate on logical operands and return a logical value, i.e.,
TRUE(!) or FALSE(O). Used typically in if and while statements. Do not confuse
logical operators with the bitwise Boolean operators. For example, 1 is a logical NOT
and - is a bitwise NOT. The first negates, e.g. !(5 == 6) is TRUE. The second
complements the bits, e.g. -{l,0,1,1) is 0100.
Operator
!
Name
Logical negation
&&
Logical AND
11
Logical OR
Copyrighted material
Fundamentals of HDL.
1 -16
Introduction
Unary reduction operators operate on a single operand. They produce a single bit
result from applying the operator to all of the bits of the operand. For example, in
statement B =&A, if A. = 1101, then B = (1 & 1 & 0 & 1) = 0.
Operator
Name
&
ANO reduction
OR reduction
XOR reduction
-&
NANO reduction
-1
NOR reduction
XNOR reduction
Bitwise operators operate on the bits of the operand or operands. The result of A
& B is the AND of each corresponding bit of A with B. For example, if A = 1011 and
B = 0101, then C= A & B gives C = 0001. Except for bitwise .negation, these operators
operate on a two operands.
Operator
Operation
Bitwise negation
&
Bitwise ANO
Bitwise OR
Bitwise XOR
-&
Bitwise NANO
- 1
Bitwise NOR
_11.
or"'-
Relational operators compare two operands and return a logical value, i.e. TRUE(l)
or FALSE(O). For example, if A = 0100 and B = 0100, then statement if (A== B) results
True(l). If any bit is unknown, the relation is ambiguous and the result is
unknown(X).
Copyrighted material
Fundamentals of HDL
Introduction
1 - 17
Ope rator
Operatio n
>
Greater than
>=
<
Less than
<=
--
Logical equality
!=
Logical inequality
Binary arithmetic operators operate on two operands. Register and net, i.e. wire,
operands are treated as unsigned. However, real and integer operands may be signed.
U any bit of an operand is unknown ('x') then the result is unknown.
Operator
Ope ration
Add ition
Subtraction
Multiplication
Division
Modulus
Comments
Operatio n
Comments
Unary minus
O peratio n
Comm ents
---
Case equality
!==
Case inequality
'
Copyrighted material
Fundamentals of HDL
<<
1 -18
Introduction
Shift left
Shift right
?:
Conditional
=A < 2; //shifts A
Type
Unary operators
Multiplying operators
.. I o/o
Sign operators
Relational operators
<< >>
& -&
I -I
'
_, + - (Highest precedence)
< <=
> >=
== != === -==
Logical operators
& -&
I- I
&&
II
Conditional operators
?: (Lowest precedence)
Fundamental s of HDL
1 -19
Introduction
Scalar types : The scalar types include numeric data types and enumerated
data types. The numeric types consist of integer, floating point (real) and
physical types. Bit, Boolean and character are all enumerated types.
Composite types : Array and record types are composite da ta types. The
values of these types are collection of their elements.
Access types : They are pointers; they provide access to objects of a given
data type.
File type : They provide access to object tha t contain a sequence of values of
a given type.
Other types : They include the data types provided by the several external
libraries.
We have seen that, the scalar types consist of enumeration types, integer types,
physical types, and floating point types. Enumeration, d ata types and integer types are
called discrete types. On the other hand, in teger types, floating point types and
physical types are called numeric types.
Integer type
As the name indicates, it covers all integer values, the values can be positive or
negative. The defau lt range of Integer is -2147483647 to +21 47483647. However, user
can specify a shorter range by using the pre-defined word ran ge. The shorter range
may require less bits to represent the number when binary encoded. We can define
the subtype of base type whose range must be wholly contained within the bounds of
the range of base type.
Examples:
sub typ e shorter is short range 0 to 31; -- 5 bit binary encod ing.
sub type shortest is short range 0 to 15; -- 4 bit binary encoding.
Copyrighted material
Fundamentals of HDL
1 20
Introduction
Note : The encoding of integers in a binary format means that all ranges are rounded
up to the nearest power of two. This means that if shorter had been declared
as:
subtype shorter is short range 0 to 15;
Then the object is synthesized into 4 wires. Objects declared type of type integer
without a range constraint will be synthesized into 32 wires.
Real (floating point) type
Floating point type definition defines both a type and subtype of that types. The
default range of floating point is -1E38 to + IE38. Like integer type, here also we can
specify the shorter range by using the predefined word range.
Examples :
type Real_data is real;
type Voltage is range to -12.0 to +12.0;
Subtype min voltage is range - 5.0 to +5.0;
Enumerated types
Bit, Boolean, Character and severity_level are the enumerated types. These are
defined in a library such as std or ieee.
Bit data type allows only two values 0 or 1. It is used to describe a signal that
takes only l(High) or O(Low). The type Boolean has two values, True(l) or False(O).
Both True and False are predefined words.
The type character constitutes the 128 characters of the ASCII character set. These
character values are called character literals and are always written between two
single quotes (' '). For example, 'A', '_', ' 3 ' and so on.
An object with type severity can take one of four values : note, warning, error or
failure. This type is typically used in assertion statements.
Copynqhted material
1 - 21
Fundamentals of HDL
Introduction
Examples :
type Bit is ('O', '1');
type Switch_level is ('O', ' 1', 'x');
Physical type
ps = 1000 fs;
ns = 1000 ps;
us = 1000 ns;
ms= 1000 us;
-- femtosecond
picosecond
nanosecond
-- microsecond
-- millisecond
sec
1000 ms; -- second
min = 60 sec; -- minute
end units;
type distance is range 0 to 1E16
units
-- base unit :
A''
-- angstrom
-- metric lengths;
nm
10A;
nanometer
um
= 1000 run;
micrometer (or micron)
mm = 1000 um;
-- millimeter
cm= 10 mm;
-- centimeter
Copynqhted material
Fundamentals of HDL
m = 1000 mm;
km= 1000 m;
-- English lengths :
mil= 254000 A;
inch = 1000 mil;
ft = 12 inch;
yd= 3 ft;
fin = 6 ft;
Introduction
-meter
kilometer
.. mil
-- inch
foot
yard
fathom
1 - 22
-- mile
league
y : time; z : integer:
y := y/10;
The arithmetic operations are predefined for all physical types. It is an error if the
execution of such an operation cannot deliver the correct result (that is, if the value
corresponding to the mathematical result is not a value of the physical type).
User-defined types
The user can define a type by using the predefined word type.
Example :
Composite types are used to define collection of values. These include both arrays
of values (collection of values of a single type) and records of values (collection of
values of the same or different types).
Copyrighted material
Fundamentals of HDL
1 - 23
Introduction
An array object is a composite object consisting of elements that have the same
subtype. The name for an element of an array uses one or more index values
belonging to specified discrete types. The value of an array object is a composite value
consisting of the values of its elements.
An array object is characterized by the number of indices (the dimensionality of
the array), the type, position and range of each index and the type and possible
constraints of the elements. The order of the indices is significant.
A one-dimensional array has a distinct element for each possible index value. A
multidimensional array has a distinct element for each possible sequence of index
values that can be formed by selecting one value for each index (in the given order).
The possible values for a given index are all the values that belong to the
corresponding range; this range of values is called the index ran ge.
Example:
Copyrighted material
Fundamentals of HDL
1 24
Introduction
string and bit_vector are the predefined array types, which are defined in
package std.
The values of the predefined type string are one-dimensional arrays of the
predefined type character, indexed by values of the predefined subtype positive;
subtype pos!tive is integer range 1 to integerhigh;
type string is array (positive range <>) of character;
The values of the predefined type bit_vector are one-dimensional arrays of the
predefined type BIT, indexed by values of the predefined subtype natural:
subtyp e natu ral is integer range 0 to integerhigh;
type bit_vector is array (natural range <>) of bit;
Record type
A recod type is a composite type, objects of which consist of named elements.
The value of a record object is a composite value consisting of the values of its
~iements. The record type is analogous to the record datatype in pascal and the struct
decl:uation in C.
record type definition creates a record types; it consists of the element
declarations, in the order in which they appear in the type definition.
A
Example :
type DATE is
record
DAY
: INTEGER range 1 to 31
MONTH : MONTH_NAME;
YEAR
end record;
Copynght8d maten:il
Fundamentals of HDL
1 - 25
Introduction
File types are used to define objects representing files in the host system
environment. The value of a file object is the sequence of values contained in the host
system file.
type_file _type_name Is file of type_name;
The type mark in a file type definition defines the subtype of the values contained
in the file. The type mark may denote either a constrained or an unconstrained
subtype. The base type of this subtype must not be a fi le type or an access type. If the
base type is a composite type, it must not contain a subelement of an access type. If
the base type is an array type, it must be a one-dimensional array type.
Examples :
file of string
file of natural
Three operations are provided for objects of a file type. Given the following file
type declaration :
type FT is file of TM :
Where type mark TM denotes a scalar type, a record type, or a constrained array
subtype, the following operations are implicitly declared immediately following the
file type declaration :
procedure read (F : in FT; valu e : out TM);
proced ure write (F : out FT; value: in TM);
function endfile (F: in FT) return b oolean;
Procedure read retrieves the next value from a file. Procedure write appends a
value to a file. Function endfile returns False if a subsequent read operation on an
input file can retrieve another value from the file; otherwise it returns true. Function
endfile always returns true for an output file.
Copyrighted material
1 - 26
Fundamentals of HDL
Introduction
std_logic is a data type defined by IEEE standard 1164, and defined in the file
ieee.vhd.std_logic is an enumerated type. This logic has nine v'llues as listed in
Table. 1.7.
Value
Definition
- Uninitialized
- Forcing unknown
- Forcing 0
- Forcing 1
z
w
- High impedance
- Weak unknown
- Weak 0
- Weak 1
- Don't care
Table 1.7
The std_logic data type is very important for both simulation and synthesis.
Std_logic includes values that allow us to accurately simulate such circuit conditions
as unknowns and high-impedance stages. For synthesis purposes, the high-impedance
and don't -care values provide a convenient and easily recognizable way to represent
three-state enables and don't-care logic. For synthesis, only the values 0, 1, z and have meaning and are supported.
std_lugic_vector type
In the above example, port I is declared as type std_logic_vector which has 8 bits.
Signed
Copyrighted material
1 - 27
Fundamentals of HDL
Introduction
bit of objects of signed type represents sign and such objects are represented in 2's
complement form. let us see the object definition.
In the above definition, the variable difference is declared as signed type and has
5 bits with initial value 10011, or - 13.
Unsigned
The type unsigned represents integer data in the form of an array of std_logic and
it is declared in the external package numeric_std. Let us see the object definition
variable num : unsigned (4 downto 0) := 10011; In the above definition, the variable
num is declared as unsigned type and has 5 bits with initial value 10011, or 19.
The reg and wire data objects may have the following possible values :
Value
Definition
The reg variables are initialized to x (unknown logic value) at the start of the
simulation. Any wire variable not connected to something has the x value. We may
specify the size of a register or wire in the declaration. For example, the declarations
wire Dl;
wire DO = t 'bO;
reg flag;
Copyrighted material
Fundamentals of HDL
1. 28
Introduction
Specify wires 0 1 and DO to be single bit wide. The initial value of DO is l'bO,
which represents 1 bit with value 0.
When the size of the reg or wire is more than 1 bit then registers and wires are
declared as vectors. Vectors are declared by brackets. The bits in vectors can be
referenced by the notation (<start-bit>:<end-bit>]. For example, the declarations
reg (0:7( A, B;
wire 10:3) Dataout;
reg (7:0) C = 8'b10001010;
reg (7:0) D ~ 3'd138;
A = 8'b01011010
B = {A(0:3) I A(4:7(, 4'b0000};
Specify registers A and B to be 8-bit wide with the most significant bit the zeroth
bit, whereas the most significant bit of register C and register D is bit seven. The wire
Dataout is 4 bits wide. C holds a value of 10001010 (b stands for binary). D holds the
same value as C (10001010); however it is specified in decimal 138 (d stands for
decimal).
B is set to the first four bits of A bitwise or-ed with the last four bits of A and
then concatenated with 0000. B now holds a value of 11110000. The II brackets means
the bits of the two or more arguments separated by commas are concatenated
together.
An argument may be replicated by specifying a repetition number of the form :
In addition to modeling hardware, there are other uses for variables in a hardware
model. For example, the designer might want to use an integer variable to count the
number of times an event occurs. For the convenience of the designer, Verilog HDL
Copyrighted material
Fundamentals of HDL
1 - 29
Introduction
has several data types which do not have a corresponding hardware realization. These
data types include integer, real and time. The data types integer and real behave
pretty much as in other languages, e.g. C. Be warned that a rag variable is unsigned
and that an integer variable is a signed 32-bit integer. This has important
consequences when we subtract.
time variables hold 64-bit quantities and are used in conjunction with the $time
system function. Arrays of integer and time variables (but not reals) are allowed.
Multiple dimensional arrays are not allowed in Verilog HDL.
Examples:
integer Count;
integer K(1:64J;
real cost;
time Start, Stop;
1.5.2.3 Parameter
Parameter type is used to define global constants. We can declare global constants
by predefined word parameter.
Examples:
parameter N = 0;
parameter M = 7;
reg (M:NJ C = 8'b10001010;
Behavioral
Data flow
Structural
Switch-level
Mixed-Type
Mixed-Language
Copyrighted material
1 30
Fundamentals of HDL
Introduction
Let us see the HDL uescription of full adder shown in the Fig. 1.4
begin
In Verilog, the key mechanism used to model the behavior is predefined words
always or initial.
Copyrighted material
Fundamentals of HDL
....
1 - 31
lntrQduction
Sum = (A
B)
Cout = (A & B)
Cin;
I (Cin &
A)
I (Cin &
B);
end
endmodule
end adder;
In Verilog, predefined word assign is used to assign a value to the left-hand side
of a s igna l-ass ignme nt s ta te m ent.
....
= (A
B)
Cin;
I (Cin &
A)
I (Cin &
B);
endmodule
Copyrighted material
Fundamentals of HDL
1 - 32
Introduction
The built in operators of VHDL (for example : AND, OR,"NOT) and Verilog (for
example & I ") are used in the expression.
Here, the data flow model for the full_add is described using a two concurrent
signal assignment. In a signal assignment statement, the symbol <= implies an
assignment of a value to a signal in VHDL. The value of the expression on the
right-hand-side of the statement is computed and is assigned to the signal on the
left-hand-side, called a target signal. In Verilog, predefined word assign is used to
assign a value to a signal. A concurrent signal assignment is executed only when any
signal in the expression on the right-hand-side has an event on it, that is, the value of
the signal changes.
Design hierarchy
Copyrighted material
Fundamentals of HDL
1 - 33
Introduction
begin
use ieee.std_logic_1164.all;
entity Inv la
port (X : in std_logic;
Y : out std_logic);
end Inv;
architecture Inverter of Inv la
component nmos
port (01
: out std_logic;
11, 12
: in std_logic);
Copyrighted material
1 . 34
Fundamentals of HDL
Introduction
en d component;
Component pmos
port (01
: out std_logic;
11, 12
: in std_logic);
en d component;
- pmos and nmos are keywords for switch level
for all : pmos use entity work.mos (pmos_behavioral);
for all: nmos use entity work.mos (nmos_behavioral);
-- above two statements refer the mos package.
constant vdd : std_ logic : = '1 ';
constant gnd: std_logic := 'O';
be gin
p : pmos port map (Y, vdd, X);
n : nmos port map (Y, gnd, X);
end inverter;
....
Copyrighted material
Fundamentals of HDL
1 . 35
Introduction
-- behavioral description
Cout < = (A and B) or (Cin and A) or (Cin and B);
end proce ss;
end adder;
...
-...
input A, B, Cin;
outpu t Sum, Cout;
re g Sum, Cout;
11 data-flow description
11 behavioral description
always @(A, B, Cin)
begin
Cout = (A & B)
I (Cin &
A)
I (Cin &
B);
end
e n dmod ule
I Cl
endmodule
Copyrighted material
Fundamentals of HDL
1 . 36
Introduction
library ieee;
use ieee.std_logic_1164.all;
-- For correct mixing of two codes the entity name should be same, i.e., Half_adder
e ntity Half_ adder is
port ( X, Y : in std_logic;
S, C : out std_logic);
end Half_adder;
architecture add er of Half adder is
begin
S <= A x or B;
C <=A and B;
end adder;
1.7.1 Synthesis
The task of designing a digital system that implements a desired functional
behaviour is referred to as the "synthesis'. Simply we can say, synthesis is the process
of generating a logic circuit from a truth table. For performing this process
automatically, synthesis CAD tools are available.
Let us see, how HDL is useful for the synthesis of a digital circuit. A HDL
program is the input to a synthesis cotnpiler. When this HDL code is passed throngh
initial synthesis tool, a lower-level description of the circuit is generated as an output.
With this process, a set of logic expressions which describes the logic functions
required to realize the circuit is produced. After this, these expressions are
manipulated further by the synthesis tools. The design entry may be in the form of
schematic capture or truth table. The logic expressions produced by the synthesis tool
are not likely to be in an optimal form. It is the task of the synthesis tool to
manipulate the user's design to produce an equivalent but better circuit automatically.
This step of synthesis process is called 'logic synthesis' or 'logic optimization'. Still the
optimized circuit is in the form of logic equations. In the last step of synthesis, it is
determined exactly, how the circuit will be realized in a specific hardware technology.
For executing this task, according to the physical resources available, it is decided how
to implement each logic function given by an expression. In this process a list of
components and their interconnections is derived from the model of a digital system
described in HDL. This list is called a 'netlist'. An integrated circuit or a layout of a
printed circuit board can be obtained by using a gate-level netlist. Thus a logic
synthesis produces a database with instructions on how to fabricate a physical piece of
Copyrighted material
1. 37
Fundamentals of HDL
Introduction
digital hardware. Logic synthesis consists of that part of a digital system design that
can be automated with computer software.
1.7.2 Simulation
In any design process, there are the basic tasks which should be performed in a
sequence. The flow-chart shown in Fig. 1.5 gives this basic sequence of tasks.
START
Initial design
Simulation
Successful design
First, the initial design is generated manually by the designer according to his
views, skills and knowledge. After this, the simulation of the design is carried out
mostly with the help of CAD tools. For the successful simulation, it is necessary to
apply adequate input conditions to the design as well as to the final product which
has to be tested. The simulator checks the designed product under the original
product specifications. This is known that what should be achieved. So if there are
errors, then those are removed and redesigned product is again simulated. This loop is
repeated until the simulation gives problem-free/error-free product. Once the designed
product performs correctly all of its functions, we call it the 'successful design'.
The operation of a digital circuit can be verified fastly and accurately using logic
simulation. There are two types of verification techniques, functional and timing.
The simulation is referred to as 'functional simulation' when all the functions of
the circuit are verified. After completion of successful functional simulation, the
Copyrighted material
Fundamentals of HDL
Introduction
1 - 38
'physical design' step is carried out. Physical design includes the physical location of
each chip on the board and the needed wiring pattern. CAD tools are used for
performing this task automatically. After physical design, the functionality of the
circuit is checked. But, eventhough the functional behaviour is correct, the circuit may
operate more slowly than the desired. The physical wiring on board introduces
resistance and capacitance of electrical signals. The delays are introduced because of
logic circuits such as gates. This reduces the speed of operation of the circuit and thus
lead to inadequate performance. So timing behaviour of the circuit should also be
considered. The simulation which also considers the timing behavior of the circuit is
referred to as 'timing simulation'.
Thus in functional simulation, the circuit logical operation is studied by deriving
the truth table of the circuit independent of timing considerations. In timing
simulation, the circuit operation is studied by considering timing behaviour of the
circuit. For example, the waveforms at the output of the gate are observed when they
respond to a given input.
VHOL
Verilog
Application
Data type
Easy of
learning
libraries and
packages
Supports
packages
and
libraries.
Package can include procedures and
functions and it can be made available
to any module. It allows reusability of
code.
Operators
Copyrighted material
Fundamentals of HDL
Procedures
and Tasks
1 - 39
Introduction
Case
sensitivity
Case insensitive
Case sensitive
Comment
Starts with -
Starts with II
'
Arlthmetl1' opera~o.rs
Operation
Addition
Subtraction
Operator
VHDL
Veritog
..
-
..
-
Multiplication
Division
Modulus
mod
Exponent
..
Concatenation
(& )
., .
.,
..
{.}
''"'' ,
. , tR~l~!ion~I 9Ptra!ors
,
" '
;,
Operation
Operator
VHDL
Verilog
Equality
==
Inequality
f;
!:
Less than
<
<
<=
<=
Greater than
>
>
>:
>:
Equality inclusive
none
---
Inequality inclusive
none
!=:
i..;opynghtE'd ni 1tenal
Introduction
1 -40
Fundamentals of HDL
Operator
Operation
VHDL
Verilog
AND
AND
&
OR
OR
NOT
NOT
NANO
NANO
-(&)
NOR
NOR
- (I)
XOR
XOR
XNOR
XNOR
...A
Operation
Operator
VHDL
Logicai left shift
sll
Verllog
<<
Rotate left
Rotate right
Fundamentals of HDL
1 - 41
Introduction
Review Questions
1. Explain the need of HDL.
A AND B
b. A & B
c. A&&B
d. A AB
e. A _AB
A 2
g. B ror 1
7. What do you mean by modelling style ?
DOD
Copyrighted material
(1 42)
Data-Flow Description
2.1 High Lights of Data-Flow Description
It simulates the system by showing how the circuit signal flow from the
inputs to the outputs.
y
C ---r--....
0
E --1.-"
Listing 2.1 : HDL code for AND-OR circuit - VHDL and Verilog
(2 - 1)
Copyrighted material
Fundamentals of HDL
22
Data-Flow Description
I 12;
Copyrighted material
Fundamentals of HDL
2-3
Data-Flow Description
----- o
B
I
I
------~ ------------~---------
'I
0
D
---------
ll
T0 T1
T2 T3
T4 T5
., .,
., .,
., .,
c"' "'
c
- "'0
0
<ll
"'c
c
0
0
"' "'"'
<ll
<ll
0
0
"'
M
Copyrighted material
Fundamentals of HDL
2-4
Important points
In VHDL we specify delay in time units such as nsec, msec, sec etc. In
Verilog, delay time is specified in screen unit time.
~-~~;~~1~u~~~~a~JIB
In Yerilog, a constant can be declared by its type, such as time or integer.
Digital computers perform various arithmetic operations. The most basic operation,
no doubt, is the addition of two binary digits. This simple ad dition consists of four
possible elementary operations, namely,
0+ 0 = 0
O+l:ol
l+O :o l
l+l:ol02
The first three operations produce a sum whose length is one digit, but when the
last operation is performed sum is two digits. The higher significant bit of this result
is called a carry, and lower significant bit is called sum . The logic circuit which
Copynqhted material
Fundamentals of HDL
2-5
Data-Flow Description
performs this operation is called a half-adder. The circuit which performs addition of
three bits (two significant bits and a previous carry) is a full-adder.
The half-adder operation needs two binary inputs : augend and addend bits; and
two binary outputs : sum and Cout. The truth table shown in Table 2.1 gives the
relation between input and output variables for half-adder operation.
Inputs
A
Outputs
Cout
Sum
Cout
Half
adder
Inputs
Outputs
Sum
For Cout
For Sum
Cout =AB
Sum=AB +AB
=A(f)B
Copyrighted material
Fundamentals of HDL
2-6
Data-Flow Description
end adder;
11
II
II
11
II
endmodule
11'*
The Fig. 2.6 shows 2 x 1 multiplexer. It has two 1-bit inputs : DO an d Dl, a 1-bit
select line S, a 1-bit output : Y and a 1-bit enable signal : En. The input signals DO and
01 are connected to the one input of AND gates : ANDl and AND2, respectively. If
enable signal (En) is low, the output is equal to one of the two inputs depending on
Copyrighted material
Fundamentals of HDL
Data-Flow Description
2-7
DO
D1
2x1
MUX
Enbar or En --!:---' 12
En-----'
the status of select (S) signal. If S = 0, the output is equal to DO and if S = 1 the
output is equal to Dl. The Table 2.2 shows the the truth table for 2 x 1 multiplexer.
Input
Output
s
x
Enbar
DO
D1
end mux2x1;
architecture MUX of mux2x1 is
s ignal Il, 12, 13, 14 : std_logic;
begin
Copyrighted material
Fundamentals of HDL
2 -8
Data-Flow Description
II Assume 10 time units delay for all and, or, not. In Verilog
II we cannot use specific time units, such as nanoseconds.
II The delay here is expressed in simulation screen units.
assign #10 Y
= I3 I I4;
--VHDL
II Verilog
Vector declaration :
signal A: bit_vector (3 downto 0); - VHDL
signal A : bit_vector (0 to 3) ;
-- VHDL
Copyrighted material
Fundamentals of HDL
2-9
Data-Flow Description
DO - - - .
01 _ _ _ _ _ _ ___.
S ---+--------'
Enbar
I
To
.,u
</)
lll
T1
T2
T3 T4
Ts
Te
.,u
.,u
.,u
.,u u.,
</)
c:.
c:
0
0
- -"'
Q)
"'
c:
</)
c:
- -"'
>
Q)
"'
c:
(')
"'
c:
0
<D
"'
"'c:
Tr
</)
c:
"' "'
Ol
II Verilog
wire 10: 3) A ;
II Verilog
In VHDL, downto and to are predefined operators that describe the width of the
vector. Operator downto is used when zeroth element is the least significant element,
and operator to is used when zeroth element is the most significant element. For
example, if A has value 1100 and declaration is signal A : bit_vector (3 down to 0)
then the elements of vector A are :
A(3]
The Fig. 2.8 shows 4 x 1 multiplexer. Each of the four lines, DO to D3, is applied to
one input of an AND gate. Selection lines are decoded to select a particular AND gate.
Copyrighted material
Fundamentals of HDL
2 -10
... '
00
Data-flow Description
14
01
.. '
..
'
..
'
15
,I
D2
......
16
,I
D3
DO
D1
02
D3
17
,I
.. 11
so
.....
S1
::.....
Enbar or EN
4x1
MUX
12
13
so ____
s1 _______.
Enbar - - - - - - - - '
Output
Enbar
so
x
DO
D1
02
03
S1
II>
use leee.std_logic_1164.all;
entity mux4xl ls
port ( D : In std_logic_vector (3 downto O);
S, Enbar: ln std_logic;
Y : out std_logic);
Copyrighted material
2 -11
Fundamentals of HDL
Data-Flow Description
end mux4x1;
architecture MUX of mux4x1 ls
signal 11, 12, 13, 14, 15, 16, 17 : std_logic;
begin
14 or 15 or 16 or 17 after 10 ns;
endMUX;
II
II
II
11
assign #10 Y = 14
assign #10
assign #10
assign #10
assign #10
I 15 I 16 I 17;
Copyrighted material
Fundamentals of HDL
2 -12
Example 2.4 : 2
><
Data-Flow Description
Let .us generalize the multiplication process for a 2 >< 2 multiplier for two unsigned
2-bit numbers : multiplicand A = Al AO and multiplier B = Bl BO. The Fig..2.9 shows
how the multiplication process is carried out.
A1
AO
B1
BO
BOA1
+
B1 A1
P3
B1 AO
P2
I~ ,..'"'""
P1
PMOAO
= BOA1 + B1AO
P1
P2 = B1 A 1 + Carryout of P1
PO
P3 = Carryout of P2
B1 AO
BO A 1
BOAO
Half-adder
P3
P3
P1
PO
Copyrighted material
Fundamentals of HDL
Ill>-
2 -13
Data-Flow Description
Listing 2.5 : HDL code for a 2 x 2 unsigned combinational array multiplier - VHDL
and Verilog.
use ieee.std_logic_1164.all;
entity Arr_Mul is
p ort (A, B: in std_logic_vector (1downto 0);
-- For simplicity propagation delay times are not considered in this example.
P(O) < = B(O) and A(O);
P(l) < = (B(O) and A(1)) xor (B(l) and A(O));
P(2) < = (B(1) and A(1)) xor ((B(O) and A(1)) and (B(1) and A(O)));
P(3) < = (B(1) and A(1)) and ((B(O) and A(l)) a.nd (B(1) and A(O)));
endMULT;
assign P131 = (All i & Bil)) & ((BIOi & Al l ))& (Bill & AIOI)):
endmodule
Fig. 2.11 shows the D latch. The NANO gates 1, 2, 3 and 4 form the basic SR latch
with enable input. The fifth NANO gate is used to provide the complemented inputs.
Copyrighted material
2 - 14
Fundamentals of HDL
Data-Flow Description
EN
(a) D latch
Fig. 2.11
As shown in the Fig. 2.11, D input goes directly to the S input, and its
complement is applied to the R input, through gate 5. Therefore, only two input
conditions exist, either S =0 and R = 1 or S = 1 and R = 0. The truth table for D latch
is as shown in the Table 2.4.
EN
Qn
Qn+1
State
0
1
0
1
x
x
x
Reset
Qn
Set
No change (NC)
As shown in the truth table, the Q output follows the D input. For this reason D
latch is sometimes called transparent latch.
Looking ilt the truth table for D latch with enable input and s implifying Qn+J
functior1 by K-map we get the characteristic equation for D latch with enable input as
Qn<l = EN D +EN Qn. This is illustrated in Fig. 2.12.
Copyrighted material
Fundamentals of HDL
~
2 -15
Data-Flow Description
library ieee;
use ieee.std_logic_1164.all;
entity D_Latch ia
port (D, EN : in std_logic;
a. Obar: buffer std_logic);
-- a and Obar are declared as buffer because they act as
both input and output, they appear on the right and left
hand s ide of s ignal assignment statements. inout or
-- linkage could have been used instead of buffer.
end D_Latch;
Copyrighted material
Fundamentals of HDL
2 -16
Data-Flow Description
A comparator is a special
combinational circuit designed
primarily to compare the relative
magnitude of two binary numbers.
Fig. 2.13 shows the block diagram
of an n-bit comparator. It receives
two n-bit numbers A and B as
inputs and the outputs are A > B,
A = B and A < B. Depending
upon the relative magnitudes of
the two numbers, one of the
outputs will be high.
Inputs
n-bit
comparator
A:>B
A=B
A<B
Outputs
Inputs
Outputs
A> B
A= B
0
0
A< B
Copyrighted material
Fundamentals of HDL
2 - 17
Data-Flow Description
K-map simplification
A >B
1 0
00
01
11
10
00
01
r1
11
10
-;-;;:
0
~t
---
l;
},-
1 J
{.. ~r.~Cl.
A< B
1 0
00
01
11
10
00
Cl
00
01
i@
01
11
~J
11
10
.r?"2)
10
rn
~~ ':
~\
00
,....01_
I
11
~ 1~
1~ ' ....:..JI
..
,,
10
...
;'
1E
1 _..:A;;
~-
ff
0
t~
Fig. 2.14
(A
= B) =
= (Ao
(A< B)
Copyrighted material
Fundamentals of HDL
218
Data-Flow Description
Logic Diagram
A,
A>B
A=B
A<B
Fig. 2.15
Copyn 1nt
11
Fuhdamentals of HDL
...
2 -19
Data-Flow Description
I All i &
I IA11J &
- Billi
I (-AIO I &
A single full-adder is capable of adding two one-bit numbers and an input carry.
In order to add binary numbers with more than one bit, additional full-adders can be
employed. A 4-bit, parallel adder can be constructed using number of full adder
circuits connected in parallel. Fig. 2.16 shows the block diagram of 4-bit parallel adder
using number of full-adder circuits connected in cascade, i.e. the carry output of each
adder is connected to the carry input of the next higher-order adder.
Copyrighted material
Fundamentals of HDL
83
Cout
2 -20
A'J
Full
adder
82
Sum3
81
A2
Full
C3
Data-Flow Description
Full
C2
BO
A1
adder
adder
Sum2
Sum1
C1
AO
Full
adder
Cin
Sumo
It should be noted that either a half-adder can be used for the least significant
position or the carry input of a full-adder is made 0 because there is no carry into the
least significant bit position.
~
Listing 2.8 : 4-bit ripple-carry adder case study - VHDL and Verilog.
Copyrighted material
Fundamentals of HDL
2 - 21
Data-Flow Description
endmodule
Carry Lookahead Adder
The 4-bit adder discussed is implemented using full-adder. In which the carry
output of each full-adder stage is connected to the carry input of the next higher-order
stage. Therefore, the sum and carry outpu ts of any stage cannot be produced until the
input carry occurs; this leads to a time delay in the addition process. This delay is
known as carry propagation delay, whid1 can be best explained by considering the
following addition.
0 1 0 1
+ 0 0 1 1
Addition of the LSB position produces a carry into the second position. This carry,
when added to the bits of the second position (stage), produces a carry into the third
position. The latter carry, when added to the bits of the third position, produces a
carry into the last position. The key thing to notice in this example is that the sum bit
generated in the last position (MSB) depends on the carry tha t was generated by the
addition in the previous positions. This means that, adder will not produce correct
resul t until LSB carry has propagated through the intermediate full-adders. This
represents a time delay that depends on the propagation delay produced in an each
full-adder. For example, if each full-adder is considered to have a propagation delay
Copyrighted material
Fundamentals of HDL
2 -22
Data-Flow Description
of 30 ns, then 53 will not reach its correct value until 90 ns after LSB carry is
generated. Therefore, total time required to perform addition is 90+30 = 120 ns.
Obviously, this situation becomes much worse if we extend the adder circuit to
add a greaier number of bits. If the adder were handling 16-bit numbers, the carry
propagation delay could be 480 ns.
One method of speeding up this process by eliminating inter stage carry delay is
called lookahead-carry addition. This method utilizes logic gates to look at the
lower-order bits of the augend and addend to see if a higher-order carry is to be
generated. It uses two functions: carry generate and carry propagate.
Consider the circuit of the full adder shown in Fig. 2.17. Here, we define two
functions : carry generate and carry propagate.
A;-~~\\
B; - -+--1
P;
G;
=
=
A; EBB;
A; B;
C; +I = G; + P; C;
G; is called a carry generate and it produces on carry when both A; and B; are
one, regardless of the input carry. P; is called a carry propagate because it is
associated with the propagation of the carry from C; to C;.i Now C;.1 can be
expressed as a sum of products function of the P and G outputs of all the preceding
stages. For example, the carriers in a four stage carry-lookahead adder are defined as
follows:
C1
=Go + Po C;n
C2 = G1 + P1 C1 = G1 + P1Go + P1 Po C;n
C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 Go + P2 P1 Po C;n
~=~+~~=~+~G2+~~G1 +~~~~+~~~~~
Copyrighted material
2. 23
Fundamentals of HDL
Data-Flow Description
53
P3 G3
A3
93
52
A2
P2 G2
51
92
A1
P1 G1
91
AO
BO
We can further simplify the design by noting that the sum equation of stage i.
Si
....
Ai xor Bi xor Ci as Si
= Pi xor Gi xor Ci
library ieee;
use ieee.std_logic_1164.all;
entity adder is
Copyrighted material
2 - 24
Fundamentals of HDL
Data-Flow Description
C2 <=
G(1) or (P(1) an d G(O)) or (P(1) and P(O) and C in) aft e r 2*de lay_gt;
C3 < =
G(2) or (P(2) and G(1)) or (P(2) and P(1) and G(O)) or (P(2) and P(1)
and P(1) and Cin) afte r 2*delay_gt;
C4 < =
G(3) or (P(3) and G(2)) or (P(3) and P(2) and G(1)) or (P(3) and P()
and P(1) and G(O)) or (P(3) and P(2) and P(1) and P(O) and Gin)
after 2ctelay_gt;
= A(O) I B(O);
I B(1);
I B(2);
I B(3);
= G(O) I (P(OJ & Gin );
= G(1 ) I (P(l) & G(O)) I (P (1) &
2 - 25
A _ _o_o_o_o_ _ _ _ _ _ _ _ _l.__
10_1_
1 _ _ _ __
0 _ _ _ __
0 _ _0_0_0_0_ _ _ _ _ _ _ _ _~!0_1_1_
Cin
Sum
0010
0000
Cout
i-
4 x 14 = 56 ns
0000
0000
!1011
I0110
Cin - - - - - - - - - - -- - '
0010
0000
>- 4
x 7 = 28 ns
Fig. 2.19 Simulation waveform f or 4-bit adder with a 7 ns gate delaYcopyrighted material
Fundamentals of HDL
2 . 26
Data-Flow Description
The Fig. 2.19 shows the simulation waveform for a 4-bit ripple carry and carry
lookahead adders. In both the cases gate delay is considered as 7 ns. To calculate the
worst delay, i.e., maximum delay, the values for the inputs A, B and Cin are taken as
A = 1011, B = 0110 and Cin = 1. These values cause a change in all the carry-out
signals. In Fig. 2.19 (a), the total delay is 56 ns. Since there are four one--bit adders,
and each has a worst delay of 14 ns (two XOR gates). Th.is total delay equals to the
number of 1-bit adders times the delay of one 1-bit adder.
In Fig. 2.19 (b), the total delay is 28 ns, which is 4 times the delay of a single gate
(7 ns). On increasing the number of input bits of the lookahead adder, the total worst
delay will remain same, i.e., 28 ns.
Review Questions
1. List tlte higlllights of data-flow description.
2. Explain the str11ct11re of the data-flow description with the help of example.
3. Explain the signal declarntion and assignment statements used in VHDL and Verilog.
4. Explain the steps in tlte execution of assignment statements.
5. Explain tlte constant declaration and assignment statement in VHDL and Verilog.
6. Write a VHDL and Verilog description of 4 "1 multiplexer.
7. Write a VHDL and Verilog description of 3 : 8 decoder wit/1 active low enable input.
8. Explain /row gate delays are included in the VHDL and Verilog description.
9. Compare lite worst case delays of 4-bit ripple carry adder and 4-bit carry-looka/1ead adder wit/1 tire
help of simulation waveform.
DOD
Copyrighted material
Behavioral Description
3.1 Behavioral Description Highlights
The behavioral system describes the system by showing how the outputs
behave according to changes in the inputs.
While describing in the behavioral style, it is not necessary to know the logic
diagram of the system; however, it is required to know how the output
behaves in response to change in the input.
In VHDL, the statements inside the process are sequential. In Verilog, all
statements are concurrent.
(3 - 1)
Copyrighted material
Fundamentals of HDL
Ill-
3-2
Behavioral Description
-- signal-assignment statement 1
signal-assignment statement 2
w ith 10 nanoseconds delays.
end process;
end adder;
Verilog Behavioral Description of Half Adder
module half_adder (A, B, Sum , Cout);
input A;
input B;
output Sum;
output Cout;
reg Sum, Cout;
/* Since Sum and Cout are outputs and they are written
inside "always," they should be declared as reg *I
always @(A, B)
begin
#10 Sum = a
b;
A
11
is a bitwise xor logical operator.
11 & is a bitwise logical "and" operator
/* The above two statements are p rocedural
(inside always) signal-assignment statements with
10 simulation screen units delay I
A
end
endmodule
Copyrighted material
Fundamentals of HDL
3-3
Behavioral Description
A ------'
B ~--------------~
Sum - - - - - - - - -
Cout ~-------'
TO
~
"'c
0
0
r
T1
0
"'"'c
~
~
Fig. 3.1
Copyrighted material
3.4
Fundamentals of HDL
Behavioral Description
begin
stl: A :=X;
st2: B := not A;
st3: 01 < = A;
end process ;
One important thing to note that we can label any statement in the VHDL such as
stl, st2 and st3 in the previous description.
statement 1;
statement 2;
else
statement x;
statement y;
end if;
Copyrighted material
3.5
Fundamentals of HDL
Behavioral Description
Example :
if (EN
= '1') then
Q := St;
else
Q:=S2;
end if;
Verilog Syntax :
if (Boolean Expression)
begin
statement 1;
statement 2;
end
else
begin
statement x ;
State ment y;
end
Example:
if (EN== 1)
Q= Sl;
else
Q= S2;
11*
VHDL
if Clk = '1' then
Q: = D;
end if;
Copyrighted material
Fundamentals of HDL
3-6
Behavioral Description
Veri log
if (Clk == 1)
begin
O = D:
end
if Clk is J (high), then the va lue of D is assigned to ou tput Q. If Clk is not high, Q
retains its curren t value, th us simulating a latch.
VHDL syntax :
if en ='00' then
c < = a;
else
c < = 'O';
encl if;
enrl process;
Veri log Syntax :
if (Boolean Expression 1)
begin
statement 1; statement 2; . ..
end
else if (Boolean Expression 2)
begin
statemen t x: statement y; .. .
Copyrighted material
3-7
Fundamentals of HDL
Behavioral Description
end
else
begin
statement a ; statement b; .. .
end
Example
always @ (a, b , en)
begin
if (en == OJ
c = a;
else if (en = = 1}
c = b;
else
c = 0;
end
Here 'en' signal is in sensitivity list. If en = 00, signal 'a' is assigned to output 'c'.
Similarly if 'en'= '01' then 'b' is assigned to 'c' else 'O' value is assigned to 'c'.
111
Copyrighted material
Fundamentals of HDL
3-8
Behavioral Description
begin
if Enbar = 'O' then
if S = '1' then
temp := Dl;
else
temp: = DO;
end if;
Y < = temp;
else
y <= 'Z';
end if;
end process;
endMUX;
reg Y;
always @ (S , DO, D1, Enbar)
begin
if (Enbar == 1)
= 1'bz;
else
begin
if {S)
= D1;
/* This is a procedural assignment. Procedural assignments
are used to assign values to variables declared as regs
(as Y here in this module). Proc,edural statements have to
appear inside always, blocks, initial, tasks, or functions I
else
Y = DO;
end
end
endmodule
Copyrighted material
Fundamentals of HDL
1..
3-9
Behavioral Description
use leee.lltd_logic_1164.all;
entity mux2 x 1 is
port ( DO, D1, S, Enbar : In std_logic;
Y: out std_logic);
end mux2X1;
architecture MUX of mux2x1 hi
begin
process (S , DO, D1, Enbar)
-- S, DO, D1 and Enbar are the sensitivity list of the process.
variable temp: std_logic;
begin
temp := D1;
elslf Enb ar = 'O' and (S
temp := DO;
else
temp := 'Z';
= 'O' ) the n
end If;
Y <=temp ;
end process;
end MUX;
begin
Y
DO;
end
else If (Enbar = = O & S = = 0)
Copyrighted material
3 -10
Fundamentals of HDL
y
Behavioral Description
= 01;
else
Y = l'bz;
end
endrnodule
n-.
The Fig. 3.2 shows the logic symbol for D latch. It has input (D), output Q and
Qbar and active high enables input (En). When En is high, the output Q follows input
D and Qbar is always the invert of Q.
D
En
En
Fig. 3.2 D-latch
...
Listing 3.2 : VHDL code for behavioral description of D-Latch using variable
assignment statements entity DLatch_var is
port ( D, En: in bit;
Q,
end DLatch_var;
architecture DL_Var of DLatch_var is
begin
= '1' then
templ := D;
temp2 :=not templ;
if En
Copyrighted material
3 -11
Fundamentals of HDL
Behavioral Description
end if;
Q <= templ;
port ( D, En : in bit;
Q : buffer bit;
-- Q
end DLatch_sig;
architecture DL_sig of DLatch_sig is
begin
process (D, En)
begin
if En
= '1' then
Q <= D;
signal assignment
signal assignment
end if;
end process;
end DL_sig;
...
input D, En;
output
a, Obar;
reg Q, Obar;
always @ (D, En)
begin
if (En == 1)
bt'gin
O = D;
Obar= - Q;
end
Copyrighted material
Fundamentals of HDL
Behavioral Description
3 -12
end
endmodule
The Table 3.1 gives the comparison between signal and variable.
Parameter
Signal
Variable
Assignment operator
<=
Utility
Represents circuit
interconnects (wires)
Scope
Behavior
Usage
In a package, entity or
architecture. In an entity, all
ports are signals by default.
The Fig. 3.3 shows the simulation waveform of D latch using variable assignment
statement. This waveform correctly describes D-latch. The Fig. 3.4 shows the
simulation waveform of D latch using signal assignment statement. As shown in the
Fig. 3.4, at T = 50 ns, En changes from 0 .to 1, and D is 1 at T = 50 ns. Therefore, new
value for Q is calculated as 1; however, it is assigned at T = 50 + ti. Since at T = 50
ns, value of Q is still 0, Qbar is calculated as 1 using old value of Q.
---ii
En
-:I
Obar
50
100
150
200
250
300
- - - limens
Copyrighted material
Fundamentals of HDL
Behavioral Description
313
En
Q
Obar
50
100
150
200
250
300
- - Tlmens
Fig. 3.4 Simulation waveform of D latch using signal assignment statement
case (control-expression) is
cas e (control-expression)
end
endcase
Copyrighted material
Fundamentals of HDL'
3 14
Behavioral Description
Example :
VHDL
case option is
when "00''. => temp: = a + b;
when "01" => temp := a - b;
w hen ' 10" => temp: = a b ;
when others =>temp : = a I b;
e n d case:
Ve rilog
.,
....
case option
2' bOO : temp = a + b;
= a - b;
. 2' bOl
.. : temp
.
2' b l O: temp = a* b;
d efault : temp = a I b;
endcase
Here, .priority encoded logic means firstly the IF statement executes sequentially,
so depending on the first IF condition that particular input is connected to output.
Next depending on the second IF condition, the another input is passed to output.
Copyrighted material
Fundamentals of HDL
3 -15
Behavioral Description
According to this logic, for this example, three multiplexer are generated by tool. So in
this case hardware is more so the delay generated by logic gates is more; so the. speed
is reduced.
The case statement produces parallel logic. Here, in case statement depenping on
the value of "sel" one of the four inputs is passed to the output. So a single
multiplexer of 4 inputs with two select lines and one outp ut is generate_d by a tool. So
the generated hardware is less, so the delay by logic gates is less; -so the speed is high.
Example:
process (sel, a, b, c, d)
begin
case sel is
when '00' =>op<= a;
when '01' = >op < = b:
when '10' = >op < = c;
when others =>op<= d;
end case;
end process;
Example 3.6 : Behavioral description of a positive edge triggered JK
flip-flop using the case statement
CP
On
On1
0
0
1
1
0
0
1
1
0
1
0
1
0
0
0
0
0
1
1
1
1
0
1
0
1
On+1
On
1
1
1
0
1
0
1
. On
Fundamentals of HDL
316
Behavioral Description
clock. Fig. 3.6 shows the input and output waveforms for positive edge triggering JK
flip-flop.
CP
J -. ....
. ..
K_J
a--,. ._____.
Fig. 3.6 Input and output waveforms for positive edge triggered JK flip.flop
Looking at the truth table for JK flip-flop and simplifying Qn+I function by K-map
we get the characteristic equation for JK flip-flop as Qn+I "' JQ n + KQ n. This is
illustrated in Fig. 3.7.
Li sting 3.5 : HDL code for a positive edge-triggered JK flip-flop using the case
:;tatement-VHDL and Verilog.
use leee.std_logic_1164.all;
entity JK_FF ls
port( JK : In bit_veetor (1 dow nto OJ;
elk : in std_logie;
a. Obar : out b it);
end JK_FF;
arctiltecture Flip_Flop of JK_FF ls
b e gin
Pl : proce ss (elk)
Copyrighted material
Fundamentals of HDL
3 -17
Behavioral Description
case JK Is
when ' 01" =>tempt:= 'O';
when 'tO" => templ := 't';
when oo = >tempt:= tempt;
when "11' =>tempt := not tempt;
end c.ase;
Q <= tempt;
temp2 := not tempt;
Obar < = temp2;
end if;
end proc.ess Pt;
end Flip_Flop;
c.ase (JK)
2'd0: Q = Q;
2'dt: Q = 0;
2'd2: Q = 1;
2'd3: Q = - Q;
endc.ase
Obar=- Q;
end
endmodule
A counter is a register capable of arriving at its clock input. For up counters, the
next state is the increment of the present state. For example, if the present state is 010,
then the next state is 011. For down counters, the next state is the decrement of the
present state. A 3-bit up counter counts from 0 to 7, i.e., it is a mod 8 counter.
Copyrighted material
Fundamentals of HDL
Behavioral Description
3 -1 8
The Fig. 3.8 shows the logic symbol and excitation table for 3-bit counter. It has
two inputs : elk and Reset (active high). On the positive edge of the elk (Clock) input
counter increments only if Reset input is 0 (Low); otherwise counter output is reset to
000.
elk
(Clock)
Reset
Present
state
state
t
I
I
I
I
I
I
H
L
L
L
L
L
L
L
L
xxx
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
AO
A1
3 . bit
elk
A2
counter
Reset
Next
Fig. 3.8
.,..
Listing 3.6 : HDL code for a 3-bit binary counter using the case statement.
S~tement
Description
library ieee;
use ieee.std_logic_1164.all;
entity CT_Case is
port ( elk, Reset : in std_logic;
0: buffer std_logic_vector (2 downto O));
end CT_Case;
architecture Counter_3b of CT_case is
begin
counter : process(clk)
variable temp: std_logic_vector (2 downto 0) := "011";
-- 011 is the initial value, so the counter starts from 100
begin
if rising_ edge (elk) then
if Reset = 'O' then
case temp is
when "000" = >temp: = "001';
when "001" =>temp: = "010";
when "010" = >temp:= "011' ;
Copyrighted material
3 -19
Fundamentals of HDL
Behavioral Description
0 <=temp;
end process counter;
end c ounter_3b;
Verilog 3-Bit Binary Counter Case Statement De scription
module CT_Case (elk, Reset, Q);
input elk, Reset;
output (2:0) O;
reg (2:0) O;
initial
Q
= 3'b010;
begin
case (Q}
3'd0 : Q
3'd1: Q
3'd2 : Q
3'd3 : Q
3'd4 : 0
3'd5 : 0
3'd6 : Q
=
=
=
=
=
=
=
3'd1;
3'd 2;
3'd3;
3'd4;
3'd5;
3'd 6;
3'd7;
3'd 7 : Q = 3'd0;
endcase
end
else
Copyrighted material
Fundamentals of HDL
3-20
Behavioral Description
= 3'b000;
end
endmodule
Verilog has another two types of case : casex and casez. Casex ignores the don't
care (x) values of control expression w.hereas casez ignores the high impedance in
control expression values. For example, in
casex (I)
4bOXX1 :
4'b1XXO :
default :
0 = 1'b0;
0 = 1'b0;
0 = t'bz;
endcase;
All occurrences of X are ignored. Thus, output 0 is 0 when least significant bit of I
is 1 (high), the output 0 is 1 when most significant bit of I is 1 (high) and otherwiJ;e
output is in high impedance state.
Let us see the example of casez :
case z(l)
4'bzzz1 : 0
= 1' bl;
4'bzzz0 : 0
default : 0
= l'bz;
1' bO;
Here, 0 is 1 if, and only if the least significant bit of I is 1, 0 is 0 if and only if
the least significant bit of I is 0 and otherwise output 0 is in high impedance state.
,,._. Example 3.8 ; Verilog description of a priority encoder us ing casex.
Outputs
Do
D1
D2
03
Y1
Yo
x
x
x
x
x
Fundamentals of HDL
3 - 21
Behavioral Description
Table 3.2 shows 0 3 input with highest priority and 0 0 input with lowest priority.
When 0 3 input is high, regardless of other inputs output is 11. The 0 2 has the next
priority. Thus, when 0 3 = 0 and 0 2 = 1, regardless of other two lower priority input,
output is 10. The output for 0 1 is generated only if higher priority inputs are 0, and
so on. The output V (a valid output indicator) indicates, one or more of the inputs are
equal to 1. If all inputs are 0, V is equal to 0, and the other two outputs (Y1 and Y0) of
the circuit are not used .
._
input (0:3) D;
output (1:0) Y;
reg (1:0) Y;
always @ (D)
begin
casex (D)
4'b1000 :
y=
2'b00;
v=
l 'bl
2'bzz; V
= l'bO
II DO-D3 = 0000
endcase
end
endmodule
Copyrighted material
3 22
Fundamentals o f HDL
Behavioral Description
Example;
For i in 1 to 10 loop
i_squared(i) := i i;
end loop;
This for loop executes 10 times whenever execution begins. Its functior;l is to
calculate the squares from 1 to 10 and insert them into the i_squ ared signal array. The
index variable i starts at the leftmost (lower) value (1) of the range and is incremented
until the rightmost (higher) value (10) of the range. In each iteration index is
incremented by 1. When the value of index is greater than the higher value, the loop
is terminated.
In some languages, the loop index (in this example, i) can be assigne9. a value
inside the loop to change its value. VHDL does not allow any assignment to the loop
index. VHDL locally declares the index; it is not necessary to declare variable i
explicitly in the process, function or procedure. If another variable of the same name
exists in the process, function or procedure, then these two variables are treated as
separate variables.
We can use downto cause to create a descending range. Here is the example :
for i in 10 downto 1 loop
i_squared (i) := 1 1;
e nd loop;
Note : for single statement in the for loop we can omit begin and end.
Example:
intege r i;
for (i = 1; i < = 10; i = 1
+ 1)
begin
i_squared Iii = i i;
end
In the above example, the initial_assignment (i = 1) specifies the initial value of the
loop index. The condition specifies the condition when loop must be terminated. As
long as the condition is true, the statements in the loop are executed. The
step-assignment (i = i + 1) specifies how to modify index; it can be incremented or
decremented.
Copyrighted material
Fundamentals of HDL
3 - 23
Behavioral Description
This loop executes all the statement written in the while loop body as long as the
condition is true. When condition is false, program exits the loop.
VHDL while-loop
Count: = O;
Result := O;
While (Count < 10) loop
Count: = Count + 1;
Result : = Result + Count;
end loop;
Verilog While-Loop
Count= O;
Re sult = O;
While (Count < 10)
begin
Count = Count + 1;
Result = Result + Count;
end
Note : Instead of direct value we can use variable to specify the termination
condition. For example, we can write, while (Count < x). In this case,
In Verilog, the repeat statement executes the loop for fixed number of times. It
cannot be used to loop on a general logical expression, i.e., no condition is allowed in
repeat.
Example :
i = O; Result = O;
repeat (10)
begin
Result
end
= Result +
i;
Copyrighted material
Fundamentals of HDL
3. 24
Behav!oral Description
clock = 1'bO;
forever # 10 clock = -clock;
end
In this example, clock first gets initialized to 0 and then toggles every 10 time
units.
3.4.5.5 VHDL Next and Exit
The VHDL supports, two sequential statements next and exit associated with the
loop. The exit causes program to exit the loop whereas next causes the program to
jump to the end of the loop, skipping all statements written between next and end
loop. The index is incremented and if its value is still within the range of the loop, the
loop is repeated, otherwise the program exits the loop.
process (A, B}
constant max_limit: inte ger := 100;
begin
next;
else
done(i} :
= true;
end if;
In the above example, the for loop multiplies the numbers in arrays A and B and
puts the results in array mu!. This behavior continues whenever the flag is in array
done is not true. If the done flag is already set for this value of index i, then the next
statement is executed. It skips the further statements and goto next iteration. If value
of i is still within the range of loop i.e. less than max_limit. The loop is repeated.
Copyrighted material
Fundamentals of HDL
3 -25
Behavioral Description
entity count_ones is
port (Din : in std_logic_vector (7 downto 0);
ones : out integer range 0 to 8);
end count_ones;
arehltecture count of count ones ls
begin
process (Din)
variable temp : integer range 0 to 8;
begin
temp:= O;
for i in O t o 7 loop
if(Din(i) = '1 ') then
temp: = temp+ 1;
end if;
end loop;
ones < = temp;
end process;
end count;
Verilog ones counter description
module count_ones (Din, Ones)
input (7 : OJ Din;
output (2 : OJ ones;
reg 12 : OJ ones;
integer i;
initial
ones = 3'b000;
always @ (Din)
begin
for (i
= O; i
< 8; i
= i + 1)
begin
if (Din [iJ = = 1)
Copyrighted material
Fundamentals of HDL
3 - 26
Behavioral Description
begin
ones = ones
end
end
end
endmodule
1;
integers~VHDL
and
i+
1;
end loop;
y <= i;
end proce11;
end fact;
Copyrighted material
Fundamentals of HDL
3 - 27
Behavioral Description
while (i < = N)
begin
Y = i Y;
i
= i + l;
end
end
endmod ule
Case study : Booth Algorithm
0 1 0 0 0 0 (16)
- 0 0 0 0 1 0 (2)
0 0 1 1 1 0 (14)
Copyrighted material
Fundamentals of HDL
Behavioral Description
3-28
-1 times the shifted multiplicand is selected when moving from 0 to 1, +1 times the
shifted multiplicand is selected when moving from 1 to 0, and 0 times the shifted multiplicand
is selected for none of the above case, as multiplier is scanned from right to left.
We have to assume an implied 0 to right of the multiplier LSB. This is illustrated
in the following examples.
Example : Recode the multiplier 1 0 1 1 0 0 for Booth's multiplication.
Solution :
0 1
1 0 0
- 1+1 0-1
~ltiplier
0 0
Recoded multiplier
1 0 0 1 .r-:ultiplier
0 -1 0 +1 -1
Recoded multiplier
The Fig. 3.9 shows the Booth's multiplication. As shown in the Fig. 3.9, whenever
multiplicand is multiplied by - 1, its 2's complement is taken as a partial result.
Multiplier : O O 1 1 O O
Multiplicand : O 1 O O 11.
Recoded multiplier : 0 + 1 0 - 1 0 0
Multiplication :
0
+1
-1
()'
f-
0
0
Copyrighted material
Fundamentals of HDL
Behavioral Description
3 - 29
0
1
-1
-1
(+14)
(- 5)
Multiplicand
Multiplier
Recoded Multiplier
Multiplication :
0
0
-1
+1
0
-1
O 2's complement of the multiplicand
(-70)
The same algorithm also can be used for negative multiplier and negative
multiplicand. This is illustrated in the following example.
Example : Explain the following pair of signed 2's complement numbers.
Multiplicand : 1 1 0 0 1 1 (-13)
Multiplier
: 1 0 1 1 0 0 (-20)
Solution :
0
+1
- 1
-1
Multiplier
Recoded Multiplier
Multiplication :
- 1
+1
-1
Multiplicand
0
Recoded Multiplier
~~~~~~~~~~~~~~~~~~~~~~~~~-
0
0
<-
(260)
Copyrighted material
3 - 30
Fundamental s of HDL
Behavioral Description
Hardware Implementation
The Booth's algorithm can be implemented as shown in the Fig. 3.10. The circuit is
similar to circuit for positive number multiplication. It consists of n-bit adder, shift,
add subtract control logic and four registers, A, B, Q and Q_1. As shown in the
Fig. 3.10 multiplier and multiplicand are loaded into register Q and register B,
respectively, and register A and Q _1 are initially set to 0.
- - - n-bit bus
n
Add I Sub
Shift, Add
and subtract
Control Logic
L____....,.__.!;E;!!n~ab~le;_J-,___-;;:ddj~;t,;;:ctl
Add/subtract
Enable
.___....,..._ __,
Shift Right
n-Bit Adder
,,
Initial settings : A -
, , r----------------
o and 0_1 = O
The n-bit adder performs addition of two inputs. One input is the A register and
other input is multiplicand. In case of addition, Add/sub line is 0, therefore Cin,;. 0
and multiplicand is directly applied as a second input to the n-bit adder. In case of
subtraction, Add/sub line is 1, therefore Cin =1 and multiplicand is complemented
and then applied to the n-bit adder. As a result, the 2's complement of multiplicand is
added in the A register.
The shift, add and subtract control logic scans bits Q 0 and Q_ 1 one at a time and
generates the control signals as shown in the table 3.3. If the two bits are same
(1 - 1 or 0 - 0), then all of the bits of the A, Q, and Q _ 1 registers are shifted to right
1 bit without addition or subtraction (Add/subtract Enable = 0). If the two bits are
differ, then the multiplicand ( B-register) is added to or subtracted from the A register,
depending on the status of bits. If bits are Q 0 = 0 and Q_1 = 1 then multiplicand is
added and if bits are Q 0 = 1 and Q . 1 = 0 then multiplicand is subtracted. After
addition or subtraction right shift occurs such that the leftmost bit of A ~An -I) is not
Copyrighted material
Fundamentals of HDL
3 - 31
Behavioral
De~cription
only shifted into A n-l, but also remains in A n-t This is required to pres.erve the sign
of the number in A and Q. It is known as an arithmetic shift, since it preserves the sign
bit.
Qi
Q.1
-Add/sub
Add/Subtract Enable
Shift .
Table 3.3 Truth table for shift, add and subtract control logic
The sequence of events in Booth's algorithm can be explained with the help of
flowchart shown in Fig. 3.11.
- o
0 .1 -
B -
Multiplicand
Q Multiplier
Count n
= 10
= 01
= 11
= 00
A -A- B
A - A +B
Arithmetic Shift
Right: A,
0_ 1
Count Count - 1
a.
No
3 . 32
Fundamentals of HDL
Behavioral Description
Let us see the multiplication of 4-bit numbers, 5 and 4 with all possible
combinations.
CASE 1 : Both Positive ( 5x 4)
(5)
Q..1
Operation
0 0 0 0
0 1 0 0
Initial
Step 1 :
0 0 0 0
0 0 1 0
Step 2 :
0 0 0 0
0 0 0 1
Step 3 :
1 0 1 1
0 0 0 1
A +- A-8
1 1 0 1
1 0 0 0
0 0 1 0
1 0 0 0
A +-A+ 8
0 0 0 1
0 1 0 0
Multiplicand (8) +- 0 1 0 1
Steps
Step 4 :
Result
0 0 0 1
0 1 0 0
= + 20
Multiplier (Q)
...
11 0 0 (- 4)
Q_I
Operation
0 0 0 0
1 1 0 0
Initial
Step 1 :
0 0 0 0
0 1 1 0
Step 2:
0 0 0 0
0 0 1 1
Step 3:
1 0 1 1
0 0 1 1
1 1 0 1
1 0 0 1
1 1 1 0
1 1 0 0
Steps
Step 4 :
Result :
1 1 1 0
1 1 0 0
=-
A +-A -
Copyrighted material
Fundamentals of HDL
Behavioral Description
3 - 33
Multiplier(Q)
Q..,
Operation
0 0 0 0
0 1 0 0
Initial
Step 1 :
0 0 0 0
0 0 1 0
Step 2 :
0 0 0 0
0 0 0 1
Step 3:
0 1 0 1
0 0 0 1
A.-A-B
0 0 1 0
1 0 0 0
1 1 0 1
1 0 0 0
A <- A+B
1 1 1 0
1 1 0 0
Multiplicand(B)
Steps
Step 4 :
Result:
1 1 1 0
1 1 0 0
<-
0 1 0 0 (4)
- 20
Multiplier(Q)
<- 1 1 0 0 (- 4)
Q_,
Operation
0 0 0 0
1 1 0 0
Initial
Step 1 :
0 0 0 0
0 1 1 0
Step 2 :
0 0 0 0
0 0 1 1
Step 3 :
0 1 0 1
0 0 1 1
A <- A-B
0 0 1 0
1 0 0 1
Step 4 :
0 0 0 1
0 1 0 0
Result :
0 0 0 1
Steps
....
1 0 1 1 (-5)
0 1 0 0
= + 20
Copyrighted material
Fundamentals of HDL
3. 34
Behavioral Description
-- B : Multiplicand 0 : MUitiplier
process (B, 0)
variable 001 : signed (1 downto O);
variable A : signed (3 downto O);
variable 0_1 : unsigned (0 downto O);
begin
case temp is
when "1 0" = >A := A-B;
when "01'' =>A :=A + B;
when others = > null;
end case;
0 _1 := 0(0);
0 : = 0 srl 1; -- logical shift 0 of one position to the right
0(3) := A(O);
end loop;
Result< = A & O;
end process;
end Mul_Booth;
A= 4'b0000;
Copyrighted material
Fundamentals of HDL
3 - 35
Behavioral Description
0 _1 = 1'b0;
for (i = O; i < 4; i = i
+ 1)
be gin
11 concatenation
case (001)
2'd2 : A = A - B;
2'd1 : A = A +B;
= O(OJ;
0:=0>>1;
0(3] = A(O J;
A = A >> l ;
A [7[ = A [6];
th e shift. *I
e nd
Result = {A, O}
11 concatenation
end
endrnodule
Review Questions
1. List tlte l1ighligltts of behavioral description.
ODO
Copyrighted material
(3 - 36)
Co y1 Jht
rn
1I
Structural Description
4.1 Highlights of Structural Description
Basic Verilog package recognizes the gates; however basic VHDL package
does not recognize gates. In VHDL, we have include one or more libraries,
packages or modules that have the gate description.
(4 - 1)
Copyrighted material
Fundamentals of HDL
4-2
Structural Description
The and2 components has two inputs : 11 and 12 and one output 01. Once the
component is declared we can use the same component one or more times in the
system description.
The instantiation part of the code maps the generic inputs/outputs to the actual
inputs / outputs of the system. For example, the statement and2 port map (A, B, Cout);
maps A to input I1 of and2, input B to input 12 pf and2, and output Cout to output
01 of and2. This mapping means that the logic relationship 'between A . B and Cout is
the same as between Il, 12 and 01.
....
end component;
component and2
p ort ( 11, 12 : in s td_!ogic;
01 : out std_logic);
end component ;
begin
Statements instantiation
Xl : xor2 port map (A, B, Sum);
A1 : and2 port map (A, B, Cout );
end adder;
Copyrighted material
Fundamentals of HDL
4-3
Structural Description
The VHDL part of listing 4.1., does not give the complete code for half_adder. It
does not specify the function of the component::' and2 and xor2. To specify and2 as an
AND gate or xor2 as an XOR gate, we have to link the entity having the same name
as component which specifies the relationship between 11, 12 and 01 as AND gate or
XOR gate, respectively. This is illustrated in Listing 4.2.
~
4.4
Fundamentals of HDL
Structural Description
end component;
component and2
port ( 11, 12 : ID std_logic;
01 : out std_logic);
end component;
begin
As mentioned earlier, basic Verilog recognizes logic gates. The Fig. 4.1 ~hows all
the gates recognized by the Verilog. Like VHDL, the statements in the structural
Verilog are concurrent; they are event driven and their order of appearance in the
module is irrelevant.
--t>Ibuf
-I>-
=[>--
not
nor
xor
and
=D-
:=)~
nand
xnor
4.3 Binding
Binding is nothing but the linking of entity to architecture and .coml?onent to
entity in the VHDL. In Verilog, the binding means linking of one module to another
module.
Copyrighted material
Fundamentals of HDL
....
4.5
Structural Description
end gate;
entity ent la
port (A, B : in std_logic;
sum, cout : out std_logic);
end ent;
architecture arch of eht la
component andg ate
Copyrighted material
Fundamentals of HDL
4.5
Structural Description
end component;
b egin
andgate p ort map (A, B, Cout);
end arch;
a'rfo
moaule in VHDL.
entity' ent is
en d ent;
architeeture arch of ent is
end arch;
The HDL simulator generates a library named work every time it compiles HDL
code. We can bound this library to another module by including following statement
in the module.
Here, the entity to be bound to the module is andgate; andgate has an architecture
by the name of gate, and aU information in this architecture is visible to the module in
which the above use statement is written.
*
binds the architecture xor2_7 of the entity ent to the component 'XOr.2. Because of
this binding, component xor2 behaves as a two-input XOR gate with a propagative
delay of 7ns. Similarly, the statement :
Lopynghtcd material
Fundamentals of HDL
4.7
Structural Description
binds the architecture and 2_4 of the entity ent of the component and2. Because of
this binding, component and2 behaves as a two-input AND gate with a propagative
delay of 4ns.
In listing 4.6, it is assumed that entities ent and half_adder are stored in the same
directory, i.e., their path is same. In case of different paths we have to specify the path
of the library work in the for all statement.
.,...
01<=11xor12;
end xor2_7;
architecture and2 4 of ent is
begin
01 < = 11 and 12 after 4 ns;
end and2_4;
compile the above code and store it in a known location.
module half_adder
library leee;
use leee.std_logic_1164.all;
entity half_adder is
port (A, B: in std_logic;
Sum, Cout : out std_logic);
end half_adder;
architecture adder of half_adder ii
component xor2
port ( 11, 12 : in std_logic;
01 : out std_logic);
Copyrighted material
fundamentals of HDL
4-8
Structural Description
end component;
component and2
port ( I1, 12 : in std_logic;
01 : out std_logic);
end component;
for all : xor2 use entity work.ant (xor2_7);
for all: and2 use entity work.ent (and2_4);
begin
)Ill>
Sum[O] is the output of the two input XOR gate with A[O) and B[O] as the
inputs.
Cout[O] is the output of the two input AND gate with A[O] and B[O] as the
inputs.
Copyrighted material
Fundamentals of HDL
u
....
4-9
Structural Description
Example 4.1 : VHDL code for inverter, AND, OR, XOR, NOR and NANO
gates.
Listing 4.8 : VHDL code for inverter, AND, OR, NOR, NANO XOR gates
-- one input gates ------------------------- ---------------------------------------------- ------------library ieee;
use ieee.std_logic_1164.all;
entity one_input is
port ( 11 : in std_logic;
01 : out std_logic);
end one_input;
architecture inv_4 of one_input is
begin
end inv_4;
architecture inv_7 of one_input is
begin
01 < = not 11 after 7 ns;
end inv_7;
-- two input gates -----------------------------------------------------------------------------------library ieee;
use ieee.atd_logic_1164.all;
entity two_input is
port ( I1, 12 : in std_logic;
01 : out std_logic);
end two_input;
architecture xor2_4 of two_input is
begin
01 < = I1 xor 12 after 4ns.; -- 2-input exclusive-or with 4-ns delay
end xor2_4;
architecture and2_4 of two_input is
begin
01 < = I1 and 12 after 4ns;
end and2_4;
architecture and2_7 of two_input is
begin
01 < = I1 and 12 after 7 ns;
end and2_7;
Copyrighted material
Fundamentals of HDL
4 -10
Structural Description
end or2_4;
architecture or2_7 of two_ input is
begin
01 < = 11 or 12 after 7 ns; -- 2-input or gate with 7-ns delay.
end or2_7;
architecture nor2_7 of two_input la
begin
01 < = 11 nor 12 after 7 ns; -- 2-input nor gate with 7-ns delay.
end nor2_7;
architecture nand2_7 of two_input is
begin
01 <= 11nand12 after 7 ns; -- 2-input nand gate with 7-ns delay.
end nand2_7;
-- three input gates --------------------------------------------------------------~---------------library ieee;
use ieee.std_logic_1164.all;
entity three_input Is
port ( 11, 12, 13 : in std_logic;
01 : out std_logic);
end three_input;
architecture and3_ 4 of three_input Is
begin
begin
end and3_7;
architecture or3_ 4 of three_ input Is
begin
begin
Copyrighted material
4. 11
Fundamentals of HDL
01 <
= I1 or 12 or 13 after 7 ns;
Structural Descriptio n
end or3_7;
four input gates ------------------------------------------------------------- ------------- ------library iee e ;
u se ieee.std_logic_1164.all;
entity four_input is
port ( 11, 12, 13, 14 : in std_logic;
01 : out std_logic);
emi"four_input;
architecture or4_4 of four_input is
begin
lJJ. .
2x 1
MUX
Enbar or En _ __,..___... 12
En----~
....
Listing 4.9 : HDL description of a 2x1 multiplexer with active low enable.
library leee;
use ieee.std_Jogic_1164.all;
entity mux2 x 1 is
port (DO, Dl, S, Enbar: 1n st d_logic;
Y : out std_!ogic);
Copyrighted material
4 -12
Fundamentals of HDL
Structural Description
endmux2 x 1;
architecture MUX of mux2 x 1 is
-- Components declaration
component and3
port ( Il, 12, 13: In std_logic;
01 : out std_logic);
end component;
Only different types of components need be declared.
Since the multiplexer has two identical AND gates,
only one is declared.
component or2
port ( Il, 12 : in std:...logic;
01 : out std_logic);
end component;
component inv
port ( I1 : in std_logic;
01 : out std_logic);
end component;
signal 11, 12, 13, 14 : std_logic;
for all : and3 use entity work.three_input (and3_7);
for all : inv use entity work.one_input (inv_7);
for all: or2 use entity work.two_input (or2_7);
be~
-- instantiation
Al : and3 port map (DO, 11, 12, 13);
A2 : and3 port map (Dl, S, 12, 14);
lVl : inv port map (S, Il);
lV2 : inv port map (Enbar, 12);
OR : or2 port map (13, 14, Y);
endMUX;
Copyrighted material
Fundamentals of HDL
4 -13
A decoder is a multiple-input,
multiple-output logic circuit which
n-dala
converts coded inputs into coded
inputs
outputs,
where the input and output
n
Possible
n:2
n
codes are different. The input code
2 outputs
Decoder
generally has fewer bits than the output
Enable
code. Each input code word produces a
inputs
different output code word, i.e., there is
one-to-one mapping from input code
Fig. 4.3 General structure of decoder
words into output code words. This
one-to-one mapping can be expressed in a truth table.
The Fig. 4.3 shows the general structure of the decoder circuit. As shown in the
Fig. 4.3, the encoded information is presented as n inputs producing 2" possible
outputs. The 2" output values are from 0 through 2" - 1. Sometimes an n-bit binary
code is truncated to represent fewer output values than 2". For example, in the BCD
code, the 4-bit combinations 0000 through 1001 represent the decimal digits 0-9, and
combinations 1010 through 1111 are. not used. Usually, a decoder is provided with
enable inputs to activate decoded output based on data inputs. When any one enable
input is unasserted, all outputs of decoder are disabled.
A
Abar
Bbar
Y0 Abar Bbar
Enable (EN)
Fundamentals of HDL
4 -14
Structural Description
A decoder which has an n-bit binary input code and a one activated output
out-of-2" output code is called bin ary decoder. A binary decoder is used when it is
necessary to activate exactly one of 2 outputs based on an n-bit input value.
Fig. 4.4 shows 2 to 4 decoder. Here, 2 inputs are decoded into four outputs, each
output representing one of the minterms of the 2 input variables. The two inverters
provide the complement of the inputs, and each one of four AND gates generates one
of the minterms.
The Table 4.1 shows the truth table for a 2-to-4 decoder. As shown in the truth
table, if enable input is 1 (EN = 1), one, and only one, of the outputs Y0 to Y3, is
active for a given input. The output Y0 is active, i.e. Y0 = 1 when inputs A = B = 0,
the output Y1 is active when inputs A = 0 and B = l. If enable input is 0, i.e. EN = 0,
then all the ou tputs are 0.
Inputs
Outputs
EN
Y3
Y2
Y1
Yo
0
0
entity decoder2 x 4 is
port ( A, B, En : in std_logic;
Y : out std_logic_vector (3 downto 0));
end decoder2 x 4;
architectu re decotjer of decoder2x4 hi
component inv
port ( 11 : in std_logic;
01 : out std_logic);
end component;
component and3
port ( 11, 12, 13 : in std_logic;
01 : out std_logic);
Copyrighted material
Fundamentals of HDL
4-15
Structural Description
end component;
for all : inv use entity work.one_input (inv_ 4);
for all: and3 use entit y work.three_input (and3_4);
-- Signal Declaration
signal Abar, Bbar : std_logic;
begin
The Fig. 4.5 shows the 2x 4 decoder with tri-state output. For this decoder when
enable (En) input is low, the outputs are in high impedance state, i.e. tri-state.
Copyrighted material
4 -16
Fundamentals of HDL
Structural Description
Bbar
Abar
>---
Y1
>---
v2
En
Fig. 4.5 2x 4 decoder with tri-state output
The Table 4.2 shows the truth table for a 2x4 decoder with tri-state output.
Inputs
Outputs
En
Y3
Y2
Y1
YO
.1
Iii>
Copyrighted material
Fundamentals of HDL
4-17
Structural Description
begin
temp:= 11;
else
temp := 'Z';
end if;
01 <=temp;
Copyrighted material
4 - 18
Fundamentals of HDL
Structural Description
In VHDL, we have to write a description of. the tri-state buffer gate. However,
Verilog has built-in buffers. The Fig. 4.6 shows the buffers supported by Verilog.
in
buff1:
---1>-~
Enable
notif1 :
in~ out
Enable
in
out
--t:;.- out
~
buffO:
Enable
notito :
in - - - { >.
__J
out
Enable
Copyrighted material
Fundamentals of HDL
4 -19
Structural Description
Second Half-Adder
--t,....,_,,..,"'""
B _.;.:..+;..,_.....,fl
Copyrighted material
Fundamentals of HDL
4-20
Structural Descriptli:m
...
end adder;
Copyrighted material
Fundamentals of HDL
Structural Description
4 -21
II Half-Adder Module
module HA (A, B, S, C);
Input A, B;
output S, C;
xor (S, A, B);
and (C, A, B);
endmodule
S (Set)
0 __,
R (Reset)-~
CASE 1 : S
=1 and R =0
Fundamentals of HDL
4-22
Structural Description
R (Reset),- ---<
CASE 2 : S 0 and R ,. 1
S (Set)
= 0 and R =0
Initially, Q = 1 and Q= 0
CASE 3 : S
S (Set)
Q= 1
CASE 4 : S = 1 and R
=1
When R and S both are at logic 1, they force the outputs of both NOR gates to the
low state. (Q=O and Q= O). So we call this an indeterminate or prohibited state, and
represent this condition in the truth table as an asterisk (). This condition also violates
the basic definition of a latch that requires Q to be the complement of Q. Thus in
normal operation this condition must be avoided by milking sure that l 's are not
applied to both the inputs simultaneously.
Fig. 4.10 shows the symbol and truth table for SR latch. Looking at Fig. 4.10 we
can summarize the operation of SR latch as follows :
Copyrighted material
Fundamentals of HDL
With both inputs low, the output does not change and latch remains latched
in its last state. This condition is called inactive state because nothing
changes.
When R input is low and S input is high, the Q output of latch is set (at
logic 1).
When R input is high and S input is low, the Q output of latch is reset (at
logic 0).
When R and S inputs both are high, output is unpredictable. This is called
indeterminate condition.
(a) Symbol
.,..
4-23
Qn
Q n+1
x
x
State
No change(NC)
Reset
.Set
Indeterminate
Fig. 4.10
Listing 4.15 : HDL description of an SR latch with NOR gates.
end SR_Latch;
architecture Latch of SR Latch is
. Here
and Obar signals are declared as buffer; however these signals are
-- mapped with in and out signals. Some simulators may not allow such
-- mapping. In this case, change all in and out to buffer.
Copyrighted material
Fundamentals of HDL
4-24
Structural Description
component nor2
port ( 11, 12 : in std_logic;
01 : out std_logic);
end component;
for all : nor2 use entity work.two_input (nor2_7);
b egin
n l : nor2 port map (S, Q, Obar);
Copyrighted material
Fundamentals of HDL
4 25
Structural Description
end component;
for all: n and2 use entity work.two_input (nand2_7);
signal Sl, R, Rl : std_logic;
begin
endmodule
$1
CP
R1
O (Q bar)
Copyrighted material
Fundamentals of HDL
CP
Structural Description
4 - 26
CP
a.
Cn1
J1.
J1.
J1.
J1.
J1.
J1.
J1.
J1.
0
0
x
x
x
x
, ,
0
Stata
No cllange(NC)
Reset
Set
Indeterminate
No change(NC)
The Fig. 4.12 shows the logic symbol and truth table of clocked SR flip-flop.
Listing 4.17 : HDL description of a SR-Flip-Flop-VHDL and Verilog.
IJI>
S, R, CP : in std_logic;
Q,
end SR_FF;
architecture FF of SR FF is
-- Here Q and Obar signals are declared as buffer; however these signals are
-- mapped with in an d out signals. Some simulators may not allow such
-- mapping . In this case, change all in and out to buffer.
component nand2
port (
11, 12 : in std_logic;
01 : out std_logic);
on d component;
for a ll : nand2 use e ntity work .two_input (nand2_7);
signal Sl, Rl : std_logic;
begin
Copyrighted material
Fundamentals of HDL
Structural Description
4 -27
Q,
Obar);
input S, R. CP;
output
a. Obar;
Ill
CP
CP
Q n+1
.n.
I~
an
CP ~
1
lI
D~
1:
a~
Fundamentals of HDL
~
4 -28
Structural Description
Copyrighted material
4-29
Fundamentals of HDL
Structural Description
CP
On
O n+1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
On+1
On
On
use
leee.std_logi~_1164.all;
entity JK_FF Is
port ( J, K, CP : in std_logic;
Q, Obar : buffer std_logic);
-- Q , Obar are declared buffer b e cause they be h ave as input and output.
end JK_FF;
Copyrighted material
Fundamentals of HDL
4. 30
Structural Description
architecture FF of JK FF ill
-- Here 0 and Obar signals are declared as buffer; however these signals are
-- mapped with in and out signals. Some simulators may not allow such
-- mapping. In this case, change all in and out to buffer.
component nor2
port ( 11, 12 : in std_logic;
0 1 : out std_logic);
end component;
component and3
port ( 11, 12, 13 : in std_logic;
01 : out std_Jogic);
end component;
for all : nor2 use entity work.tw o_input (nor2_7);
for all : and3 use entity work.three_input (and3_7);
signal R, S
begin
Verilog JK_FF
module JK_FF (J, K, CP, 0, Obar);
input J, K, CP;
output 0 , Obar;
nor (Obar, S, 0);
nor ( Q, R, Obar);
and (R, 0 , K, CP);
and (S, CP, J, Obar);
endmodule
is more than two bits, the truth tables and hence the circuit becomes more
complicated. Thus, we can implement 3-bit comparator with some different approach.
In this approach 3-bit adder is used to generate AeqB, AgtB and AltB signals.
Copyrighted material
Fundamentals of HDL
Structural Description
4 - 31
Consider, there are two numbers A and B, each of n bits. Let us assume A is greater
than B. This condition can be written as
A>B=>A - B >0
: B+ 1 is 2's complement of B
The above equation says that if A is greater than B, then the sum of_A and B
should be greater than ln ln - l 1 2 11 10 . If n adder is used to add A and B, and the
final carryout is 1 then we can say that A + B > ln 1" _ 1 12 11 10 , i.e. A > B.
If this condition is not satisfied, we can say that A
equality by checking the following equation.
A+ B = ln ln -
12 11 lo
If A > B and A = B, both conditions are not true then we can say that A < B.
61
A2
BO
A1
AO
Bbar2
Full
Adder
AgtB
C2
Full
Adder
Sum2
Sum1
AltB
AeqB
C1
Full
Adder
Sumo
Copyrighted material
Fundamentals of HDL
4-32
Str;uctural.Description
The listing 4.20 shows the HDL code for 3-bit comparator. The HDL code for a
full-adder has already written in example 4.5.
..,.
4. 33
Fundamentals of HDL
Structural Description
A simple SRAM (static RAM) cell consists of a latch. It has a tri-state output. If the
Sel line of the cell is low, the output of the cell is in high, impedance state. The R/W
(Read/ Write) signal controls the operation of the cell. If RI W is high, the cell
performs read operation; otherwise it performs write operation. The Table 4.3 shows
the excitation -table for memory cell.
Sel
R/W
Din
En
en
Dout
Din
Din
Din
Copyrighted material
4 . 34
Fundamentals of HDL
Structural Description
K-map simplification
For En
ForD
0
:. 0 = Din . R/Vll
En = Sel. R/Vll
ForCn
RJW
SeI
Cn
Dout
Oout = Q (for Cn = 1)
Oout Z (for Cn 0)
= Sel. R/Vll
Fig. 4.17
The Fig. 4.17 shows the logic symbol and logic diagram of SRAM cell.
SRAM
Cell
Dout
Oout
R/Vll
(RWb ar)
Set
(a) Logic symbol
Fig. 4.18
The listing 4.21 shows the HDL code for SRAM cell. The code is linked with the
entity D-latch in example 4.7 by statement :
for all : D_Latch use entity work. D_Latch (Latch) ;
Copyrighted material
Fundamentals of HDL
4-35
Structural Description
entity memory ls
port ( Sel, RW, Din: in std_logic;
Dout: buffer std_logic );
end memory;
architecture mem_cell of memory is
component and2
port ( 11, 12 : in std_ logic;
01 : out std_logic);
end component;
component inv
port ( 11 : in std_logic;
01 : out std_logic);
end component;
component bufifl
port ( 11, 12 : in std_logic;
01 : out std_logic);
end component;
component D_Latch
port ( Il, I2 : in std_logic;
01, 02: buffer std_logic);
end component;
for all: and2 use entity work.two_input (and2_4);
for all: inv use entity work.one_input (inv_4);
for all: or2 use entity work.two_input (or2_4);
for all: bufifl use entity work.two_input (bufifl);
for all : D_Latch use entity work.D_latch (Latch);
signal RWbar, D, En, Q : std_logic;
begin
a, open);
Copyrighted material
4- 36
Fundamentals of HDL
Structural Description
D_Latr..il
lnp uts
Combinational
circuit
Outputs
(Combinational
componenl)
Memory
elements
Present state
(Sequential
component)
14-
Nexistale
Sequential circuit
j
Copyrighted material
Fundamentals of HDL
.37
Structural Description
The information stored in the memory elements at any given time defines the
present state of the sequential circuit. The present state and the external inputs
determine the outputs and the next state of the sequential circuit. Thus we can specify
the sequential circuit by a time sequence of external inputs, internal states (present
states and next states), and outputs.
Sr. No.
Comblnatlonal circuits
Sequential circuits
1.
2.
3.
4.
5.
Moore model : The output depends only on the present state of the
flip-flops.
Mealy m1Jdel : The output depends on both the present state of the flip-flop(s)
and on the input(s).
4.4.1.1 Moore Model
As mentioned earlier, when the output of the sequential circuit depends only on
the present state of the flip-flop, the sequential circuit is referred to as Moore model.
Let us see one example of Moore model. Fig. 4.20 shows a sequential network which
consists of two JK flip-flops and AND gate. The network has one input X and one
output Y.
Copyrighted material
4. 38
Fundamentals of HDL
QA
JA
Structural Description
Je
CP
KA
Os
QA
Ka
QB
y
In general form the Moore model can be represented with its block schematic as
Inputs
{:
Next
state
decoder
Memory
elements
I
Fig. 4.21 (a) Moore model
Inputs
{:
~
Next
state
decoder
Memory
elements
Output
decoder
(Combinational
circuit)
--. }~i---
Copyrighted material
Fundamentals of HDL
4-39
Structural Description
When the output of the sequential network depends on both the present state of
flip-flop(s) and on the input(s), the sequential circuit is referred to as Mealy model.
Fig. 4.22 shows the sample Mealy model. As shown in the Fig. 4.22, the output of the
circuit is derived from the combination of present state of flip-flops and input(s) of the
circuit.
QA
JA
JB
CP
KA
Os
QA
Ke
Oe
y
Looking at Fig. 4.22, we can easily realise that, changes in the input within the
clock pulses cannot affect the state of the flip-flop. However, they can affect the
output of the circuit. Due to this, if the input variations are not synchronized with the
clock, the derived output will also not be synchronized with the clock and we get
false output (as it is a synchronous sequential network). The false outputs can be
eliminated by allowing input to change only at the active transition of the clock (in
our example HIGH-to-LOW).
In general form the Mealy model can be represented with its block schematic as
shown in Fig. 4.23.
r-Output
decoder
'"'""
Next
state
decoder
Outputs
Memory
elements
r--
Copyrighted material
Fundamentals of HDL
Structural Description
4-40
Moore Model
Mealy Model
a)
b)
c)
generation place.
Output variable : All variables that exit the sequential machine are called
output variables.
For example, in the Mealy model shown in Fig. 4.22, X is an input variable, Y is
an output variable, QA and Q 8 are the state variables and variable XA which excites
flip-flop B is an excitation variable.
4.4.2.1 State and State Variable
We know that state is defined by the output of flip-flops (memory). In the state
machine, state variables and states are related by the expression
y
where
and
In state machines, it is necessary to distinguish state variables before and after the
clock pulse. State variable A can be represented as A before the arrival of a clock and
Copyrighted material
Fundamentals of HDL
4 - 41
Structural Description
as A+ after the arrival of a synchronizing clock pulse. The idea of present state and
next state is illustrated in Fig. 4.24.
Clock
I,.._ \
I
I
I
I
I
I
State ==>k:
\,__--fI
t+1
t- 1
A-
>K
I
I
I
I
I
I
I
I
>K
A+
I
I
I
I
I
I
The status- of all state variables, at some time, t, before the next clock edge,
represents condition called present state.
Next state
The status of all state variables, at some time, t + 1, represents a condition called
next state.
4.4.2.3 State Transition Diagram
State diagram is a
pictorial representation of a
behaviour of a sequential
circuit. Fig. 4.25 shows a
state diagram. The state is
represented by the circle,
and the transition between
sta tes is indicated by
directed lines connecting
the circles. A directed line
connecting a circle with
itself indicates that next
state is same as present
state. The binary number
inside each circle identifies
the state represented by the
Fig. 4.25 State diagram for Mealy circuit
circle. The directed lines
are labelled with two binary numbers separated by a symbol '/'. The input value that
causes the state transition is labelled first and the output value during the present
state is labelled after the symbol '/'.
Copyrighted material
Fundamentals of HDL
4 -42
Structural Description
Next state
Output
x"' 0
X=1
X=O
X=1
AB
AB
AB
c
a
c
In case of Moore circuit the output section has only one column since output does
not depend on input. The Table 4.5 (b) shows the state table for Moore circuit whose
state diagram is shown in Fig. 4.26.
Copyrighted material
Fundamentals of HDL
4-43
Present state
Structural Description
Next state
Output
X=O
x=1
AB
AB
AB
A transition table takes the state table one step further. The state diagram and
state table represent state using symbols or names. Jn the transition table specific state
variable values are assigned to each state. Assignment of values to state variables is
called State assignment. Like state table transition table also represents relationship
between input, output and flip-flop states. The Fig. 4.27 shows the transition table.
Present state
Next state
Output
X=O
X=1
X=O
x= 1
AB
AB
00
10
11
00
1 0
0 1
00
10
Copyrighted material
Fundamentals of HDL
4-44
Structural Description
Example 4 .13 : A sequential circuit has one input and one output. The state
diagram is shown in Fig. 4.28. Design the sequential circuit with a) D flip-flops
b) T flip-flops c) RS flip-flops and d) JK- flip-flops.
1/1
Fig. 4.28
The transition table for the state diagram shown in Fig. 4.28 is as given in
Solution :
Table 4.6.
Present state
Next state
Output
X=O
X =1
X= O
x .. 1
AB
AB
00
10
1 1
00
1 0
01
00
10
Table 4.6
As seen from the transition table there are no equivalent states. Therefore, no
reduction is the state diagram. The transition table shows that circuit goes through
four states, therefore we require 2 flip-flops (number of states = 2"', where m =
number of flip-flops). Since two flip-flops are required first is denoted as A and
second is denoted as B.
As mentioned earlier, for D flip-flops next states are nothing but the new present
states. Thus, we can directly use next states to determine the flip-flop input with the
help of K-map simplification.
Copyrighted material
4 .45
Fundamentals of HDL
Structural Description
For output
00
01
11
1')]
10
l!l
AB
Fig. 4.29
K-map Simplification
DA = A BX + A B X + ABX + A B X
and
D8 = AB X + AB X
Y = ABX + AX
With these flip-flop inpu t functions and circuit output function we can draw the
logic diagram as follows.
i l -- r - ,
ii
>---.
x--....-"'
i i --r--....
B
;c--....-"
QA
A-_,..-,
A
ii
x- -....-"
A--r--,
ii
;c--1...-"'
i l --r--....
B
>--~
;c-....__..,
A-....r--....
ii
x--t...-"
-Os 9
CP
Copyrighted material
Fundamentals of HDL
...
4-46
Structural Description
Y : ou t std_logic);
end s _circuit;
architecture circuit_D of s _circuit Is
component and2
port ( 11, 12: in std_logic;
01 : out std_logic);
end component;
component and3
port ( 11, 12, !3 : in std_logic;
01 : out std_logic);
end compone nt ;
component or2
p ort ( 11, 12 : in std_ logic;
0 1 : out std_logic);
end component;
component or4
port ( 11, 12, 13, 14 : in std_logic:
01 : out std_logic);
end component ;
component inv
port ( 11 : in std_logic;
01 : out std_logic);
e nd component;
component D_FF
p ort ( 11, 12 : in std_logic;
0 1, 02 : buffer std_logic);
e n d component;
for all : and2 use entity work.two_input (and2_4);
for all : and3 use entity work.three_input (and2_4);
Copyrighted material
Fundamentals of HDL
4-47
Structural Description
II>-
Copyrighted material
4 -48
Fundamentals of HDL
Structural Description
Using the excitation table for JK flip-flop shown in Table 4.7 we can determine the
excitation table for the given circuit as shown in Table 4.8.
Qn
Qn + 1
x
x
Input
Flip-flop Inputs
Next state
Output
JA
KA
Jo
Ka
x
x
0
0
x
x
x
x
x
x
'l
x
x
x
x
x
x
x
x
Table 4.8
The first row of circuit excitation table shows that there is no change in the state
for both flip-flops. The transition from 0 ~ 0 for JK filp-flop requires inputs J and K
to be 0 and X, respectively. Similarly, we can determine inputs for each flip-flop for
each row in the table by referring present statt:, next state and excitation table. Let us
use K-map simplification to determine the flip-flop input functions and circuit output
functions.
Copyrighted material
4 - 49
Fundamentals of HDL
00
00
01
01
11
11 !~
1.
10
(b) For KA
(c) For J 8
(d) For Ke
0
0
Fig. 4.31
J.. = BX+ BX
KA = BX+
fo
KB
BX
AX
A+X
- --
Output (Y)
Fig. 4.32 Logic diagram of given sequential cir cuit using J K flip-flop
....
Listing 4.23 : HDL description for given sequential circuit using - VHDL and Verilog.
Copyrighted material
4. 50
Fundamentals of HDL
Structural Description
Y : out std_logic);
end s _circuit;
architecture circuit JK of s - circuit is
component and2
port ( I1, 12 : in std_ logic;
01 : out std_logic);
end component;
component and3
port ( 11, 12, 13 : in std_logic;
01 : out std_logic);
end component;
component or2
port ( 11, 12 : In std_logic;
01 : out std_logic);
end component;
component inv
port ( 11 : In std_logic;
01 : out std_logic);
end component;
component JK_FF
port ( 11, 12, 13 : in std_logic;
01, 02 : buffer std_logic);
end component;
for al!: and2 use entity work.two_input (and2_4);
for all : and3 use entity work.three_input (and2_4);
for all : inv use entity work.one input (inv 4);
'
for all: or2 use entity'work.two_input (or2_4);
: and2
: and2
: and2
: and2
port map
port map
port map
port map
Copyrighted material
Fundamentals of HDL
Structural Description
4 - 51
Fig. 4.33 (a) shows 3-bit synchronous binary counter and its timing diagram. The
state sequence for this counter is shown in Table 4.9.
HIGH
JO
-c I>
KO
01
J1
.--c >
K1
01
i..r>-
J2
K2
02
.....
CP
Copyrighted material
Fundamentals of HDL
4 -52
Structural Description
CP
QO
01 - - - - - '
Fig. 4.33 (b) Timing diagram for 3-bit synchronous binary counter
Looking at Fig. 4.33 (b), we can see that QO changes on each clock .pulse as we
progress from its original state to its final state and then back to its original state. To
produce this operation, flip-flop 0 is held in the toggle mode by connecting J and K
inputs to HIGH. Now let us see what flip-flop 1 does. Flip-flop 1 toggles, when QO is
1. When QO is a 0, flip-flop 1 is in the no-change mode and remains in its present
state. Looking at the Table 4.9 we can notice that flip-flop 2 has to change its state
only when Q l and QO both are at logic 1. This condition is detected by AND gate
and applied to the J and K inputs of flip-flop 2. Whenever both QO and QI are HIGH,
the outpu.t of the AND gate makes the J and K inputs of flip-flop 2 HIGH, and
flip-flop 2 toggles on the following clock pulse. At all other times, the J and K inputs
of flip-flop 2 are held LOW by the AND gate output, and flip-flop does not change
state.
....
entity counter is
port ( CP : in std_logic;
Copyrighted material
Fundamentals of HDL
4. 53
Structural Description
01 : out std_logic);
end component ;
compon ent JK_FF
port ( 11, 12, 13 : in std_logic;
signal J2 std_logic;
begin
\
Fundamentals of HDL
4-54
Structural Description
When generate statement is used, it is not necessary to write out all of the component
instantiations individually. In VHDL, the syntax of a simple iterative generate loop is
given below.
The identifier is a variable with type compatible with the range. This identifier
may be used within the concurrent statement given within a FOR loop. The
concurrent statement is executed for each possible value of the identifier within the
range. For example, consider a circuit consisting of 8 AND gates. A generate statement
can be used to create repetitive (8) structures of AND gate as shown below.
library ieee;
use ieee.std_logic_ 1164.all;
entity and8 is
port (A, B : in std_!ogic_vector (1 to 8);
0: out std_logic_vector (1 to 8));
end and8;
architecture and8_arch of and8 is
component and
port ( X, Y: in std_logic;
Z : out std_logic);
end c omponent;
begin
G1 : for c in 1 to 8 generate
end generate ;
end and8_arch;
We declare the parameters (For example : Bus width) as constants within a VHDL
program. The value of a constant must be known when a VHDL program is compiled.
But in many applications it is useful to design and ~ompile a VHDL program without
Copynqhted material
Fundamentals of HDL
4- 55
Structural Description
specifying the values of some parameters. VHDL provides this facility with generic
statement and Verilog provides this facility with parameter statement.
Generic and Parameter Declaration
The constants whose values are not specified within a VHDL program are called
generic constants. These are defined in an entity declaration with a generic declaration
before the port declaration. The syntax of generic declaration is given below.
entity entity_ name is
generic ( constant_names
: constant_type;
constant name
: constant_type;
constant name
: constant type);
port
signal_name
: mod e signal_type;
signal_names
signal_names
: mode signal_type);
end entity_name;
For example, consider an arbitrary_width bus inverter. The bus_width for this bus
inverter is user_specifiable. The VHDL program for this bus inverter is given below.
library ieee;
use leee.std_logic_1164.all;
entity businv is
generic (width: integer: = 8);
port (
end businv;
architecture businv arch of busin v Is
component inv port (
I: In std_logic)
0 : out std_logic);
end component;
begin
gl:
u1:
end businv_arch;
Multiple (in our example, 8) copies of this inverter can be instantiated in the
program by taking different user-specified widths.
Copyrighted material
Fundamentals of HDL
4- 56
Structural Description
end
endgenerate
library ieee;
use leee.std_logic_1164.all;
entity comp_gen is
generic (N : integer: = 3);
port (A, B: in std_Jogic_vector (N downto 0);
AgtB, AltB. AeqB: buffer std_logic);
end comp_gen;
architecture compare of comp_gen is
component full_adder
port (11, 12, 13 : in std_logic; 01, 02 : out std_logic);
end component;
com pone nt inv
port (11 : in std_logic; 01 : out std_logic);
end component;
component nor2
port (11, 12 : in std_logic; 01 : out std_Jogic);
Copyrighted material.
Fundamentals of HDL
4. 57
Structural Description
end component;
component and2
port (11, 12: in std_logic; 01 : out std_logic);
end component;
signal Sum, Bbar: std_logic_vector (N downto 0);
signal C, eq: std_logic_vector (N
+ 1downto0);
= 3;
input (N:OJ A, B;
output AgtB, AltB, AeqB;
wire (N:O( Sum, Bbar;
wire (N+ l : 0( C, eq;
assign C(OI
assign eq(OI
= l'bO;
= l 'b l;
generate
genvar i;
for (i = O; i <
= N; i = i +
1)
begin : u
Copyrighted material
4 . 58
Fundamentals of HDL
Structural Description
The Fig. 4.5 shows the 4-bit asynchronous down counter using JK flip-flops. Here,
the clock signal is connected to the clock input of only first flip-flop. This connection
is same as asynchronous/ripple up counter. However, the clock input of the
remaining flip-flop is triggered by the Q output of the previous stage.
00
01
02
03
QN
IJI.
Listing 4.26 : HDL description of an N-bit asynchronous down counter using generate
statement.
uae ieee.std_logic_1164.all;
entity asyn_ctr is
g eneric (N : integer: = 4);
-- This is a 4-bit counter.
port ( CP : in std_logic;
Q, Obar : buffer std_logic_vector (N-1 downto 0));
end asyn_ctr;
archi tecture asyn_ctr_gen of asyn_ctr is
Copyrighted material
Fundamentals of HDL
4 -59
Structural Description
component JK_FF is
port( 11, 12, 13 : in std_logic;
01, 02 : buffer std_logic):
end component ;
for all : JK_FF use entity work.JKFF' (F'F);
signals : std_logic_vector (N downto 0);
begin
= 4;
input CP;
output [N-1:0[ 0, Obar;
wire [N:O) s;
memory cell can be expanded to N-bit using the generate statement. This is illustrated
in listing 4.27.
Copyrighted material
4. 60
Fundamentals of HDL
..,_
Structural Description
end word_gen;
Verilog N-Bit Memory Word Using Generate
module memory_word {D_in. sel, R_W, D_out);
parameter N = B;
input (N:O) D_in;
input sel, R_W;
output [N:O) D_out;
$1
generate
genvar i;
for (i = 0; i < = N; i
begin: u
= i + 1)
Copyrighted material
Fundamentals of HDL
Structural Description
4 - 61
Listing 4.28 : HDL description of N-bit register using - VHDL and Verilog.
-- 8-b it register
end Regis;
architecture register_nBit of Reg is is
component D_FF is
port( 11, 12 : in std_ logic;
01, 02 : buffer std_logic):
end component ;
begin
build: for i in 0 to N- 1 generate
for all : D_FF use entity work.OFF (FF );
begin
d : D_FF port map(D(i),CP , Q(i), Qbar(i));
end g enerate b uild;
end register_nBit ;
Copyrighted material
Fundamentals of HDL
4 - 62
Structural Description
The binary information (data) in a register can be moved from stage to stage
within the register or into or out of the register upon application of clock pulses. This
type of bit movement or shifting is essential for certain arithmetic and logic operations
used in microprocessors. This gives rise to a group of registers called 'shift registers'.
They are very important in applications involving the storage and transfer of data in a
digital system.
The Fig. 4.36 shows the N-bit left shift register. Here, the data is shifted left by
one bit on receiving every clock pulse. Din is a serial input signal and Dout is a data
output signal.
Din
'--~~~~~-+~~~~~~+-~~~~~-<-~cP
-- 8-bit regist er
Copyrighted material
Fundamentals of HDL
4. 63
Structural Description
end component ;
begin
build: for i in 0 to N-1 generate
for all : D_FF use entity work.OFF (FF);
signal D : std_logic_vector (N downto O);
begin
D < = (Q & Din);
d: D_FF port map(D(i), CP , Q(i), Obar(i));
end generate build;
Dout < = D(N);
end register_nBit;
= {Q, Din};
generate
genvar i;
for (i = O; i < N; i = i + 1)
begin : u
D_FF FF (D(i]. CP, Q(i], Obar(i]);
end
endgenerate
assign Dout = D(N];
endmodule
Copyrighted material
Fundamentals of HDL
4- 64
Structural Description
Review Questions
1. List the lriglrliglrts of stmcl11ral dt'Scription.
2. Explain tire organization of tire structural description witlr tire help of exarrrple.
3. Lists tile built-in gates supported by Verilog.
4. Wlmt is binding ?
5. Explain the bi11di11g betwee11 e11tity a11d architecture in VHDL.
6. Explain tire binding betwce11 entity a11d co111po11e11t in VHDL.
7. Explain tire binding between a libran; and 111od11le in VHDL.
JO. Write a structural descri11tio11 of 3 : 8 decoder witlr actit1e lrigh enable input.
11. Write a structural description of T flip-fl.op.
12. Design a sequential circuit of three-bit et1e11 counter and write a str11ct11ral descriptio11 for it.
13. Write a structural descriptio11 for a 4-bit synclrrono11s binary co1111ter.
14. Write a str11ct11ral description for right shift register.
ODO
Copyrighted material