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Encounter Workshop 3
What you will learn - Flip Chip Planning
Importing a design
Arranging the IO drivers
Designing bump pins
Customizing the bumps
Assigning IO drivers to bumps
Assigning power and ground to bumps
Routing IO driver pins to bump pins
Designing power and ground rings and stripes
Routing power and ground to bump pins
Routing power and ground to instance power pins
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1.
DTMF_INST/clk
DTMF_INST/spi_clk
scan_clk
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Imported,
Floorplanned
NanoPlaced
Scan chain optimized
Trial routed
Wire parasitic extracted
Setup timing analyzed
Timing optimized for setup timing
Clock tree synthesized
Hold time analyzed
Timing optimized for close timing
NanoRoute routed
Signal integrity analyzed
Fix violating noisy nets
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2.
Note: The following setting up instruction is the same for both Workshops 1 and 2. If
you have already run either Workshop, you can skip to section 3. Starting an Encounter
Session.
The following is the instruction to setup and use the Encounter design tool. You need to
find the installed Encounter directory to get access to the both the Encounter software and
the DTMF design. The design is located in the <install_dir>/share/fe/gift/tutorials/dtmf
directory.
Checklist a. Locate the Encounter install directory.
b. Create a work directory to run the DTMF design.
c. Login to the Cadence Learning Management System at:
http://learning.cadence.com
Setting the Encounter environment In an UNIX window (shell tool, xterm, or etc.), you must set a path to the installation
directory and set an environment variable for the cdslmd license:
set path=(<install_dir>/tools/bin $path)
setenv LM_LICENSE_FILE
\
<install_dir>/share/license/<cdslmd_lic>
which encounter (to see if the path is set properly?)
Note that this UNIX window becomes the Encounter Console where Encounter
commands are entered and Encounter messages are outputted.
Setting up your work directory for the workshop
This requires three steps.
1) Copying the DTMF design data
Copy all the contents (files and directories) from the ~share/fe/gift/tutorial/ directory to
your work directory. Use the UNIX commands:
mkdir <work_directory_name>
cd <work_directory_name>
cp r <install_dir>/share/fe/gift/tutorials/* .
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3.
Make sure you are in the dtmf/work_fe work directory and type:
encounter
Now the Encounter Main Window displays.
Toolbar
Widgets
Menus
Color
Preference
form
Select bar
Design
Views
Tool
Widgets
Selectability
toggles
Visibility
toggles
Color
options
Displays name of
selected or queried
object
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Auto Query of
object when
enabled ON
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Coordinates of
cursor location
Action
Bind Key
Fit Display
Group
Ungroup
Ruler
Ruler
Attribute
View DB
Redo
Undo
Zoom-in
Zoom-out
Pans
Align
Description
Opens the Binding Key form.
Zooms the display to fit the core area.
Moves up the hierarchy on the highlighted instance.
Moves down the hierarchy on the highlighted Hinstance.
Create a ruler.
Removes last ruler displayed.
Opens the object attribute editor form on selected object.
View the attributes of highlighted object.
Returns the design to state to last Undo command.
Returns the design to state to previous command.
Zooms in the display, 2x.
Zooms out the display, 2x.
Pans the display in direction of arrow.
Opens the Align Instance/Module form to align horizontally
Deselects
Redraws
Deletes
Selects
Focus
Action
Focus
Focus
Description
Changes the focus of stacked objects.
Changes the focus of previous stacked object.
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Populates
Populates the Edit Route form with the net name and more
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Action
Ends
Deletes
Moves
Description
Ends the drawing mode for creating special route.
Removes last point/segment.
Moves the current segment in direction of arrow.
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domain
eco
filler
fix
floorplan
footprint
group
hier
import
load
noise
partition
place
preference
power
restore
route
save
scan
sdf
select
snap
timing
verify
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4.
Importing the design - The Design Import form is used to load the Verilog netlist,
physical libraries, process technology libraries, timing libraries, and timing constraints.
Other important items are also loaded during design import and they are contained in the
2 tabs of the Design Import form. Open the Design Import form and make the following
entries.
Form Design -> Import Design
Load The configurations file dtmfLef.flipchip.conf and examine the entries in the
Design Import form.
Click the OK button when ready to import.
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5.
Loading the floorplan The blocks are preplaced and this is done by loading a floorplan
file. You can design your own floorplan but keep in mind that no bumps will be allowed
on top of the PLLCLK_INST block.
Form Design -> Load -> Floorplan
Load The floorplan file dtmf_flipchip.blocks.fp
Click the Open button when ready.
Now the blocks are preplaced as in Figure 1.
Figure 1 Floorplan View with Blocks Preplaced
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Creating bumps for the design The bump array of 10-by-10 needs to be placed in a
square pattern across the die. Open the Create Bump Array form and make the following
entries.
Form Floorplan -> Flip Chip -> Create Bump Array
In the Bump Matrix section, leave the defaults since a full matrix is required.
In the Create in Area section, leave the default values.
In the Bump Spacing section,
Change the Bump Pitch, Horizontal: 100
Change the Vertical: 100.
In the Edge Spacing section,
Change the DX: 80
Change the DY: 70
Click the OK button when ready.
Now, your created bumps should be similar to Figure 2. If your bump matrix pattern is
not what you want, use the Floorplan -> Clear Floorplan -> Specified Objects -> Bump
Pins and click OK button to remove the bump pins, and try again to create the bumps.
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6.
Since bumps are not allowed on top of the PLLCLK_INST block, the 9 bumps that are
inside the block boundary must be removed. Open the Clear Floorplan form and make
the following entries.
Form Floorplan -> Edit Floorplan -> Clear Floorplan
Select Selected
Select the 9 bumps on top of the PLLCLK_INST block by holding down the Shiftkey while selecting (LMB).
After removing the 9 bumps, the floorplan looks like Figure 3.
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The assumption is that we are in the early development stage and we can freely assign the
signal bump locations.
Assigning signals to bump pins This is done with the Assign Signals form. Make the
following entries.
Form Floorplan -> Flip Chip -> Assign Signals
In the Assign to Tiles/Bumps section,
Select Closest
Click the Assign button when ready.
The bumps with signal assignments are now blue in color. To inspect the relative
closeness of the bumps to each IO driver, use the menu item, Floorplan -> Flip Chip ->
Display Options -> Signals. This will display the signal names on each bump (zoomedin).
Viewing IO signal names and assigned bumps information
1) Use the menu items in Floorplan -> Flip Chip -> Display Options. The
displays are Number, Signals, Terminals, or Bump Names.
2) Use the Floorplan -> Flip Chip -> Assign Signals form to view or make
assignments. First select an IO Signal name in the form, and then observe the
Physical view. The IO driver and bump pair are highlighted in green color.
The form is used to assign a signal to a bump or to unassign a signal to a
bump.
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Assigning power to bump pins The bumps that are to be assigned to power are shown
in Figure 4, and the VDD bumps to be assigned are highlighted with white color outline.
Open the Assign Power/Ground Bumps form and make the following entries.
Form Floorplan -> Flip Chip -> Assign Power/Ground
Select the 17 bumps highlighted in Figure 4 using the Shift-key + (LMB).
In the Bumps/Tiles section,
Select Selected Bumps.
In the Power/Ground section,
Select Power.
Click the Set button when ready
Now the VDD bumps are red in color.
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Assigning ground to bump pins The bumps that are to be assigned to ground are the
remaining unassigned bumps. Open the Assign Power/Ground Bumps form and make
the following entries.
Form Floorplan -> Flip Chip -> Assign Power/Ground Bumps
In the Bumps/Tiles section,
Select Floating Bumps.
In the Power/Ground section,
Select Ground.
Click the Set button when ready
The VSS bumps are orange-yellow in color. Now, all the bump pins are assigned.
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The connections need to be routed between the assigned IO driver pin and the bump pin.
This is done with the flip chip router and layers Metal 7 and 8 (RDL layers) are used.
First, the refclk signal is routed with shields and the shields are tied to VDD. Open
the Route Flip Chip Signal form and make the following entries.
Form Route -> Flip Chip -> Signal
In the Basic page and in the Net(s) section,
Select Named: refclk.
In the Layer Range Control section,
Change Bottom Layer M7
Under Jog control,
Select Prefer different layer jog
Now,
Select and Enter Route width: 1.5
Select Delete existing routes (this selection is done for later use).
Use the remaining defaults.
Click the Advanced tab to open the page.
In the Shield Routing section,
Select Net: Tie high
Select and Enter Width 0.44
Click the Apply button when ready (keep this form displayed).
Zoom in to view the shielded clock net between the IO driver and bump. The net is on
the left side of the chip.
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Second, the reset and pllrst signals are routed with splitting their routes. Again, the
flip chip router is used.
Form Route -> Flip Chip -> Signal
From the previous entries, make the following changes.
Click the Basic tab and in the Net(s) section,
Change Named: reset pllrst.
In the Layer Range Control section, make sure this is still selected,
Change Bottom Layer M7
Under Jog control, make sure this is still selected,
Select Prefer different layer jog
Now, make sure of the selection and entry,
Select and Enter Route width: 1.5 and
Use the remaining defaults.
Click the Advanced tab to open the page.
In the Shield Routing section,
Deselect Net:
Deselect Width
In the Splitting section,
Select and Enter Width limit: 0.5
Select and Enter Gap between split segments: 0.46
Select Splitting style: River
Click the Apply button when ready.
Zoom in to view the split nets between the IO drivers and bumps.
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Third, the vcom and vcop signals are routed with differential (balancing).
Form Route -> Flip Chip -> Signal
From the previous entries, make only these changes.
Click the Basic tab and in the Net(s) section,
Change Named: vcom vcop
Click the Advanced tab to open the page.
In the Differential Routing section,
Enter Differential routing tolerance (L/W unit): 2
Enter Balanced pair threshold (%): 20
Select Differential routing for selected nets
Select L/W matching
In the Segment Splitting section,
Deselect Width limit: 0.5
Deselect Gap between split segments: 0.46
Click the Apply button when ready.
Zoom in to view the two nets between the IO drivers and bumps located at the left side of
the chip.
Rerouting flip chip signal information If you want to retry routing a previous
routed signal, this can be in two ways. 1) Select/highlight any segment of the net
and in the Nets section of the Route Flip Chip Signal form, make sure to select the
Selected option, and then make sure the Delete existing route is selected (at
the bottom of the form). Rerunning the flip chip router will reroute this net.
2) Enter the net name(s) in the Named text entry box, and then make sure the
Delete existing route is selected (at the bottom of the form) before running flip
chip router as you did in this exercise.
3) Shield routing does not get automatically deleted. Use the Floorplan -> Clear
Floorplan form to delete the power/ground special route before rerouting the
signals.
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Forth, the remaining IO signals are routed to bumps with the default setting in the flip
chip router form. Make the following entries.
Form Route -> Flip Chip -> Signal
Click the Defaults button at the bottom of the form.
In the Layer Range Control section, make sure this are still selected,
Change Bottom Layer M7
Click the OK button when ready.
Now only the remaining unrouted IO signals are routed to their bumps.
9
Before designing any power and ground rings or stripes, we must assign the global nets of
power and ground for the entire design, and this is done with the Global Net Connections
form. From the netlist, the power pins, tie high pins, and tie low pins need to be
connected to power and ground nets. Also, from the LEF file, the vdd! and gnd! ring pins
need to be connected to power and ground nets. There are 6 sets of entries required and
they are shown in the table below.
Form Floorplan -> Connect Global Nets
For Set 1:
Enter Set 1 from table (follow Figure 5).
Click Add to List button.
Continue for Sets 2 through 6 and when done, the completed form looks like Figure 6.
Click the Apply button when all 6 sets appear in the Connection List.
Entry
Pins
Instance Basename
Tie High
Tie Low
Apply All
To Global Net
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Set 1
VDD
*
n/s
n/s
Selected
VDD
Set 2
vdd!
*
n/s
n/s
Selected
VDD
Set 3
VSS
*
n/s
n/s
Selected
VSS
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Set 4
gnd!
*
n/s
n/s
Selected
VSS
Set 5
n/s
*
n/s
Selected
Selected
VSS
Set 6
n/s
*
Selected
n/s
Selected
VDD
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After applying the 6 sets, click the Check button. There should be no warning messages.
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10
Now with the power and ground nets assigned, power planning can be done. In this
design, power and ground rings are added around the core area and around one of the
blocks. Power and ground stripes are also added to the top level design. The Synthesize
Power Plan form is used and this form contains design and block/IP templates which are
used to customize the power rings and stripes. See the Figure 14 which helps identifies
the templates. There are 6 major steps in the following instruction set.
Figure 14 The Synthesize Power Plan form
Note these buttons:
New template form
Opens an existing template form
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The 1st major step is to assign power rings to the pllclk block. Make the following
entries:
Form Power -> Power Planning -> Synthesize Power Plan
Enter Total Average Power (mW): 6.0
Select Use template to create power plan
Select IP
Click New template icon (blank sheet icon) and this opens the Edit Power Plan
Template form.
In the Edit Power Plan Template form,
Click the IP Block tab.
Select pllclk in the IP Block List
In the Block Ring tab,
Select Require Block Ring
Deselect Allow sharing with others
Select Offset and enter 1.0.
In the Layer section,
Select M6/M5 and enter 8.0 for Bit width.
No power stripes are required for the pllclk block and the Stripe tab is skipped
Click the Set button and this both bolds pllclk and changes the color blue in the IP Block
List.
Click the Save As button and this opens the Specify Template Name form.
In the Specify Template Name form,
Enter the Template Name: block. This is the power planning template for the block and
will be used later.
Click the OK button to save pllclk block template work.
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The 2nd major step is to assign power rings and stripes to the entire design. Note that the
Synthesize Power Plan form redisplays after you clicked OK in the last step. Keep this
form displaying since it is used several more times. Make the following entries
In the Synthesize Power Plan form, make the selection changes:
Select Design and
Click New template icon (blank sheet icon) and this opens the Edit Power Plan
Template form.
Select Ring and
Select M6/M5.
Select Stripe and
Select M6.
Note the Illustration window that displays the ring and stripes for the entire design.
Enter Region Name: chip
Enter IP Library Template: block (use the down-arrow stepper).
Click the Add/Modify button to set the ring and stripe specifications.
Click the Save As button and this opens the Specify Template Name form.
In the Specify Template Name form,
Enter Template Name: chip.
Note that this is the power planning template for the entire design including the block.
Click the OK button to save design template work.
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The 3rd major step is to assign power planning options for the rings and stripes. Leave the
Synthesize Power Plan form displaying since it will be used once more. Make the
following entries.
Form Power -> Power Planning -> Edit Power Planning Option
Click Object: Stripe button.
Select Stripe Breaking in the Options window and note the illustration on the
right side of the form.
Underneath the illustration,
Select Omit stripes inside block rings and
Click the Add/Modify button located above the illustration.
Enter Power Planning Option Set breaking and
Click the Save button.
Click the Close button to close this form.
The 4th major step is to assign rings and stripes options to the chip template, and the
Synthesize Power Plan form is used. Make the following entries:
In the Synthesize Power Plan form (which should be displaying), make sure the template
selection are still Design and the template name is chip.
Click Open template icon (sheet with text icon) and this opens the Edit Power Plan
Template form.
Enter Power Planning Option Set: breaking (use the down-arrow stepper) and
Click the Add/Modify button.
Click the Save button to save the final setting for the power planning template. Note that
you can overwrite the chip template file since the content is being modified.
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The 5th step is to assign the width and space parameters to the ring and stripes for the top
level in the Specify Template Parameter form. Make the following entries:
In the Synthesize Power Plan form (which should be displaying), make sure the template
selection are still Design and the template name is chip.
Click Specify Template Parameter icon (text icon on the far right) and this opens the
Specify Template Parameter form.
Note the left side of the form in the Design section which displays the DTMF power and
ground design according to the preceding template work. By selecting/highlighting
DTMF_CHIP: chip, this allows you to assign the parameters to the rings and stripes. By
selecting DTMF_CHIP/PLLCLK_INST: pllclk, this allows you to view the parameters
assigned by the block template. Make sure that DTMF_CHIP: chip is selected before
making the following entries:
In the Ring section, leave the options deselected and make the following changes:
For Metal6-Metal5,
Change Width to 8.0, Spacing to 1.0, and Offset from center to 9.0
In the Stripe section, leave the Wire Group deselected since only a single set/group of
power stripes is required and make the following changes:
For Metal6,
Change Width to 8.0, Spacing to 1.0, Offset from auto to 100
Select Pitch and
Change Count/Pitch to 100.
In Configure Template section, make sure 6.0 mW is entered for the Total Power.
Click the OK button when ready.
The 6th and final step is generating the rings and stripes for the entire design after entering
our specification into the power plan templates. This is done in the Synthesize Power
Plan form. Make the following entries:
In the Synthesize Power Plan form (which should be displaying), make sure the template,
Total Average Power entry is 6 mW, selection are still Design, the template name is
chip.
Click the Apply or the OK button.
Now you should see to power and ground rings and stripes created for the design. See
Figure 6. You can ignore the Invalid EM message since no EM limits were entered.
Zoom in on a VDD or VSS bump to view the vias generated.
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11
The power connections need to be made to the VDD and VSS bumps and this is done in
the Route Flip Chip Power form. Make the following entries.
Form Route -> Flip Chip -> Power
Use the Basic page defaults and
Select and Enter Route width: 8.0
Click the OK button when ready.
Now, all the power bumps are connected to VDD and VSS stripes.
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12
To route the remaining power and ground structure, SRoute is used. SRoute routes to the
block pins, pad pins, pad rings, standard cell pins, and unconnected stripes. For our
exercise, we will be routing block pins, pad pins, and standard cell pins. Make the
following entries.
Form Route -> Special Route
In the Basic page, make the changes in the Route section to:
Deselect Pad rings.
In the Layer Change Control section,
Change Top layer: M6
Bottom layer: M1
Use the remaining defaults in the Basic page.
Click the Advanced tab and then click Extension control from the list. Make 2 selection
changes as follows:
In the Primary Connection for: and under Standard Cell Pins and stripe section, change
selection to:
Select None
In the Secondary Connection/Stripe (Standard Cell Pins Only) (if the primary connection
fails) section, change selection to:
Select Last cell in the row
Click OK when ready.
Now the power and ground rings around the core area are connected to the power and
ground pads, block pins are connected, power rings are all connected, and standard cell
follow pins are connected.
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Verifying connectivity and geometry After designing the power and ground for the
design, the connections and geometries can be verified (DRC). These 2 tools are in the
Verify menu. To verify the power and ground connectivity, make the following entries.
Form Verify -> Verify Connectivity
Change selection to:
Select Special only
Deselect Antenna checking.
Use the remaining defaults.
Click OK when ready.
There are violations markers because of antenna warnings and these warning can be
ignored since these are power and ground.
Identifying violation marker information There are 2 ways to identify
violation markers: 1) Click the Q button at the bottom in the Encounter window
which enables auto query of objects. Moving the cursor exactly on top of a
violation marker displays the violation type in the bottom selected object text box.
You may have to zoom-in very closely to have the violation type displayed. 2)
Open the Verify -> Violation Browser to display the violations.
The violation markers are cleared using Verify -> Clear Violation menu item.
To verify the geometries, use the Verify Geometry form and make the following entries.
Form Verify -> Verify Geometry
Use the defaults in the form which does not check for antenna geometries.
Click OK when ready.
Clear the DRC markers if any.
Now you are ready to proceed to do placement work as learned in Workshop 1.
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