Lic Manual

Linear and Digital Integrated Circuits Lab
EE6311 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY L T P C

0032
OBJECTIVES:
Working Practice in simulators / CAD Tools / Experiment test bench to learn design,
testing and characterizing of circuit behaviour with digital and analog ICs.
LIST OF EXPERIMENTS:
1. Implementation of Boolean Functions, Adder/ Subtractor circuits.
2. Code converters: Excess-3 to BCD and Binary to Gray code converter and vice-versa
3. Parity generator and parity checking
4. Encoders and Decoders
5. Counters: Design and implementation of 4-bit modulo counters as synchronous and
Asynchronous types using FF ICs and specific counter IC.
6. Shift Registers: Design and implementation of 4-bit shift registers in SISO, SIPO,
PISO,
PIPO modes using suitable ICs.
7. Study of multiplexer and demultiplexer
8 Timer IC application: Study of NE/SE 555 timer in Astable, Monostable operation.
9. Application of Op-Amp: inverting and non-inverting amplifier, Adder, comparator,
Integrator and Differentiator.
10. Study of VCO and PLL ICs:
i. Voltage to frequency characteristics of NE/ SE 566 IC.
ii. Frequency multiplication using NE/SE 565 PLL IC.
TOTAL : 45 PERIODS
Department of Electrical and Electronics Engg
Exp. No:
Date
:
STUDY OF BASIC DIGITAL ICs
AIM:
To test of ICs by using verification of truth table of basic ICs.
COMPONENTS REQUIRED:
S.NO
COMPONENT NAME
RANGE
1.
Digital trainer kit
2.
IC7408, IC7432, IC7486,
IC7404, IC7400, IC7402.
3.
Breadboard
4.
Connecting wires
QUANTITY
1
Each 1
1
THEORY:
1. AND gate (IC 7408)
The operation of AND gate is such that the output is HIGH only when all of the inputs
are HIGH. When any of the inputs are LOW, the output is LOW. The basic purpose of
AND gate is to determine whether certain conditions are simultaneously true.
AND function, Z=A.B
2. OR gate (IC 7432)
The operation of OR gate is such that the output is HIGH when any of the inputs are
HIGH. When all of the inputs are LOW, the output is LOW. The basic purpose of OR
gate is to determine whether one or more input bit(s) are HIGH.
OR function, Z=A+B
3. NOT gate (IC 7404)
The inverter (Not gate) performs a basic logic function called inversion or
complementation. The purpose of the inverter is to change one logic level to opposite
level. In terms of bits, it changes a 1 to 0 and vice-versa.
NOT function, Z=A' or Z=A
4. NAND gate (IC 7400)
The term NAND is a contraction of NOT-AND and implies an AND function with a
complemented (inverted) output. The logical operation of the NAND gate is such that, a
LOW output occurs when all inputs are HIGH. When any of the inputs are LOW, the
output will be HIGH.
NAND function, Z=A.B
AND gate (IC 7408)

Symbol
Truth Table
A
B
Input
A
B
0
0
0
1
1
0
1
1
Z
IC7400
PinDiagram
Output
Z=A.B
0
0
0
1
14
13
I
C
7
4
0
8
3
4
5
6
12
11
10
9
NAND gate (IC 7400)

Symbol
A
B
Truth Table
Z
IC7400
Input
A
B
0
0
0
1
1
0
1
1
Pin Diagram
Output
Z=A.B
1
1
1
0
1
2
I
C
7
4
0
0
3
4
5
6
7
NOR gate (IC 7402)

Symbol
Truth Table
Input
A
0
0
1
1
Output
B
0
1
0
1
Z=A+B
1
0
0
0
3
A
B
5
6
7
1
2
1
1
1
0
Pin Diagram
8
1
4
1
3
1
IC7402
2
3
4
1
4
1
3
I
C
7
4
0
2
1
2
1
1
1
9
8
Ex-OR gate (IC 7486)

Symbol
Truth Table
Pin Diagram
Input
A
B
Output
Z=A B
0
0
1
1
0
1
1
0
0
1
0
1
A
B
IC7486I
C7
4
8
6
3
4
5
6
7
Truth Table
A
B
Z
IC7432
Input
A
B
0
0
0
1
1
0
1
1
12
111
0
9
8
OR gate (IC 7432)

Symbol
14
13
Pin Diagram
Output
Z=A+B
0
1
1
1
1
2
3
4
5
14
13
I
C7
4
3
2
12
11
10
9
6
7
NOT gate (IC 7404)

Symbol
Truth Table
Z
IC7404
Input
A
0
1
Output
Z=A'
1
0
Pin Diagram
1
2
3
4
5
6
7
14
I
C
7
4
0
4
13
12
11
10
9
8
Note: For all the above ICs

Pin No: 7 is connected to GND and Pin No:14 is connected to Vcc of +5volts
5. NOR gate (IC 7402)
The term NOR is a contraction of NOT-OR and implies an OR function with a
complemented (inverted) output. The logical operation of the NOR gate is such that, a
LOW output occurs when any of its inputs are HIGH. When all of the inputs are LOW,
the output will be HIGH.
NOR function, Z=A+B
The NAND and NOR gates are popular logic functions because they are universal
functions/gates: that is, they can be used to construct an AND gate, an OR gate, an
inverter or any combination of these.
6. Ex-OR gate (IC 7486)
The operation of Ex-OR gate is such that the output is HIGH when one of the input is
HIGH. When all of the inputs are LOW (or) HIGH, the output is LOW.
Ex-OR function, Z=A B +A B or Z= Z=A B
BASIC FLIP-FLOPS
Sequential Circuits
The present output depends upon the present input and previous output. The sequential
circuits are formed from combinational circuit by adding a memory element.
Flip Flops
A Flip Flop is also called as 1 bit memory cell (or) Bitable Multivibrator.
Flip flop is a sequential circuit which can maintain a binary state indefinitely until the
power is delivered to the circuit and the input signal changes its states.
Inputs
Flip
Flop
Normal Output (Q)

Complemented
Output (Q')
Characteristics of Flip Flop

1. A Flip Flop has two outputs (Q and Q')
2. The contents will be erased when the power is cut-off.
3. The two stable states are:

When Q=1; Q'=0- SET state
When Q=0; Q'=1- RESET state
RS Flip Flop
Characteristic/Truth Table
R
Q
7408
R
0
0
1
1
7402
CP
Q'
S
0
1
0
1
Q(t+1)
Q(t)
1
0
*
* - indeterminate state
D Flip Flop
D
Q
7408
Q(t)
0
0
1
1
7402
Q'
D
0
1
0
1
Q(t+1)
0
1
0
1
JK Flip Flop
K
Q
7411
CP
7402
J
J
0
0
1
1
Q'
K
0
1
0
1
Q(t+1)
Q(t)
1
0
Q(t)
The four kinds of Flip Flops are:

1. RS Flip Flop
2. D Flip Flop
3. JK Flip Flop
4. T Flip Flop
1. RS Flip Flop
1. A clocked RS Flip Flop consists of a basic NOR flip-flop and two AND gates. The
outputs of two AND gates remain zero as long as the clock pulse is zero, regardless
of the S and R inputs.
2. When the clock pulse (CP) goes to 1, information from the S and R input is allowed
to reach the basic flip flop. The set state is reached with S=1, R=0 and CP=1.
3. To change to clear state inputs must be S=0, R=1 and CP=1.
4. When S=1, R=1 and if CP=1 or 0, the state of flip-flop is indeterminate
2. D Flip Flop
1. The D flip-flop is a modification of RS flip-flop. The NOR gates form the basic flipflop. The D input goes directly to S input and its complement is applied to R input.
2. When the CP is 0, the output of the AND gates are zero irrespective of any inputs.
3. When CP=0 or 1 and D=1; the flip-flop is driven to set state.
4. When CP=0 or 1 and D=1; the flip-flop is driven to reset state.
5. D flip-flop is also called as DATA (or) DELAY (or) TRANSPARENT flip-flop
3. JK Flip Flop
JK flip-flop is designed to as a refinement to the indeterminate state occurring in RS flipflop. The inputs J and K behave as S and R inputs.
1. When the inputs are applied to both J and K simultaneously, the flip-flop switches to
its complement state, that is if Q=1, it switches to Q=0.
2. The output Q is ANDed with K and CP inputs, so that the flip-flop is cleared during
a clock pulse only if Q=1 previously.

3. Similarly, the output Q is ANDed with J and CP inputs, so that the flip-flop is set
with a clock pulse only if Q=1 previously.
DISCUSSION QUESTIONS:
1. What is a sequential circuit?
A sequential circuit is a circuit in which the present output depends upon
the input and previous output.
2. What is a flip-flop?
In digital circuits, a flip-flop is a kind of bistable multivibrator, an electronic
circuit which has two stable states and thereby is capable of serving as one bit of
memory.
3. What are the applications of flip-flops?
Digital circuits, counter, memory register are the applications of flip-flops.
4. What are the types of flip-flop?
RS flip-flop, JK flip-flop, D flip-flop, T flip-flop,
Clocked SR flip-flop, JK master-slave flip-flop, Edge triggered flip-flop, Pulse
triggered flip-flop.
5. What are the characteristics of flip-flop?
i. It has two outputs (Q and Q)
ii. The two stable states are
When Q=1, Q=0 - set
When Q=0, Q=1 - reset
RESULT:
Thus Testing of ICs was done by verifying basic logic gates.
Exp. No:
Date :
DESIGN AND IMPLEMENTATION OF

ADDER/SUBTRACTOR USING LOGIC GATES
AIM:
To design and implement
(i)
Half Adder
(ii)
Full Adder
(iii)
Half Subtractor
(iv)
Full Subtractor using logic gates.
S.NO
1.
2.
3.
4.
COMPONENT NAME
Digital trainer kit
IC7408, IC7432, IC7486
Breadboard
Connecting wires
RANGE
QUANTITY
1
Each 1
1
Theory:
Combinational Circuits
The present output(s) depends on the present input(s) only.
Eg: Adder, Subractor, Encoder, Decoder, Multiplexers, Demultiplexers, Comparator Code
converters, and Parity generator and checker.
General Block Diagram
I1
I2
Combinational
Circuit
.
.
.
O1
O2
.
.
.
In
In- Input
On -Output
On
Half Adder
A Half Adder is a combinational circuit used for the addition of two bits. Thus we find
that the circuit needs two binary inputs (A and B) and two binary outputs. The input
variables designate the augend and addend bits, the output variables produce the Sum (S)
and the Carry (C).
Sum, S = A B=AB' +A'B
Carry, C= AB
Half Adder
Implementation
Truth Table
Sum
A
B
IC7486
carry
Input
A
B
0
0
0
1
1
0
1
1
IC7408
Output
S
C
0
0
1
0
1
0
0
1
Simplification using K-Map

Sum, S= A'B+AB' = A B
B
A 0
1
0 0
1
1
Carry, C
B
A 0
1
0 0
0
1
Carry, C= AB
Full Adder
A Full Adder is a combinational circuit used for the addition of three bits. Thus we find
that the circuit needs three binary inputs and two binary outputs. The input variables are
designated by A, B and Carry in (C in), the output variables produce the Sum (S) and the
Carry out (Cout).
Sum, S = A BCin =AB'Cin' +A'BCin'+A'B'Cin+ABCin
Carry, Cout = AB + ACin +BCin
Truth Table:
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
Cin
0
1
0
1
0
1
0
1
S
0
1
1
0
1
0
0
1
Cout
0
0
0
1
0
1
1
1
Implementation:
10
Simplification using K-Map

Sum Cin
AB 0 1
00 0 1
01 1 0
11 0 1
10 1 0
S=
AB'Cin'
Cout = AB + ACin +BCin
= Cin' (AB'+A'B) + Cin (A'B'+AB)
= Cin'(A B) + Cin (A B)
= A BC
out, Cout
CCarry
in
0
1
AB
00 0 0
01 0 1
11 1 1
10 0 1
+A'BCin'+A'B'Cin+ABCin
Half Subtractor
A Half Subtractor is a combinational circuit that subtracts two bits and produces their
difference. It has two outputs. One output generates the difference (D) and the second
output generates the borrow (B)
Difference D=AB+AB
Borrow
Bo=AB
Truth Table:
A
0
0
1
1
B
0
1
0
1
Bo
0
1
0
0
D
0
1
1
0
11
Function:
D=AB+AB= A B
Bo=AB
Implementation
IC7486
A
B
A B
IC7408
Bo=AB
Full Subtractor
Full subtractor is a combinational circuit that performs a subtraction between two bits .It
has three inputs (A, B, C) and two outputs (D, Bo).
Difference D=ABC+ABC+ABC+ABC
Borrow
Bo=AB+AC+BC
Truth Table
A
0
0
0
0
1
1
1
1
B
0
0
1
1
0
0
1
1
C
0
1
0
1
0
1
0
1
Bo
0
1
1
1
0
0
0
1
D
0
1
1
0
1
0
0
1
Logic Function
Difference D=ABC+ABC+ABC+ABC
Borrow Bo=AB+AC+BC
Logic Diagram:
12
A
B
C
D
IC7486
IC7404
Bo
IC7432
IC7408
PROCEDURE:
1. Obtain the required IC along with the Digital trainer kit.
2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.
DISCUSSION QUESTIONS
1. Difference between combinational circuits and sequential circuits?
Combinational circuit
When logic gates are connected
together to produce a specified
output for certain specified
combinations of input variables,
with no storage involved, the
resulting circuit is called
combinational logic.
Sequential circuit
In sequential circuits the output
variables dependent not only on
the present input Variables but
they also depend up on the past
history of these input variables.
2. Define half adder and full adder.

The logic circuit which performs the addition of two bits is a half adder.
The circuit which performs the addition of three bits is a full adder.
3. What is a k-map?
13
The Karnaugh map, also known as a Veitch diagram (K-map or KV-map

for short), is a tool to facilitate management of Boolean algebraic
expressions. A Karnaugh map is unique in that only one variable
changes value between squares; in other words, the rows and columns
are ordered according to the principles of Gray code.
4. Why are NAND and NOR gates known as universal gates?
The NAND and NOR gates are known as universal gates, since any
logic function can be implemented using NAND or NOR gates.
5. What are the applications of adder?
i. Arithmetic logic unit (ALU)
ii. Binary multiplier.
RESULT:
Thus the combinational circuits(ii)
Half Adder
(iii)
Full Adder
(iv)
Half Subtractor
(v)
Full Subtractor was designed and implemented using the logic gates.
DESIGN AND IMPLEMENTATION OF BINARY TO GRAY

CODE CONVERSION & VICE-VERSA USING LOGIC GATES
Exp. No:
Date
:
AIM:
To design and implement 4-bit

(i)
Binary to Gray code conversion
(ii)
Gray code to Binary conversion using logic gates.
COMPONENETS REQUIRED:
S.NO
1.
2.
3.
4.
COMPONENT NAME
Digital trainer kit
IC7486
Breadboard
Connecting wires
RANGE
THEORY:
14
QUANTITY
1
1
1
A code converter is a circuit that makes the two systems compatible even though
each uses a different binary code.
Since, we design a 4-bit converter; let A, B, C and D be the inputs
W, X, Y, and Z be the outputs.
(i) Binary to Gray code conversion
Gray code is also called as reflective code. In order to convert the given Binary
code into Gray code, the steps to be followed are,
1. Retain MSB as such.
2. Add the successive digits to obtain the four bit Gray code.
Advantage of Gray code
1. Gray code undergoes a single bit change.
2. Error detection is easier.
K-map simplification is used in order to obtain the output (Gray code) in terms of the
input A, B, C.
Implementation
A
W=A
IC7486
x A B
yBC
Z C D
TRUTH TABLE
(i) Binary to Gray code conversion
15
Binary code
A B C
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Gray code
W X
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
Y
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
Z
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
(ii) Gray code to Binary code conversion

In order to convert the given Gray code into Binary code, the steps to be
followed are,
1. Retain MSB as such.
2. Add the successive digit with the previous result to obtain the four bit Binary
code.
Logic Diagram
W X Y Z
A=W
B W X
Gray code
Binary code
W X Y Z A B C CD W X Y
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0 D1 W X Y Z
0
0
1
1
0
0
1
0
0
0
1
0
0 IC7486
0
1
1
0
1
1
0
0
1
0
0
Truth Table
0
1
1
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
0
0
1
1
1
1
1
0
0
1
0
0
0
1
1
0
1
1
0
0
1
1
1
1
1
1
0
1
0
1
1
1
0
1
0
1
1
1
0
1
0
1
1
0
016
1
0
1
1
1
1
0
1
1
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
PROCEDURE:
3. Find the output in terms of inputs using k-map.
1. What are applications of code converter?
i) Electromechanical switches.
ii) Digital communication.
2. What are the advantages of gray code?
a .Single output changes at a time
b .Multiphase, multifrequency clock generator.
3. Give another name of gray code?
Reflected binary code.
4. Define fan in.
Fan in is defined as the total number of inputs to a logic gate.
5. Define noise margin.
17
It is the maximum noise voltage added to an input signal of a

digital circuit that does not cause an undesirable chance in circuit
output.
RESULT:
Thus the 4-bit
(i)
Binary to Gray Code conversion
(ii)
Gray code to Binary code converter were designed and implemented using the
logic gates.
Exp. No:
Date 3 :
DESIGN AND IMPLEMENTATION OF BCD TO EXCESSCODE CONVERSION & VICE-VERSA USING LOGIC GATES
AIM
To design and implement 4-bit
(i)
BCD to Excess-3 code conversion
(ii)
Excess-3 code to BCD conversion using logic gates.
S.NO
COMPONENT NAME
1.
Digital trainer kit
2.
IC7408, IC7432, IC7486
3.
Breadboard
4.
Connecting wires
RANGE
18
QUANTITY
1
Each 1
1
THEORY:
A binary number of n digits can be represented by n circuit elements, each
having an output of 1or 0. Binary code is used to represent any discrete element of
information which is different among a group of quantities. The availability of large
codes for the same elements of information results in the use of different codes by
different digital systems. Thus a conversion circuit must be inserted between the two
systems if they use different codes. A code converter is a circuit that makes the two
systems compatible even though each uses a different binary code.
Since, we design a 4-bit converter; let A, B, C and D be the inputs
W, X, Y, and Z be the outputs.
An Excess-3 code is obtained by adding 3 to each digit. For BCD code-10
combinations are only possible. Even though there are 4 inputs with 16 possible
combinations, the remaining 6 combinations are assumed to be dont care terms as they
will never occur. Hence the dont care terms (denoted by X) can be assigned an output
of 0 or 1. K-map simplification is used in order to obtain the output (Excess-3 code) in
terms of the input A, B, C and D
A
B
Logic diagram for BCD to Excess 3 code conversion
B
D
B'
C
B'
D
C'
D
'
Department of Electrical andCElectronics Engg
19
D
D
TRUTH TABLE:
BCD code
A B C
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
D
0
1
0
1
0
1
0
1
0
1
Excess-3 code
W X Y Z
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
3
1
3
2
12
Excess-3 code to BCD conversion
The BCD code can be obtained from Exces-3-code by applying reverse procedure
of the above conversion. i.e, By subtracting 3 from the Excess-3-code.
3
4
5
1
2
13
12
Logic Diagram Of Excess-3 To Bcd Conversion

W X Y Z
1
1
2
A
1
20
Excess-3 code
W X Y Z
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
BCD code
A B C
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
1 0 0
1 0 0
D
0
1
0
1
0
1
0
1
0
1
Truth Table
PROCEDURE:
3. Find the output in terms of inputs using k-map.
21

1. What is meant by code converter?
A converter used to convert one form of code to another form is called a
code Converter.e.g binary to gray code converter, gray to binary code converter.
2. What is a Logic gate?
Logic gates are the basic elements that make up a digital system. The
electronic
gate is a circuit that is able to operate on a number of binary inputs
in order to perform a particular logical function.
3. What is the Binary coded decimal?
A binary coded decimal is a combination of four binary digits that represent
decimal numbers.
4. What is the Binary number?
Binary number system consists of 0 and 1.
RESULT:
Thus the 4-bit
(i)
BCD to Excess-3 Code
(ii)
Excess-3-code to BCD code conversion were designed and implemented
using the logic gates.
Exp. No:
Date
:
DESIGN AND IMPLEMENTATION OF 8-BIT ODD/EVEN

PARITY GENERATOR, CHECKER USING IC74180
AIM
To implement
(i)
Even Parity Generator/Checker
(ii)
Odd Parity Generator/Checker using IC74180
S.NO
1.
2.
3.
4.
COMPONENT NAME
Digital trainer kit
IC74180
Breadboard
Connecting wires
RANGE
QUANTITY
1
1
1
THEORY:
A parity generator is a circuit that, given an n-1 bit data word, generates an extra
(parity) bit that is transmitted with the word. The value of this parity bit is determined by
the bits of the data word.
22
In an even parity scheme, the parity bit is a 1 if there is an odd number of 1's in the
data word. Thus when we examine all the bits transmitted (data word + parity), we see an
even number of ones (thus "even" parity).
At the receiving end of the transmission, a parity checker uses this extra information
to detect single-bit errors in the transmitted data word. It does so by regenerating the
parity bit in the same manner as the generator and comparing the two parity bits.
Disagreement between these bits means that one of the transmitted bits is incorrect,
though the checker cannot determine which bit is in error. Note that single-bit parity
scheme is unable to detect an even number of errors (e.g. 4 bits are wrong).
PROCEDURE:
3. Connections are made as per the logic diagram.
Design
Pin Diagram of IC74180 (8-bit Parity Generator/Checker)
A
B
EVEN
ODD
Even O/P
Odd O/P
Gnd
14
13
12
11
10
9
8
I
C
7
4
1
8
0
Vcc
H
G
F
E
D
C
Truth table of IC 74180

Sum of 1s at
A through H
Even
Even Odd
input input
1
0
Even
output
1
23
Odd
output
0
Odd
Even
Odd
For example
Generator
Even Odd
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
0
0
1
1. What is meant by parity bit?
A parity bit is an extra bit included with a message to make the total
number of 1's either even or odd.
2. What is an parity generator?
The circuit that generates the parity bit in the transmitter is called
parity generator.
3. What is an parity checker?
The circuit that checks the parity an receiver is called parity checker.
4. What is an odd parity?
A binary digit that is added to ensure that the number of bits with value
of one in a given set of bits is always odd is an odd parity.
5. What is an even parity?
A binary digit that is added to ensure that the number of bits with value
of one in a given set of bits is always odd is an even parity.
24
RESULT
Thus the implementation of
1. Even Parity Generator/Checker
2. Odd Parity Generator/Checker using IC74180
Exp. No:
Date :
DESIGN AND IMPLEMENTATION OF 4:1 MULTIPLEXER

AND 1:4 DEMULTIPLEXER
AIM:
(i)
4x1 Multiplexer
(ii)
1x4 Demultiplexer using logic gates.
S.NO
1.
2.
3.
4.
COMPONENT NAME
Digital trainer kit
IC7411, IC7432, IC7404
Breadboard
Connecting wires
RANGE
THEORY:
25
QUANTITY
1
Each 1
1
Multiplexer (or) Data selector (or) MUX

A digital multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it into a single output line. The selection of a
particular input line is controlled by a set of selection lines (S0, S1 Sn-1)
Block Diagram
I0
I1
.
.
.
I inputs
Y output
S Selection lines
.
.
.
In-1
2nx 1
MUX
S0, S1 Sn-1
Kinds:
2x1 MUX, 4x1 MUX, 16x1 MUX, 32x1 MUX and so on..
2x1 MUX
A logical symbol for 2 inputs (I0, I1) MUX consists of 1 selection line - S0 and one
output (Y).
4x1 MUX
A 4-to-1 line multiplexer consists of 4 inputs (I0, I1, I2, I3) and 2 selection lines (S0,
S1 ) . The circuit operation is as follows. Consider S0, S1, as 10. The AND Gate associated
with input I2 has two of its inputs as 1 and the third input is connected to I 2. For the other
AND gates at least one input is zero which makes the net output from the AND gate to be
zero. The OR gate value is now equal to the value of I2 ,
I0
I1
I2
I3
S1
Logic diagram:
S0
4-to-1 line MUX (or) 4x1MUX
S1 '
Y
Y
I0
I1
I2
I3
26
I1 S0 'S1 +
I2 S0 S1'+
I2 S 0 S 1
S1
0
1
0
1
I1
Truth Table
S0
0
0
1
1
S0 '
I0
S1
Y= I0 S0 'S1 '+
S0
7411
I2
4x 1
MUX
I3
Demultiplexer (or) Data distributor (or) DEMUX

A digital demultiplexer is a combinational circuit that accepts a single input and
distributes it into the specified number of output lines. The selection of a particular output
line is controlled by a set of selection lines (S0, S1 Sn-1)
Block Diagram
Din
1x2n
DEMUX
.
.
.
Y0
Y1
.
.
.
Yn-1
D inputs
Y output
S Selection lines
S0, S1 Sn-1
Kinds:
1x2 DEMUX, 1x 4 DEMUX, 1x 16 DEMUX, 1x 32 DEMUX and so on..
1x2 DEMUX
A logical symbol for 1 input (Din ) MUX consists of 1 selection line - S0 and one
output (Y).
1x4 DEMUX
A 1-to-4line demultiplexer consists of 1 input(D 0) ,4 outputs (Y0, Y1, Y2, Y3) and 2
selection lines (S0, S1 ) . The circuit operation is as follows. Consider S 0, S1, as 10. The
AND Gate associated with output Y2 has two of its inputs as 1 and the third input is
connected to Din. For the other AND gates at least one input is zero which makes the net
output from the AND gate to be zero. Thus the output gets distributed in the I 2. Hence,
DEMUX is also called as a Data distributor.
S0
1-to-4 line DEMUX (or) 1x4 DEMUX
S1
PROCEDURE:
4. In 4x1 MUX the inputs are varied for checking the truth table.
5 In 1x4 DEMUX the selection line is varied to verify the truth table
Logic Diagram
Y0
Y1
Y2
S1
27
Y3
S0
Y0
Y1
Y2
Y3
S1 '
1x4
DEMUX
S0 '
Din
Din
7411
Truth Table
S0
0
0
1
1
S1
0
1
0
1
Y3
0
0
0
Din
Y2
0
0
Din
0
Y1
0
Din
0
0
Y0
Din
0
0
0
28
1. Define multiplexer?
A multiplexer is a combinational circuit that selects one digital
information from several sources and transmits the selected information on a
single output line.
2. What is demux?
Demultiplexer is a circuit that receives information on a single line and
transmits this information on one of 2n possible output lines. A demultiplexer is a
decoder with an enable input.
3. What is combinational circuit? Give an example.
A combinational circuit consists of logic gates whose outputs at any time
are determined from the present combination of inputs. Examples of
combinational circuits are adder, coder, magnitude comparator etc.
4. Where Multiplexers are used?
29
It is used in data selection, data routing, parallel to serial conversion, logic

function generation.
5. What is the other name for demultiplexer?
As the serial data is changed to parallel data, the input caused toappear aon
one of the n output lines, the demultiplexer is also called as distributor or a
serial to parallel converter.
RESULT:
Thus the combinational circuits
(i) 4x1 Mux (Multiplexer)
(ii) 1x4 Demux (Demulitplexer) were designed and implemented using the logic
gates.
3-to-8 Decoder (or) 3x8 Decoder
A
B
3x8
Decoder
.
.
.
Truth Table
30
D0
D1
D7
I0
I1
I2
I3
S1
S0
4-to-1 line MUX (or) 4x1MUX
S0
S1 '
S1
I3
Truth Table
S0
0
0
1
1
S1
0
1
0
1
Y
I0
I1
I2
I3
31
I1 S0 'S1 +
I2 S0 S1'+
I2 S 0 S 1
I2
Y= I0 S0 'S1 '+
I1
7411
S0 '
4x 1
MUX
I0
Exp. No:
Date
:
DESIGN AND IMPLEMENTATION OF 4:1 MULTIPLEXER AND 1:4

DEMULTIPLEXER
AIM:
(iii)
4x1 Multiplexer
(iv)
1x4 Demultiplexer using logic gates.
32
33
34
35
36
37
38
S.NO
1.
2.
3.
4.
COMPONENT NAME
Digital trainer kit
IC7411, IC7432, IC7404
Breadboard
Connecting wires
RANGE
QUANTITY
1
Each 1
1
THEORY:
Multiplexer (or) Data selector (or) MUX
A digital multiplexer is a combinational circuit that selects binary information
from one of many input lines and directs it into a single output line. The selection of a
particular input line is controlled by a set of selection lines (S0, S1 Sn-1)
39
Block Diagram
I0
I1
.
.
.
2nx 1
MUX
I inputs
Y output
S Selection lines
.
.
.
In-1
S0, S1 Sn-1
Kinds:
2x1 MUX, 4x1 MUX, 16x1 MUX, 32x1 MUX and so on..
2x1 MUX
A logical symbol for 2 inputs (I0, I1) MUX consists of 1 selection line - S0 and one
output (Y).
4x1 MUX
A 4-to-1 line multiplexer consists of 4 inputs (I0, I1, I2, I3) and 2 selection lines (S0,
S1 ) . The circuit operation is as follows. Consider S0, S1, as 10. The AND Gate associated
with input I2 has two of its inputs as 1 and the third input is connected to I 2. For the other
AND gates at least one input is zero which makes the net output from the AND gate to be
zero. The OR gate value is now equal to the value of I2 ,
1-to-4 line DEMUX (or) 1x4 DEMUX
S1
Y0
S1 '
Y1
S1
Y3
Y2
S0
7411
S0 '
1x4
DEMUX
Y0
Y1
Y2
Y3
Din
Din
S0
Logic Diagram
40
Truth Table
S0
0
0
1
1
S1
0
1
0
1
Y3
0
0
0
Din
Y2
0
0
Din
0
Y1
0
Din
0
0
Y0
Din
0
0
0
Demultiplexer (or) Data distributor (or) DEMUX

A digital demultiplexer is a combinational circuit that accepts a single input and
distributes it into the specified number of output lines. The selection of a particular output
line is controlled by a set of selection lines (S0, S1 Sn-1)
Block Diagram
Din
1x2
DEMUX
.
.
.
Y0
Y1
.
.
.
Yn-1
D inputs
Y output
S Selection lines
S0, S1
Sn-1
Kinds:
1x2 DEMUX, 1x 4 DEMUX, 1x 16 DEMUX, 1x 32 DEMUX and so on..
1x2 DEMUX
A logical symbol for 1 input (Din ) MUX consists of 1 selection line - S0 and one
output (Y).
1x4 DEMUX
A 1-to-4line demultiplexer consists of 1 input(D 0) ,4 outputs (Y0, Y1, Y2, Y3) and 2
selection lines (S0, S1 ) . The circuit operation is as follows. Consider S 0, S1, as 10. The
AND Gate associated with output Y2 has two of its inputs as 1 and the third input is
connected to Din. For the other AND gates at least one input is zero which makes the net
output from the AND gate to be zero. Thus the output gets distributed in the I 2. Hence,
DEMUX is also called as a Data distributor.
PROCEDURE:
41
5.
6.
7.
8.
5
Obtain the required IC along with the Digital trainer kit.

Connect zero volts to GND pin and +5 volts to Vcc .
Apply the inputs to the respective input pins.
In 4x1 MUX the inputs are varied for checking the truth table.
In 1x4 DEMUX the selection line is varied to verify the truth table
42
6. Define multiplexer?
A multiplexer is a combinational circuit that selects one digital
information from several sources and transmits the selected information on a
single output line.
7. What is demux?
Demultiplexer is a circuit that receives information on a single line and
transmits this information on one of 2n possible output lines. A demultiplexer is a
decoder with an enable input.
8. What is combinational circuit? Give an example.
A combinational circuit consists of logic gates whose outputs at any time
are determined from the present combination of inputs. Examples of
combinational circuits are adder, coder, magnitude comparator etc.
9. Where Multiplexers are used?
It is used in data selection, data routing, parallel to serial conversion, logic
function generation.
10. What is the other name for demultiplexer?
As the serial data is changed to parallel data, the input caused toappear aon
one of the n output lines, the demultiplexer is also called as distributor or a
serial to parallel converter.
43
RESULT:
(iii) 4x1 Mux (Multiplexer)
(iv) 1x4 Demux (Demulitplexer) were designed and implemented using the logic
gates.
3-to-8 Decoder (or) 3x8 Decoder
A
B
3x8
Decoder
.
.
.
D0
D1
D7
Truth Table
Inputs
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
D7
0
0
0
0
0
0
0
1
D6
0
0
0
0
0
0
1
0
D5
0
0
0
0
0
1
0
0
44
Outputs
D4 D3
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
D2
0
0
1
0
0
0
0
0
D1
0
1
0
0
0
0
0
0
D0
1
0
0
0
0
0
0
0
Exp. No:
Date
:
DESIGN AND IMPLEMENTATION OF 3-T0-8 DECODER AND

8-TO -3 ENCODER
AIM:
(i)
3x8 Decoder
(ii)
8x3 Encoder using logic gates.
S.NO
1.
2.
6.
7.
COMPONENT NAME
Digital trainer kit
IC7411, IC7432, IC7404
Breadboard
Connecting wires
RANGE
THEORY:
Decoder
45
QUANTITY
1
Each 1
1
A binary code of n inputs can be represented as 2n (or less) Min terms. Decoder
is a combinational logic circuit that accepts a set of inputs that represents a binary
number and activates only the output that corresponds to that input number.
Its generally represented as n-to-m line decoder (or) (n x m) decoder where, m2n
Block Diagram
A0
A1
.
.
.
nxm (or)
n
m
Decoder
.
.
.
An-1
D0
D1
Dn-1
A inputs
D outputs
(only 1 o/p is active for each i/p).
Kinds:
C
C'
B'
IC7404
A'
Logic Diagram
1. 2-to-4 line decoder

2. 3-to-8 line decoder
3. 4-to-10 line decoder (or) Binary-to-decimal decoder.
1
2
13
IC7411
D0=A'B'C'
12
D1=A'B'C
D2=A'BC'
D3=A'BC
D4=AB'C'
D5=AB'C
D6=ABC'
46
D7=ABC
3-to-8 Decoder
(or) Binary-to-Octal decoder (or) 1-out-of 8 Decoder
n=3(inputs); m2n ; i.e, m=8(outputs).
The 3 inputs are decoded into 8 outputs, each output representing one of the min terms. A
particular application of this decoder would be a binary to octal conversion. The 3
invertors provide the complement of the inputs and each one of the AND gates generates
the min terms.
Encoder
Encoder is a combinational logic circuit that performs a reverse decoder function.
i.e, An Encoder accepts an active level on one of its inputs representing a digit such as a
decimal (or) octal and converts it to a coded output lines such as binary or BCD. An
encoder has 2n (or less) input lines and n output lines.
Its generally represented as m-to-n line encoder (or) (m x n) encoder where, m2n
Block Diagram
I0
I1
.
.
.
In-1
mxn (or)
m n
Encoder
.
.
.
A0
A1
An-1
I inputs
A outputs
(only 1 o/p is active for each i/p).
8-to-3 Encoder
n=3; m2n ; i.e,m=8. (m inputs and n outputs).
The Encoder can be implemented with OR gates. The inputs are determined directly from
truth table.
PROCEDURE:
1.
2.
3.
4.
Obtain the required IC along with the Digital trainer kit.

Connect zero volts to GND pin and +5 volts to Vcc .
Apply the inputs to the respective input pins.
Verify the output with the truth table.
47
8x3 Encoder
D0
D1
D7
8x3
.
.
.
Encoder
Truth Table
D7
0
0
0
0
0
0
0
1
D6
0
0
0
0
0
0
1
0
D5
0
0
0
0
0
1
0
0
Inputs
D4 D3
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
D2
0
0
1
0
0
0
0
0
D1
0
1
0
0
0
0
0
0
D0
1
0
0
0
0
0
0
0
A
0
0
0
0
1
1
1
1
Outputs
B C
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
Logic Diagram
D7
D6 D5 D4 D3 D2 D1
D0
A=D4+D5+D6+D7
B=D2+D3+D6+D7
C=D1+D3+D5+D7
48
1. Define Decoder?
A decoder is a logic circuit that converts an n-bit binary input code into 2n
output lines, such that each output line will be activated for only one of the
possible combinations of inputs.
2. What is binary decoder?
A decoder which has an n-bit binary i/p code and a one activated output
out of 2n output code is called binary decoder. It is used when it is necessary to
activate exactly one of 2 n out puts based on an n - bit input value.
3. Define Encoder?
An encoder has 2n input lines and n output lines. In encoder the output lines
generate the binary code corresponding to the input value.
4. What is priority Encoder?
A priority encoder is an encoder circuit that includes the priority function. In
priority encoder, if 2or more inputs are equal to 1 at the same time, the input
having the highest priority will take precedence.
5. Mention some applications of decoders.
Decoders are used in counter systems, analog to digital converters, used to
drive display system
RESULT:
(i)
3x8 Decoder
(ii)
8x3 Encoder were designed and implemented using the logic gates.
49
4-bit Ripple Counter

Logic high
JA
CLK
QA
JB
FF A
KA
QB
JC
FF B
Q'A
KB
Q'B
KC
QB
QC
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
QB
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
50
QA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
QD
FF C
Q'C
KD
QC
Truth Table (state transition table)

QD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
JD
FF C
QA
CLK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
QC
Q'D
QD
Exp. No:
Date
:
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS /

ASYNCHRONOUS COUNTERS
AIM:
To design a 4-bit Asynchronous (Ripple) counter using the JK flip-flop.
To design a 3-bit Synchronous (Parallel) up/down counter using the JK flip-flop.
S.NO
COMPONENT NAME
1.
Digital trainer kit
2.
IC7408, IC7432, JK fliflop
3.
Breadboard
4.
Connecting wires
RANGE
QUANTITY
1
Each 1
1
THEORY:
Counter:
A counter is a sequential circuit that undergoes through a prescribed sequence of
binary states upon the application of clock pulse.
Types:
1. Asynchronous Counter
2. Synchronous Counter
Asynchronous Counter:
It is otherwise called as serial or ripple counter. In an asynchronous counter, each
flip flop is triggered by the output from the previous flip flop which limits its speed of
operation. The settling time in asynchronous counters is the cumulative sum of individual
settling times of flip flops. The first stage of the counter thus switches first on the
application of a clock pulse to the flipflop and successive stages change their states in
turn causing a ripple through effect of the count pulses. As the triggers move through the
flip flops like a ripple, it is called ripple counter.
Synchronous Counter
Each FF is applied with the clock pulse at the same time so as to trigger the FF
simultaneously.
General representation of the counter
n-bit counter requires n FF,
has 2n states,
counts from 0 to 2n -1,
called as MOD n counter or divide by n counter.
51
3-bit Synchronous up/down-counter

UP/ DOWN
Logic high
JA
QA
JB
QB
A
KA
JC
B
Q'A
KB
Truth Table (UP counter)

CLK
0
1
2
3
4
5
6
7
QC
0
0
0
0
1
1
1
1
QB
0
0
1
1
0
0
1
1
QA
0
1
0
1
0
1
0
1
QB
1
1
0
0
1
1
0
QA
1
0
1
0
1
0
1
Truth Table (Down counter)

CLK
0
1
2
3
4
5
6
QC
1
1
1
1
0
0
0
C
Q'B
CLK
52
QC
KC
Q'C
3-bit Synchronous up-counter

Requires 3 JK FFs
Has 23 = 8 states (counts from 0 up-to 7)
Called as MOD-3 synchronous counter (or) divide by 3 synchronous counter.
1. The counter progresses through a binary count of 0 to 7 and then recycles to 0.
2. The clock pulse is applied simultaneously.
3. Connect the normal output of the previous FF to the next FF input.
3-bit Synchronous down-counter
Requires 3 JK FFs
Has 23 = 8 states (counts from 7 down-to 0)
Called as MOD-3 synchronous counter (or) divide by 3 synchronous counter.
1. The counter progresses through a binary count of 7 to 0 and then recycles to 7.
2. The clock pulse is applied simultaneously.
3. Connect the complemented output of the previous FF to the next FF input.
3-bit Synchronous up/down-counter
An up/down counter is capable of progressing in either direction through a certain
sequence. This counter is sometimes called as a bidirectional counter
Illustration:
1. Connect the i/ps of the first JK FF to logic HIGH.
2. Apply the control signal UP/ DOWN.
3. If the control signal is 1, the upper AND gates are enabled and the counter acts
as an up counter.
4. If the control signal is 0, the lower AND gates are enabled and the counter acts
as down counter.
PROCEDURE:
Obtain the required flip-flop along with the Digital trainer kit.
1.
Connect zero volts to GND pin and +5 volts to Vcc.
2.
Connections are made as per the logic diagram.
3.
Apply the clock pulse in order to load the data into the flip-flop.
4.
Verify the truth table.
5.
53
54
1. What do you mean by present state?
The information stored in the memory elements at any given time defines the
present state of sequential circuit.
2. What do you mean by next state?
The present state and the external inputs determine the outputs and the next
state of the Sequential circuit.
3. Define synchronous sequential circuit
In synchronous sequential circuits, signals can affect the memory elements
only at discrete instant of time.
4. Define Asynchronous sequential circuit?
In asynchronous sequential circuits change in input signals can affect memory
element at any instant of time
5. What do you mean by counters?
A counter, by function is a sequential circuit consisting of set of flip flops
connected in a suitable manner to count the sequence of input pulses presented to
it in digital form.
RESULT:
Thus the 3-bit Synchronous (Parallel) up/down counter and 4 bit asynchronous
counter was designed and verified using JK Flipflop.
55
1. SISO (Serial in Serial out)
Data
in
DA QA
DB QB
DC QC
FF A
FF B
FF C
Q'A
Q'B
DD QD
Data
out
FF D
Q'C
Q'D
MSB
LSB
CLK
CLK
0
1
2
3
4
5
6
7
QA
0
1
0
1
0
0
0
0
QB
0
0
1
0
1
0
0
0
QC
0
0
0
1
0
1
0
0
QD
0
0
0
0
1(MSB)
0
1
0(LSB)
2. SIPO (Serial in Parallel out)

Data in D Q
A
A
FF A
Q'A
DB QB
DC QC
FF B
FF C
Q'B
DD QD
FF D
Q'C
Q'D
MSB
CLK
Data
out
LSB
QA
QB
56
QC
QD
Exp. No:
Date
:
IMPLEMENTATION OF SISO, SIPO, PISO & PIPO SHIFT

REGISTERS USING D FLIP-FLOP
AIM:
To implement the basic kinds of shift registers using D flip-flop.
S.NO
1.
2.
3.
4.
COMPONENT NAME
Digital trainer kit
D fliflop
Breadboard
Connecting wires
RANGE
QUANTITY
1
4
1
THEORY:
Registers:
A group of binary cells (or) flip-flops used for storing the information.
Shift register: A register which is capable of shifting the information either to right/left is
known as shift register.
Types:
1. SISO (Serial in Serial out)
2. SIPO (Serial in Parallel out)
3. PISO (Parallel in Serial out)
4. PIPO (Parallel in Parallel out)
Assume a 4-bit shift register implemented using D FF. (Eg data: 0101)
Initially all the FF are under RESET condition. Loading the FF starts from LSB.
1. At the end of each clock pulse; a new data is stored inside the FF.
2. At the end of 4th clock pulse; data is loaded into the FF.
3. At the end of 5th clock pulse; data is shifted out.
Data is entered in a serial fashion. Once the data are stored, each bit appears on its
respective output line rather than on a bit-by-bit fashion.
Serial in- Serial out Shift Register:
This type of shift register accepts data serially; i.e one bit at a time on a single
input line.It produces the stored information on its single output also in serial form. Data
may be shifted left using left shift register or shifted right using shift right register.
57
CLK
0
1
2
3
4
QA
0
1
0
1
0
QB
0
0
1
0
1
QC
0
0
0
1
0
QD
0
0
0
0
1(MSB)
3. PIPO (Parallel in Parallel out)

A
DA QA
DB QB
DC QC
FF A
FF B
FF C
Q'A
Q'B
DD QD
FF D
Q'C
Q'D
MSB
CLK
LSB
QA
QB
58
QC
QD
Serial-in-parallel out Shift register:

It consists of one serial input and outputs are taken from all the flip-flops
parallely. In this register, data is shifted in serially but shifted out in parallel. In order to
shift the data out in parallel, it is necessary to have all the data available at the outputs at
the same time. Once the data is stored, each bit appears on its respective output line and
all the bits are available simultaneously rather than on a bit by bit basis as with the serial
outputs.
Parallel in - Serial out Shift register:
For a register with parallel data inputs, the bits are entered simultaneously into the
respective flip-flops rather than a bit- by bit basis on one line.
Parallel-in-Parallel out register:
In this type of register, data inputs can be shifted either in or out of the register in
parallel. Also in this register, there is no interconnection between successive flip flops
since no serial shifting is required. Therefore, the moment the parallel entry of the data is
accomplished, the respective bits will appear at the parallel outputs.
PROCEDURE:
Obtain the required flip-flop along with the Digital trainer kit.
1.
Connect zero volts to GND pin and +5 volts to Vcc.
2.
3. Connections are made as per the logic diagram.
4. Apply the clock pulse in order to load the data into the flip-flop.
5. Verify the truth table.
59
4. PISO (Parallel in Serial out)

i/p
i/p
i/p
Shift/Load
i/p
DA QA
DB
FF A
QB
DC
FF B
Q'A
QC
FF C
Q'B
DD QD
FF D
Q'C
MSB
Q'D
LSB
CLK
Loading entering the data into the FF

Shifting reading the date out of the FF
CLK
0
1
2
3
4
5
QA
0
0
0
0
0
0
QB
0
1
0
0
0
0
QC
0
0
1
0
0
0
60
QD
0
1(MSB)
0
1
0(LSB)
0
Serial
out
1.
If a serial in serial out shift register has N stages and if the clock
frequency is f, What will be the time delay between input and output?
N
The time delay between input band output is TD = f

2.
What are registers?

A register is a group of binary cells. A register with n cells can store any
discrete quantity of information that contains n bits. The state of a register is an ntuple number of 1's and 0's, with each bit designating the state of one cell in the
register.
3.
What is meant by register transfer?

A register transfer operation is a basic operation in digital systems. It
consists of transfer of binary information from one set of registers into another set
of registers. The transfer may be direct from one register to another, or may pass
through data processing circuits to perform an operation.
4.
Define shift Registers

The binary information in a register can be moved from stage to stage
within the register or into or out of the register upon application of clock pulses.
This type of bit movement or shifting is essential for certain arithmetic and logic
operations used in microprocessors. This gives rise to a group of registers called
shift registers.
5. What are the types of shift register?
1. Serial in serial out shift register?
2. Serial in parallel out shift register
3. Parallel in serial out shift register
4. Parallel in parallel out shift register
5. Bidirectional shift register shift register.
RESULT:
Thus the 4-kinds of shift registers were implemented using D flip-flop.
61
CIRCUIT DIAGRAM:
INVERTING AMPLIFIER:
Rf = 10K
R1= 5K
LM741
10K
3
Rcomp
Vi
4
4-V
Vo
+V
NON INVERTING AMPLIFIER:
Rf = 10K
R1= 5K
LM741
10K
3
Rcomp
Vi
4
4-V
62
+V
Vo
Exp. No:
Date
:
(A)
(B)
SLEW RATE VERIFICATION
INVERTING AND NON INVERTING AMPLIFIERS
AIM:
To study the operation of an inverting & non inverting amplifier and to verify the
slew rate.
S.NO
1.
2.
3.
4.
5.
6.
7.
DESIGN:
COMPONENT NAME
Regulated variable power
supply
Signal generator
CRO
Resistors
Op- amp
Breadboard
Connecting wires
RANGE
(0-30) Volts
QUANTITY
1
1MHz
20MHz
10K,5K,
LM741
1
1
1,1
1
FORMULA USED:
1.
Gain of the inverting amplifier:
A = -(Rf / R1)
V0 = AVin
V0 / Vin = - (Rf / R1) ---------------------------- (1)

Assume
A = 2,
Input voltage Vin = 1Volts

R1 = 5 K
Substitute all values in equation (1) and find Rf value.
2.
Gain of the non inverting amplifier: Vo/ Vin =
(Rf + R1) / R1
A = 1 + (Rf/R1) -----------------(2)
Assume
A = 2,
Input voltage Vin = 1Volts

R1 = 10 K
63
Substitute all values in equation (2) and find Rf value.

Slew rate
44-V
LM741
3
7
Vi
Vo
Offset Null
No Connection
Inverting input
V+
Non - Inverting input
Output
Offset Null
+V
V-
IC741
MODEL GRAPH:
Inverting Amplifier
Input Voltage
(Volts)
Time (ms)
Output Voltage
(Volts)
Time (ms)
64
3.
Measurement of slew rate:
Slewrate
2fVm V
s
106
THEORY:
1) Inverting amplifier:
Input signal Vi is applied to the inverting input terminal through R1 and
non-inverting input terminal of op-amp is grounded. The output voltage V o is fed back to
the inverting input terminal through the Rf R1 network where Rf is the feedback resistor.
Therefore the closed loop gain of the inverting amplifier is
Acl =
Rf
Vo
=
R1
Vi
The negative sign indicates a phase shift of 180o between Vi and Vo. Since
inverting input terminal is at virtual ground, the effective input impedance is R 1. The
value of R1 should be fairly large to avoid loading effect. This however limits the gain
that can be obtained from the circuit. A load resistor R L is usually kept at the output in
actual practice otherwise, the input impedance of the measuring device such as
oscilloscope or DVM acts as the load.
2) Non inverting amplifier:
If this signal is applied to the non-inverting input terminal and feedback is
given to the inverting input terminal, the circuit amplifies without inverting the input
signal. Such a circuit is called Non-Inverting amplifier. So, it may be noted that the noninverting amplifier is also a negative feedback system as output is being feedback to the
inverting input terminal. Therefore the closed loop gain for non-inverting amplifier is
Acl =
Rf
Vo
= 1
R1
Vi
The gain can be adjusted to unity or more by proper selection of resistors

Rf and RL. So, compared to the non-inverting amplifier, the input resistance of the non-
65
inverting amplifier is extremely large as the op-amp draws negligible current from the
signal source.
Non-Inverting Amplifier
Input Voltage
(Volts)
Time (ms)
Output Voltage
(Volts)
Time (ms)
Slew Rate Verification

Input Voltage
(Volts)
Time (ms)
Output Voltage
(Volts)
Time (ms)
66
3) Slew rate:
It is the parameter that determines the op-amp for high frequency applications.
It is defined as the maximum change in the output voltage caused by a step input
voltage and is expressed in V/s. Usually op-amp with wide band width will have higher
slew rates. An ideal slew rate is infinite which means that op-amps output voltage should
change instantaneously in response to input step voltage. Practical IC op-amps have
specified slew rates from 0.1V/ s to above 1000 V/ s. It is also a function of
temperature and generally decreases with increase in temperature. The slew rate is
normally caused by a capacitor within or outside an op-amp to prevent oscillation. This
capacitor which prevents the output voltage from responding immediately to a fast
change in input. The rate at which the voltage across the capacitor Vc increases is given
dVc
I
dt
C
by,
It is the maximum current furnished by op-amp to the capacitor C. For obtaining faster
slew rate op-amp should have either a higher current or a small compensating capacitor.
Therefore slew rate is given by
Slewrate
2fVm V
s
10 6
(a)PROCEDURE:
Inverting and non inverting amplifier:
1. Connect the circuit as per the circuit diagram.
2. For the inverting amplifier the input voltage is given to the inverting terminal of opamp.
3. Measure the output voltage using CRO and enter the readings in the tabular column..
4. For non inverting amplifier, the input is given to the non inverting terminal.
5.
Measure the output voltage using CRO and enter the readings in the tabular column.
67
6. Calculate the values of gain using formula (both theoretical & practical) and enter the
readings in the tabular column.
TABULAR COLOUMN:
INVERTING AMPLIFIER:
Vi (volts)
Ri K
Vo (volts)
Rf K
Theoretical
Practical
Gain
Gain
Theoretical
Practical
Gain
Gain
NON INVERTING AMPLIFIER:

Vi (volts)
Ri K
Vo (volts)
Rf K
SLEW RATE VERIFICATION:

Frequency (K Hz)
Vi (volts)
Vo (Volts)
68
(b)PROCEDURE:
Slew Rate
2. Adjust the input sine wave signal generator so that the output is 1 Volt peak sine
wave at 1 K Hz.
3. Slowly increase the input signal frequency until the output gets just distorted.
4. Calculate the Slew rate, using above formula.
5. Now give a square wave input and repeat above procedure.
6. Increase the input frequency slowly until the output is just barely a triangular
wave. Calculate the slew rate.
69
70
1. What are the characteristics of an ideal operational amplifier?
Open loop voltage gain, AOL = , Input impedance, Ri = ,
Output impedance, Ro = 0,
Bandwidth = .
2. List the assumptions made in negative feedback circuit.
The current drawn by either of the input terminals (non-inverting and
inverting) is negligible.
The differential input voltage Vd between non-inverting and inverting
terminals is essentially zero.
3. What is an op-amp?
An op-amp is a direct coupled, high gain amplifier consisting of one or
more differential amplifiers, followed by a level translator and an output stage.
An operational amplifier is available as a single integrated circuit package. It is
a versatile device that can be used to amplify dc as well as ac input signals.
4. Explain the meaning of open loop and closed loop operation of op-amp.
In open loop, the input signals are applied at non-inverting and inverting
input terminals. Since the gain is infinite, the output of op-amp is at positive or
negative saturation level. It does not operate linear in this mode.
In closed loop, negative feedback is provided and the input signals are
applied either to inverting or non-inverting terminal. The output in this case is
not driven into saturation level. In this mode it operates linearly.
5. What is a voltage follower?
The output voltage is equal to input voltage both in magnitude and phase.
In other words, the output voltage follows the input voltage exactly.
RESULT:
Thus the Slew rate of an operational amplifier was verified and operation of
inverting and non-inverting amplifier was studied.
71
CIRCUIT DIAGRAM:
INTEGRATOR
Rf
Cf
R1
VOS1
1
6
OUT
3
+ 7
1 Vpp
OS2
V+
U2
Rcomp
DIFFERENTIATOR:
Rf
Cf
R1
C1
4
-
VOS1
OUT
3
1 Vpp
+ 7
Rcomp
72
OS2
V+
1
6
5
LM741
U2
Vout
Exp. No:
Date
:
APPLICATIONS OF OP-AMP
AIM:
To design and analyze the integrator, Differentiator, Adder and Comparator
circuits.
S.NO
1.
2.
3.
4.
5.
6.
7.
DESIGN:
APPARATUS NAME
Signal generator
CRO
Op- amp
Resistors
Regulated power supply
Capacitor
Breadboard
RANGE
1MHz
20MHz
LM741
10K, 5K
(0-30) Volts
0.1F
QUANTITY
2
1
1
2,1
3
1
INTEGRATOR:
The output voltage is given by
Vo (t )
1
R1C F
in
(t )dt Vo (o)
To find Cf:
The gain value is given by
The corner frequency is

Choose,
R1
------- (1)
1 j R f C f
Rf
fa = 2R C ---------------- (2)
f
f
fa
= 100Hz and Rf = 10K , sub in (2) find Cf
73
COMPARATOR:
4
4
R= 10K
2
-V
6
10K
Vref
Vo
+V
Vi
ADDER:
V1
V2
V3
Rf = 10K
R1= 10K
R2= 10K
R3 = 10K
4
4-V
6
3
7
Rcomp
10K
74
+V
Vo
To find R1 :
Let Gain (A) = 1 and substitute all remaining values in equation (1), then
find the value of R1.
Rcomp = R1Rf
Time constant:
T = R f Cf
DIFFERENTIATOR:
Vo RF C1
The gain value is given by
dvin
dt
jR f C1
(1 jR1C1 ) 2
------------------- (1)
The lower corner frequency is
fa = 2R C ------------------- (2)
f
1
The upper corner frequency is
fb
1
2R1C 1
------------------- (3)
Always assume fa < fb < fc and T Rf C1 Where T is time constant.

Rcomp = R1Rf
DESIGN PROCEDURE:
1. Choose fa equal to the highest frequency of the input signal. i.e. fa = 100Hz
2. Choose C1 to be less than 1 micro Farad and calculate the value of Rf.
Choose C = 1micro Farad and from equation (2) and Calculate Rf.
3. Choose fb = 10fa which ensures that fa < fb. Now find R1 using eq.(3)
Differentiator
4. To find Cf , use
RfCf = R1C1 .
Input
Voltage
(Volts)
Time
(msec)
MODEL GRAPH:
Output
Voltage
(Volts)
75
Time
(msec)
Integrator
Input
Voltage
(Volts)
Time
(msec)
Output
Voltage
(Volts)
Time
(msec)
ADDER:
The nodal equation by KCL at node A is
76
V1 V2 V3 V0
0
R1 R2 R3 R f
Rf
Rf
Rf
V0
V1
V2
V3
R2
R3
R1
or,
Where R1 = R2 = R3 = Rf then
V0= - [V1+V2 + V3]
Assume Rf =10K
Rf/R1 = 1
R1 = 10K
Rf/R2 = 1
R2 = 10K
Rf/R3 = 1 ,
R3 = 10K
Rcomp = R1R2R3Rf
THEORY:
Integrator:
In an integrator circuit, the output voltage waveform is the integral of the input
voltage waveform. Such a circuit is obtained by using a basic inverting amplifier
configuration if the feedback resistor Rf is replaced by a capacitor Cf.
Vo (t )
1
R1C F
in
(t )dt Vo (o)
Where C is the integration constant and is proportional to the value of the output voltage
Vo at time t = 0 seconds. The above equation indicates that the output voltage is directly
Comparator
proportional to the negative integral of the input voltage and inversely proportional to the
time constantInput
R1Cf. For eg.if the input is a sine wave, the output will be a cosine wave.
voltage
When input (Volts)

voltage is zero, the integrator works as an open loop amplifier. This is
because the capacitor CF acts as an open circuit to the input offset voltage V io. In other
Time
words, the input offset voltage Vio and the part of the input current charging capacitor CF
(msec)
produces error voltage at the output of the integrator. In practical
Output
Voltage
(Volts)
77
Time
(msec)
Offset Null
No Connection
Inverting input
V+
Output
Offset Null
V-
IC741
circuits to reduce the error voltage at the output, a resistor R F is connected across the
feedback capacitor CF. Thus RF limits the low frequency gain and hence minimizes the
variations in the output voltage. Both the stability and the low frequency roll off
problems can be corrected by the addition of a resistor RF.
Differentiator:
78
In a differentiator circuit, the output waveform is the derivative of the input

waveform. The differentiator may be constructed from a basic inverting amplifier if an
input resistor R1 is replaced by a capacitor C1.
Vo R F C1
dvin
dt
Thus the output voltage Vo is equal to RFC1 times the negative instantaneous rate of
change of the input voltage Vin with time. The differentiator performs the reverse of
integrators function, a cosine wave input will produce a sine wave output or a triangular
input will produce a square wave output. The gain of the circuit (R F/Xc1) increases with
increase in frequency at a rate of 20 dB/decade. This makes the circuit unstable and break
into oscillations. However the input impedance XC1 decreases with increase in frequency,
which makes the circuit very susceptible to high frequency noise. Both the stability and
the high frequency noise problems can be corrected by the addition of two components
R1 and CF. These components R1C1 and RFCF help to reduce significantly the effect of
high frequency input, amplifier noise and offsets.
Inverting summing Amplifier:
Operational amplifier may be used to design a circuit whose output is the sum of
several input signals. Such a circuit is called summing amplifier or summer. The
summing amplifier may be inverting or non inverting one Assume that the op-amp is an
ideal one, that is AoL =
and Ri = .Since the input bias current is assumed to be zero,
there is no voltage drop across the resistor Rcomp and hence the non inverting input
terminal is at ground potential. The voltage at node A is zero as the non inverting input
terminal is grounded. The nodal equation by KCL at node A is given by
TABULATION:
79
ADDER:
V1 (volts )
V2(volts)
V3 (volts)
V0 = -(V1+V2+V3)volts
DIFFERENTIATOR AND INTEGRATOR:

Input voltage
(V)
Input Time period
Output voltage
(ms)
(V)
Output Time period

(ms)
COMPARATOR:
Input voltage
(V)
Input Time period
Output voltage
(ms)
(V)
V1 V2 V3 V0
0,
R1 R2 R3 R f
80
Output Time period

(ms)
Rf
Rf
Rf
V0
V1
V2
V3
R2
R3
R1
Thus the output is an inverted, weighted sum of the inputs. In the special
case, when
R1 = R2 = R3 = Rf ,we have
V0= - [V1+V2 + V3]
Comparator:
A comparator is a circuit which compares a signal voltage applied at one input of
an op-amp with a known reference voltage at the other input. It is basically an open loop
op-amp with output Vsat (=Vcc).Comparators are used in circuits such as digital
interfacing, Schmitt triggers, voltage level detectors. A fixed reference voltage Vref is
applied to the (-) input and the time varying signal voltage V in is applied to the (+) input.
Because of this arrangement, the circuit is called non-inverting comparator. The output
voltage is at Vsat for Vi less than Vref because the voltage at the (-) input is higher than at
the (+) input. And Vo goes to +Vsat for Vi greater than Vref. Thus V0 changes from one
saturation level to another.
PROCEDURE:
DIFFERENTIATOR AND INTEGRATOR:
2. For the integrator circuit, the square wave is given as the input waveform and the
triangular wave is taken as the output using CRO.
3. For the differentiator circuit, square wave is given as input and spike wave is
taken as output.
4. Measure the input and output voltage and enter it into tabular column.
5. After completing the experiments, reduce the supply to zero potential and
disconnect the circuit diagram.
ADDER AND COMPARATOR:
1.
2.
3.
4.
5.
Connect the circuit as per the circuit diagram.

For comparator circuit, set the reference voltage Vref = 0.5V.
Adjust the signal generator so that Vi = 2V PP sine wave at 1 KHz.
Using a CRO observe the input and output waveform simultaneously. Plot the
output waveform.
Set the reference voltage Vref = -0.5V and repeat the above steps. Plot the output
waveform.
81
6.
7.
For the adder circuit, set the voltages as 1V, 2V and 3V at V1,V2,V3.
Note down the readings and enter in the tabulation.For an inverting summing
amplifier the output will be the inverted sum of these input signals.
82
1. What is integrator?
A circuit in which the output voltage waveform is the integral of the input
waveform is the integrator or integration amplifier.
Vo
1
R1C F
in
dt c
2. Write the application of integrator and differentiator?

Integrators are most commonly used in analog computers, analog to
digital
converters, various signal wave shaping circuits. Differentiators are used in
wave
shaping circuits to detect high frequency components in an input signal and
also as a rate of change detector in FM demodulators.
3. What is differentiator?
The circuit performs the mathematical operation of differentiation; that is the
output waveform is the derivative of input waveform.
dv
Vo R F C1 in
dt
4. Why integrators are preferred over differentiators in analog computers?
The gain of a differentiator increases linearly with frequency and it tends to
amplify a noise, drift which may result in spurious oscillations. The gain of the
integrators decreases with increasing frequency and hence signal to noise ratio of
integrator is higher than differentiator. So integrators are preferred over
differentiators in analog computers.
5. What do you mean by comparator?
It is a circuit which compares a signal voltage on one input of an op-amp with
a known voltage called the reference voltage on the other input.
6. Write the output voltage expression for inverting summing amplifier.
Vo = - [V1+V2 +V3+..+Vn]
RESULT:
Thus the Differentiator, Integrator, Adder and Comparator circuits were designed
and analyzed.
CIRCUIT DIAGRAM:
83
MONOSTABLE MULTIVIBRATOR:
+Vcc
8
3
Vout
7
555
C = 0.01F
2
Trigger input
ASTABLE MULTIVIBRATOR:
+VCC
RA
7
RB
Vo
555
C = 0.01F
Exp. No:
Date
:
ASTABLE AND MONOSTABLE MULTIVIBRATOR

84
USING NE555 TIMER

AIM:
To design, construct and test the Astable Multivibrator and Monostable
Multivibrator using NE 555 timer
S.NO
1.
2.
3.
4.
5.
6.
APPARATUS NAME
Signal generator
CRO
Resistors
Timer IC
Capacitors
RANGE
(0-30) Volts
1MHz
20MHz
10k
NE555
0.1F,0.01F
DESIGN:
Astable Multivibrator:
Let
Vcc = 5V
Vc
= Vcc
T= 0.69 (RA+2RB) C
f
1
1.45
T R A 2 RB C
Let RA = RB = R
T = 2.1RC
Assume R = 10K and C = 0.1F for T = 2.1ms
Also Ton = 0.69(RA+RB) C
Toff = 0.69RBC
MODEL GRAPH:
MONOSTABLE MULTIVIBRATOR
Output voltage
85
QUANTITY
1
1
1
2
1
1
T (ms)
1/3
Vcc
2/3
Vcc
Output voltage across capacitor
Tlow
Thigh
Ground
Vcc
Trigger
Discharge
555
Output
Threshold
Reset
Control
Voltage
Monostable Multivibrator:
T = 1.1RC
Assume R = 10K and C = 0.1F for T = 1.1ms
86
THEORY:
IC 555:
The astable and monostable circuit are commonly available in monolithic ICs,
and IC timers. The timer 555 is one example which has gained wide acceptance in terms
of cost and versatility. It was first introduced by Signetics Corporation as SE/NE 555.
Some important applications of this device are monostable and astable multivibrators,
dc-dc converters, digital logic probes, waveform generators, analog frequency meters and
tachometers, temperature measurement and control, infrared transmitters, burglar and
toxic gas, alarms, voltage regulators, etc.
The IC 555 timer is a 8-pin IC that can be connected to external components for
either astable or monostable operation. The 555 timer will work with any supply voltage
between 4.5V and 10V.In the internal structure of the 555 timer there are one flip flop
and two op-amps. The non-inverting input of upper op-amp is called as threshold voltage
and inverting input is called as control voltage.Multivibrators is group of regenerative
circuits. They are widely used in timing applications.Multivibrators are classified as
(1) Bistable multivibrators
(2) Monostable Multivibrators
(3) Astable Multivibrators
ASTABLE MULTIVIBRATORS:
Astable circuits are used to generate square waves. It is also known as
free running multivibrator.It has two quasistable states. Thus there is no oscillation
between these two states and no external signals to produce the change in state.
As there is no need of trigger input the second pin is connected to the sixth
pin. Comparing with monostable operation, the timing resistor is now split into two
sections RA and RB. Pin 7 is connected to the junction of R A and RB. When the power
supply Vcc is connected, the external timing capacitor C charges towards Vcc with a time
constant (RA+RB) C. When the threshold voltage exceeds Vcc, the upper op-amp has a
ASTABLE MULTIVIBRATOR:
87
o/p
voltage
Output voltage
1/3
Vcc
2/3
Vcc
T(ms)
Tlow
Thigh
high input and this sets the flip flop allowing the capacitor discharging through R B.
Therefore the discharge time constant is R BC. When the capacitor drops below +Vcc/3,
the lower amplifier has higher input and this resets the flip flop. The capacitor C is thus
88
periodically charged and discharged between (2/3) Vcc and (1/3) Vcc. The total time period
is given by
T = 0.69 (RA+2RB) C.
MONOSTABLE MULTIVIBRATORS:
The 555 timer configured for monostable operation is shown in the figure.
Monostable multivibrator often called a one shot multivibrator is a pulse generating
circuit in which the duration of this pulse is determined by the RC network connected
externally to the 555 timer. In a stable or standby state, the output of the circuit is
approximately zero or a logic-low level. When external trigger pulse is applied output is
forced to go high ( VCC). The time for which output remains high is determined by the
external RC network connected to the timer.At the end of the timing interval, the output
automatically reverts back to its logic-low stable state. The output stays low until trigger
pulse is again applied. Then the cycle repeats. The monostable circuit has only one stable
state (output low) hence the name monostable. The time during which the output remains
high is given by
PROCEDURE:
1. Get the required components and check the condition of them.
3. Switch on the power supply and look at the output with CRO.
4. Measure the width and time period of the output waveform.
5. Look at the voltage across the capacitor, an exponentially rising and falling wave
between5V and 10V is noted.
6. After completing the experiments, reduce the supply to zero potential and
disconnect the circuit diagram.
TABULATION:
89
MONOSTABLE MULTIVIBRATOR:
Parameter
Amplitude(V)
Time period(ms)
Output voltage
Capacitor voltage
ASTABLE MULTIVIBRATOR :
Parameter
Amplitude(V)
Time period(ms)
Output voltage
Capacitor voltage
1. What are the applications of 555 timers?
The applications of 555 timers include oscillator, pulse generator, burglar
alarm,
and traffic light control
2. Define duty cycle.
90
The duty cycle D of a circuit is defined as the ratio of ON time to the total
time period T= (tON +toff).
3. What is the function of 555 Timer?
The 555 timer is a highly stable device for generating accurate time delay or
oscillation. A single 555 timer can provide time delay ranging from microseconds
to hours
.
4. What are the modes of operation of a timer?
The modes of operation of timers are monostable and astable mode.
5. What are the applications of 555 timer in monostable mode?
The applications of 555 timer in Monostable mode are
(i)
Missing Pulse Detector
(ii)
Linear Ramp Generator
(iii)
Frequency Divider
(iv)
Pulse Width Modulation
6. What are the applications of 555 timer in Astable mode?
The applications of 555 timer in Astable mode are
(i) Pulse-Position Modulator
(ii) FSK Generator
(iii) Schmitt Trigger
Preparation
Performance
Record
Total
30
30
40
100
RESULT:
Thus the astable and monostable multivibrators was designed and tested using
NE555 timer.
+Vcc
10k
CIRCUIT DIAGRAM:
20k
10k
c
20k
D3
10k
20k
IC741
20k
3
100k
D2
Rcomp
D1
20k
91
-VR = 5V
4
-Vcc
Vo
MODEL GRAPH:
Analog output
Digital Input
.
Exp. No:
Date
:
R-2R LADDER TYPE D/A CONVERTER.

AIM:
To construct a three bit R-2R ladder type D/A converter and to plot the transfer
characteristics.
92
S.
Components
No
1. Op-amp
2. Resistors
3.
4.
Breadboard
Range
Quantity
LM741
10K, 20K,
100K
1
1,5,1
(0-30V)
1
2
PROCEDURE:
1. Make the connections as shown in the circuit diagram.
2. With all inputs (d0 to d2) shorted to ground, check whether any offset voltage
at the input of the op-amp.
3. Measure the output voltage for all binary inputs (000 to 111) states and plot a
graph of binary inputs Vs output voltage.
THEORY:
In R-2R ladder type DAC only two values of resistors are required. It is well
suited for integrated realization. The typical values of R range from 2.5K to 10K. The
binary inputs are simulated by switches D 1 through D3 and the output is proportional to
the binary inputs. Binary inputs can be in either high (+5) or low (0V) state. Assume that
the most significant bit which is connected to +5V and other switches are connected to
ground. This switch position corresponds to binary word to 100.The voltage at node c can
be easily calculated by the set procedure of network analysis as (-V R/4).The output
voltage Vo = (VR/2).The great advantage of the D/A converter is that it requires only two
sets of precision resistance values and number of bits can be expanded by adding more
sections of same R and 2R values. As the number of binary inputs is increased beyond
four, the circuits get complex and their accuracy degenerates.
TABULAR COLUMN:
INPUTS
D1
D2
OUTPUT
VOLTAGE
D3
93
Offset Null
No Connection
Inverting input
V+
Output
Offset Null
V-
IC741
1. What are the types of digital to analog converters?
The types of DAC are
Weighted resistor DAC
R-2R ladder DAC
Inverted R-2R ladder DAC.
2. Why an inverted R-2R ladder network DAC is better than R-2R ladder
DAC.
94
In R-2R ladder type DAC current flowing through the resistors changes as
The input data changes .More power dissipation causes heating which in turn
Creates nonlinearity in DAC.
3. Define resolution of converter
It is the smallest change in voltage which may be produced at the output of
the converter.
Resolution (in volts) = VFS / (2n-1) = 1 LSB increment.
4. What is DAC?
A digital to analog converter is used to convert a digital signal to an analog
signal. Hence the input is an n-bit binary word and combined with a
reference voltage VR to give an analog output signal. The output of DAC
is either a voltage or current.
5. Mention any two differences between weighted resistor DAC and R-2R
DAC.
S.No Weighted Resistor DAC
1.
Requires a wide range of
resistor values
2.
Higher values of resistor
required for the LSB.
R-2R DAC
Requires only two values of
resistors.
No such restriction as only two
resistor values are used what ever
may be the inputs.
RESULT:
Thus a three bit R-2R ladder type Digital to analog converter is
constructed and the transfer characteristics were drawn.
FREQUENCY MULTIPLIER:
95
Input
Signal
Phase
Comparator
Low Pass
Filter
Amplifier
N
Network
Voltage to Frequency characteristics of NE/SE 566
+Vcc
1.5 K
RT
0.001F
8
3
Vc
NE/
SE 566
1K
7
CT
96
4
1
111
111
11
VCO
Exp. No:
Date
:
(a) VOLTAGE TO FREQUENCY CHARACTERISTICS OF NE/SE 566 IC

(b) FREQUENCY MULTIPLIER USING NE/SE 565 PLL IC.
AIM:
To design, construct and test the frequency multiplier using NE565 Phase
locked loop and to test the voltage to frequency characteristics of NE/SE 566 VCO.
S.No Components name
1
NE/SE565, IC7490,NE/SE 566
2
Resistance
3
Capacitance
4
5.
6.
7.
8.
Range
2K,10K,1.5K
10F
0.01F
0.001F
Decade Resistance box

DC Power Supply
Signal Generator
CRO
Bread board
(0-30)V
1MHZ
20MHZ
DESIGN:
(a) Frequency Multiplier
Output Frequency fo =Nfin

Free Running frequency of VCO fo = (0.25/RTCT)Hz
Lock Range fL = 7.8fo/V
1
fL
Capture Range f
c
2 3.6 *103 C
(b) Voltage to frequency characteristics of NE/SE 566 IC

fo
2 V Vc
CT RT (V )
where
3
(v ) vc (v)
4
97
quantity
1,1,1
1
1
1
1
1
1
1
1
1
CIRCUIT DIAGRAM:
+V = 10V
C
10F
0.001F
R = 2K
C1
10
2
NE/SE 565
fin
fout
3
Vcc=+5V
9
5
CT
11
0.01F
-V = -10V
7490(/5)
2 3 6 7 10
1010
MODEL GRAPH:
fin
1 Cycle
Time
fout
5 Cycle
Time
98
THEORY:
Frequency Multiplier:
The frequency multiplier using the 565 PLL is shown in the block diagram. As shown in
the diagram, the frequency divider is inserted between the VCO and the phase
comparator. Since the output of the divider is locked to the input frequency f in, the VCO
is actually running at a multiple of the input frequency. The desired amount of
multiplication can be obtained by selecting a proper divide by N network, where N is an
integer. For example, to obtain the output frequency fout = 5fn, a divide-by-N = 5 network
is needed. The circuit shows this function performed by a 7490 (4-bit binary counter)
configured as a divide-by-5 circuit.
To verify the operation of the circuit, one must determine the input frequency
range and then adjust the free-running frequency fout of the VCO by means of R1 and C1
so that the output frequency of the 7490 divider is midway within the predetermined
input frequency range. The output of the VCO now should be 5f in. In the circuit, the
output frequency fout can be adjusted from 1.5 kHz to 15 kHz by varying potentiometer
R1. This means that the input frequency fin range has to be within 300Hz to 3 kHz. In
addition, the input waveform can be either sine or square and may be applied to input
pins 2 or 3. The above input output waveform represents f out = 5fin. Even though supply
voltages of 10V are used, the NE565 can be operated on 5V supply voltages instead. A
small capacitor, typically 1000pf, is corrected between pins 7 and 8 to eliminate possible
oscillations. Also capacitor C2 should be large enough to stabilize the VCO frequency.
Voltage to frequency Characteristics of VCO:
There are applications such as frequency modulation, tone generators, and
frequency shift keying, where the frequency needs to be controlled by means of an input
voltage called control voltage. This function is achieved in the voltage controlled
oscillator. A common type of VCO available in IC form is signetics NE/SE 566.A timing
capacitor CT is linearly charged or discharged by a constant current source/sink. The
amount of current can be controlled by changing the voltage V c applied at the modulating
99
input (pin5) or by changing the timing resistor RT external to the chip. The voltage at pin
6 is held at the same voltage as pin 5. Thus, if the modulating voltage at pin 5 is
Pin Diagram:
Ground 1
NC
Sq.wave
3
output
Triangular 4
wave output
NE/SE 566
VCO
+Vcc
CT
RT
5 Modulation
Input
-Vcc
14
NC
Input
13
NC
Input
12
NC
11
NC
VCO output 4
NE / SE 565
10
Reference 6
Output
Demodulated 7
Output
9
8
100
+Vcc
External capacitor
for VCO
External resistor
for VCO
increased, the voltage at pin 6 also increases, resulting in less voltage across RT and there
by decreasing the charging current. A small capacitor of 0.001F should be connected
Frequency Multiplier:
between pins 5 and 6 to eliminate possible oscillations in the control current source. The
frequency of oscillations is determined by an external resistor RT ,capacitor CT, and the
voltage applied to the control terminal 5.
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
Make Connections as per the circuit diagram

Set the input voltage as 1VPP Square wave with frequency of 1KHZ to pin 2.
Measure the output frequency
Vary the input frequency
Change the RT Value till the PLL is locked.
Note down the RT Value and measure the output frequency
Plot the waveforms of input and output signal.
For voltage to frequency characteristics the modulating input dc voltage is given
to corresponding pin and the waveforms are noted.
101
(a) Voltage to frequency characteristics of NE/SE 566

TABULATION:
Square wave form
Amplitude
Time Period
Triangular Wave
Amplitude
Time Period
(b) Frequency Multiplier:

TABULATION:
Input Frequency
(KHZ)
Output Frequency
(KHZ)
Value of external resistance

Theoritical
Practical
102
1. List the basic building blocks of a PLL (Phase locked loop)
A phase locked loop consists of a phase detector/comparator, low pass filter, error
amplifier, voltage controlled oscillator.
2. Give the uses of low pass filter used in PLL and state its types.
The low pass filter may be active or passive type. The LPF not only removes the
high frequency components and noise, but also controls the dynamic characteristics of
the PLL such as capture range, lock range, bandwidth and transient response.
3. List the applications of PLL.
The PLLs are used as frequency multiplier, divider, AM detection, FM
demodulation and FSK demodulator
4. Write the expression for voltage to frequency conversion factor.
The voltage to frequency conversion factor kv is defined as
kv
f o
v c
Where vc is the modulation voltage required to produce the frequency shift fo for a
VCO.
5. What is voltage controlled oscillator?
The voltage controlled oscillator generates an output frequency that is directly
proportional to input voltage. These are also called as voltage to frequency converters.
RESULT:
Thus the Frequency Multiplier using NE/SE 565 and Voltage to frequency
characteristics using NE/SE566 was designed and tested.
103
104

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Linear and Digital Integrated Circuits Lab

EE6311 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY L T P C

Department of Electrical and Electronics Engg

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