Debugger 166cbc

XC2000/XC16x/C166CBC Debugger
TRACE32 Online Help

TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................
ICD In-Circuit Debugger ................................................................................................................
Processor Architecture Manuals ..............................................................................................
C166 Family .............................................................................................................................
XC2000/XC16x/C166CBC Debugger ...................................................................................
General Note ......................................................................................................................
ICD/AICD
Brief Overview of Documents for New Users .................................................................
Warning ..............................................................................................................................
Monitor Routine .................................................................................................................
Quick Start .........................................................................................................................
Quick Start for Tracing with MCDS On-chip Trace
11
1. Start and Stop Tracing
11
2. Specify Trace Source and Recording Options
11
11
4. View the Results
11
Memory Classes ................................................................................................................

CPU specific SYStem Commands ...................................................................................
SYStem.BdmClock
13
Define JTAG frequency
13
Select the CPU
13
Run-time memory access (intrusive)
13
SYStem.CPU
SYStem.CpuAccess
12
SYStem.JtagClock
Define the JTAG frequency
15
Real-time memory access (non-intrusive)
15
SYStem.Mode
Establish the communication with the CPU
16
SYStem.LOCK
Lock and tristate the debug port
17
SYStem.MemAccess
SYStem.CONFIG
Configure debugger according to target topology
18
Daisy-chain Example
20
TapStates
21
SYStem.CONFIG.CORE
Assign core to TRACE32 instance
22
SYStem.CONFIG.DAP
Define mapping for DAP pins
23
SYStem.CONFIG.DAP.BreakPIN
Define mapping of break pins
23
Enable DAP mode on PORST
23
SYStem.CONFIG.DAP.DAPENable
1989-2016 Lauterbach GmbH
SYStem.CONFIG.DAP.USERn
Configure and set USER pins
SYStem.CONFIG.DEBUGPORTTYPE
Set debug cable interface mode
24
Run-time memory access for all windows
25
Periodically activate/deactivate JTAG connection
25
Disable interrupts while single stepping
25
SYStem.Option DUALPORT
SYStem.Option IDLEFIX
24
SYStem.Option IMASKASM
SYStem.Option IMASKHLL
SYStem.Option MonBase
SYStem.Option PERSTOP
SYStem.Option PERSTOPFIX
Disable interrupts while HLL single stepping
25
Define start address of debug monitor
26
Enable global peripheral suspend signal
26
Break CPU via ONCHIP break register
26
SYStem.Option BRKOUT
SYStem.Option WATCHDOG
SYStem.Option TRACEENABLE
SYStem.Option DebugLevel
SYStem.Option BootModeIndex
Activates BRKOUT signal
27
Disable or serve watchdog
27
Disable traceport
27
Debug level
28
BootModeIndex
29
Flush instruction cache
30
Debug in IDLE state
30
Delay between PORST and JTAG shifts
30
MCDS Onchip Trace ..........................................................................................................
31
SYStem.Option ICFLUSH
SYStem.Option IDLEDEBUG
SYStem.Option WaitReset
MCDS Onchip Trace Features
31
Supported Features
31
Trace Control
31
Simple Trace Control
31
Examples
32
BenchMarkCounter ...........................................................................................................
BMC.CNTx.EVENT
35
Configure the performance monitor
35
Useful Features .................................................................................................................
36
Breakpoints ........................................................................................................................
37
Software Breakpoints on Instructions
37
On-chip Breakpoints
37
On-chip Breakpoints in FLASH/ROM
37
Example for Breakpoints
38
TrOnchip Commands ........................................................................................................

TrOnchip.view
TrOnchip.CONVert
40
Display on-chip trigger window
40
Adjust range breakpoint in on-chip resource
40
TrOnchip.RESet
Set on-chip trigger to default state
40
Set filter for the trace
41
TrOnchip.TOFF
Switch the sampling to the trace to OFF
41
TrOnchip.TON
Switch the sampling to the trace to ON
41
TrOnchip.TEnable
TrOnchip.TTrigger
TrOnchip.VarCONVert
Set a trigger for the trace
41
Adjust complex breakpoint in on-chip resource
42
Define address selector
42
Define access type
42
TrOnchip.Address
TrOnchip.CYcle
TrOnchip.Data
Define data selector
TrOnchip.NoMatch
43
Define match or nomatch comparison
43
Define TASKID comparison
43
Connectors ........................................................................................................................
44
TrOnchip.TaskID
JTAG Connector
44
DAP Connector
45
Troubleshooting ................................................................................................................
SYStem.Up Errors
46
46
FAQ .....................................................................................................................................
47
Technical Data ...................................................................................................................
50
Operation Voltage
50
Support ...............................................................................................................................
51
Available Tools
51
Realtime Operation Systems
55
3rd Party Tool Integrations
55
Products .............................................................................................................................
Product Information
57
57
Version 24-May-2016
B::d.l
addr/line
P:20021A
P:20021C
P:200220
P:200224
P:200228
P:20022C
P:20022E
P:200232
P:200236
P:20023A
B::r
N
_
C
_
V
_
Z
_
E
_
MIP _
USR _
IEN _
ILV 0
Tsk
code
CC00
E6000000
E6010100
E6020200
E6030300
CC00
E60AC0FB
E60BFEFB
E609FEFB
E60800FC
label
mnemonic
nop
mov
dpp0,#0
mov
dpp1,#1
mov
dpp2,#2
mov
dpp3,#3
nop
mov
stkov,#0FBC0
mov
stkun,#0FBFE
mov
sp,#0FBFE
mov
cp,#0FC00
comment
B::per
R0
0
R1
0
R2
0
R3
0
R4
0
R5
0
R6
0
R7
0
PSW
0
SOV 0FA00
R8
0
R9
0
R10
0
R11
0
R12
0
R13
0
R14
0
R15
0
CP 0FC00
SUN 0FC00
DPP0
0
DPP1
1
DPP2
2
DPP3
3
SP 0FC00
MDH
0
MDL
0
MDC
0
CSP
20
IP
220
System Configuration
SYSCON
1484 STKSZ 256
ROMS1
WRCFG wrl+wrh CSC
Bus Configuration
BUSC0
06BF RDYEN0 dis BUSACT
BTYP w/nomux MTTC
BUSC1
04BF CSWEN1 off CSREN1
BTYP w/nomux MTTC
General Note
This documentation describes the processor specific settings and features for the debugger ICD-166CBC
and the debugger ICD-166SV2. (You can find the description of ROM Monitors for 80C166 family at C166
Monitor (monitor_c166.pdf)
ICD-166CBC supports processors based on the C166CBC and C166SV1 core, like PMB2850 (E-GOLD),
PMB6850 (E-GOLD+), PMB7850 (E-GOLD+V3), SDA6000 (M2), INKA, C165UTAH, C161U, PEF20580
(DOLCE),
ICD-166SV2 supports processors based on the C166SV2 core, like XC161CJ, XC164CS,
ICD/AICD
In the following we use the short form ICD (In-Circuit Debugger) for debug systems running on the debug
box Debug Interface and AICD (Active In-Circuit Debugger) for debug systems running on the debug box
Power Debug Interface, Power Debug Ethernet and Power Trace.
For installation and to make you familiar with the main features of the debugger see the manual Quick
Installation and Tutorial.
Brief Overview of Documents for New Users

Architecture-independent information:
Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
T32Start (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances

for different configurations of the debugger. T32Start is only available for Windows.
General Commands (general_ref_<x>.pdf): Alphabetic list of debug commands.
Architecture-specific information:
Processor Architecture Manuals: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
-
Choose Help menu > Processor Architecture Manual.
RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware
debugging.
General Note
Warning
NOTE:
To prevent debugger and target from damage it is recommended to connect or

disconnect the debug cable only while the target power is OFF.
Recommendation for the software start:
1.
Disconnect the debug cable from the target while the target power is
off.
2.
Connect the host system, the TRACE32 hardware and the debug
cable.
3.
Power ON the TRACE32 hardware.
4.
Start the TRACE32 software to load the debugger firmware.
5.
Connect the debug cable to the target.
6.
Switch the target power ON.
7.
Configure your debugger e.g. via a start-up script.
Power down:
1.
Switch off the target power.
2.
Disconnect the debug cable from the target.
3.
Close the TRACE32 software.
4.
Power OFF the TRACE32 hardware.
Warning
Monitor Routine
The monitor routine is required for ICD-166CBC, only. There is no monitor routine when using ICD166SV2.
The following resources are used by the debugger:
Stack Memory: 8 bytes of memory on the current stack.
Program Memory: 32 bytes of program memory for a exception routine.
A TRAP vector (4 bytes) at 20H.
The exception routine will be loaded automatically by the debugger on a SYStem.Up at the address which is
selectable by the SYStem.Option MONBASE command. Also the jump command will be written
automatically to 20H.
You must do all settings (e.g. BUSCON register) to make write access to these locations possible. If there is
ROM, you must place the exception routine and trap vector in the ROM yourself and you must inform the
debugger by using the SYStem.Option MONBASE command about the location. Exception: see
SYStem.MODE Prepare.
The command sequence of the exception routine is depending on the option SYStem.Option
WATCHDOG.
WATCHDOG = ON:
push r0
bset psw.0x6
loop:srvwdt
jb psw.0x6,loop
pop r0
push dpp3
mov dpp3,#0x3
atomic #4
mov dpp3:0x30fc,zeros
bclr tfr.0xc
pop dpp3
reti
The binary code is:

0xEC,
0x8A,
0xE6,
0xFC,
0xF0,
0x88,
0x03,
0xF0,
0x6F,
0xFC,
0x03,
0xCE,
0x88,
0x60,
0x00,
0xD6,
0xA7,
0xFC,
0xD1,
0xFC,
0x58,
0xF0,
0x30,
0x03,
0xA7,
0xEC,
0xF6,
0xFB,
0xA7,
0x03,
0x8E,
0x88
Monitor Routine
WATCHDOG = OFF:
push r0
bset psw.0x6
loop: diswdt
jb psw.0x6,loop
pop r0
push dpp3
mov dpp3,#0x3
atomic #4
mov dpp3:0x30fc,zeros
bclr tfr.0xc
pop dpp3
reti
The binary code is:

0xEC,
0x8A,
0xE6,
0xFC,
0xF0,
0x88,
0x03,
0xF0,
0x6F,
0xFC,
0x03,
0xCE,
0x88,
0x60,
0x00,
0xD6,
0xA5,
0xFC,
0xD1,
0xFC,
0x5A,
0xF0,
0x30,
0x03,
0xA5,
0xEC,
0xF6,
0xFB,
0xA5,
0x03,
0x8E,
0x88
At the location 20H a jump to this function has to be placed (if address = 1FFFC0H):
jmps 0x1f,0x0ffc0
The binary code is (if address = 1FFFC0H):

0xfa, 0x1f, 0xc0, 0xff
Monitor Routine
Quick Start
Check if there is a suitable script file for your hardware in /demo/c166/etc/ Read the comments in the
script file.
After finishing the preparations (see Monitor) starting up the debugger is done as follows:
1.
Select the device prompt B: for the ICD Debugger.

b:
If you are working with the PODPC card device b:: is already selected.
2.
Select the CPU type to load the CPU specific settings.

SYStem.CPU PMB2850
If you are working with the PODPC card, the correct CPU family is selected automatically after startup.
3.
Tell the debugger wheres ROM on the target.

MAP.BOnchip 0x100000++0x0fffff
This command is necessary for the use of on-chip breakpoints.

4.
Enter debug mode

SYStem.Up
This command resets the CPU and enters debug mode. After this command is executed it is possible
to access memory and registers.
5.
Load your application program.

Data.LOAD.IEEE PROG166
; IEEE specifies the format, PROG166 is

; the file name
The option of the Data.LOAD command depends on the file format generated by the compiler. For
information on the compiler options refer to the section Compiler. A detailed description of the
Data.LOAD command is given in the General Commands Reference.
Quick Start
The start up can be automated using the programming language PRACTICE. A typical start sequence is
shown below:
b::
; Select the ICD device prompt
WinCLEAR
; Clear all windows
MAP.BOnchip 0x100000++0x0fffff
; Specify wheres ROM
SYStem.cpu PMB2850
; Select the processor type
SYStem.Up
; Reset the target and enter debug

; mode
Data.LOAD.IEEE PROG166
; Load the application
Register.Set PC main
; Set the PC to function main
Data.List
; Open disassembly window *)
Register /SpotLight
; Open register window *)
Frame.view /Locals /Caller
; Open the stack frame with

; local variables *)
Var.Watch %Spotlight flags ast
; Open watch window for variables *)
PER.view
; Open window with peripheral register

; *)
Break.Set sieve
; Set breakpoint to function sieve
Break.Set 0x1000 /Program
; Set software breakpoint to address

; 1000 (address 1000 is in RAM)
;
;
;
;
Set on-chip breakpoint to address

101000 (address 101000 is in ROM)
See restrictions in On-chip
Breakpoints.)
*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.
10
Quick Start
Quick Start for Tracing with MCDS On-chip Trace

It is assumed that you are tracing a XC2000ED.

; select XC2000ED CPU
SYStem.CPU XC2000ED
Load your application and prepare for debug.
2. Specify Trace Source and Recording Options

Select the source what should be recorded (e.g. Program Flow and Timestamps). When enabling
Timestamps, the CPU clock has to be added also.
MCDS.SOURCE C166 FlowTrace ON
; enable TriCore program flow

; trace
MCDS.TimeStamp TICKS
; enable Ticks as timestamps
MCDS.CLOCK SYStem 80.0MHz
; configure CPU clock for correct

; timestamp evaluation

Go
; start tracing
Break
; stop tracing
Note that tracing can also be stopped by a breakpoint.
4. View the Results

; view recorded trace data
Onchip.List
11
Quick Start
Memory Classes
The following memory classes are available:
Memory Class
Description
Program
Data
Since C166CBC has von Neumann architecture there is no difference in the use of these memory classes.
If you use the memory classes E, EP or ED the memory is accessed even if the target CPU is running.
There is no difference in the use of E, EP and ED. The JTAG debugger use the Debug Peripheral Event
Controller (DPEC) to access memory. This acts like a cycle stealing DMA. If a Data.Dump window is opened
by using one of these memory classes, the window contents will also be refreshed while the processor is
running (see also SYStem.Option DUALPORT). Please note that in this case the program will not be
executed at full speed.
12
Memory Classes
CPU specific SYStem Commands
SYStem.BdmClock
Define JTAG frequency
Obsolete command syntax. It has the same effect as SYStem.JtagClock. Use SYStem.JtagClock instead.
SYStem.CPU
Select the CPU
Format:
SYStem.CPU <cpu>
<cpu>:
PMB2850 | PMB6850 | PMB7850 | PEF20580 | SDA6000 | C165UTAH | INKA

| (ICD-166CBC)
XC161CJ, ,XC2287, XE167F, XC2000ED, (ICD-166SV2)
Default: PMB2850 (ICD-166CBC), C166SV2 (ICD-166SV2)

Selects the processor type.
SYStem.CpuAccess
Format:
Run-time memory access (intrusive)
SYStem.CpuAccess Enable | Denied | Nonstop
Default: Denied.
Enable
Allow intrusive run-time memory access.

In order to perform a memory read or write while the CPU is executing the
program the debugger stops the program execution shortly. Each short stop
takes 1 100 ms depending on the speed of the debug interface and on the
number of the read/write accesses required.
A red S in the state line of the TRACE32 screen indicates this intrusive behavior
of the debugger.
13
Denied
Lock intrusive run-time memory access.
Nonstop
Lock all features of the debugger, that affect the run-time behavior.
Nonstop reduces the functionality of the debugger to:
run-time access to memory and variables
trace display
The debugger inhibits the following:
to stop the program execution
all features of the debugger that are intrusive (e.g. action Spot for breakpoints, performance analysis via StopAndGo mode, conditional breakpoints etc.)
14
SYStem.JtagClock
Define the JTAG frequency
Format:
SYStem.JtagClock <rate>
<rate>:
EXT | 1000. 10000000. (ICD)

10000. 50000000. (AICD)
Default 5 MHz (ICD), 10 MHz (AICD).

Selects the frequency for the JTAG clock. This influences the speed of data transmission between target and
debugger.
EXT selects the clock on the pin CPUCLOCK of the JTAG connector as clock source.
Attention: The frequency of the JTAG clock must be lower than the system clock frequency!
Not all values in between the frequency range can be generated by the debugger. The debugger will select
and display the possible value if it can not generate the exact value.
SYStem.MemAccess
Real-time memory access (non-intrusive)
Format:
SYStem.MemAccess CPU | Denied<cpu_specific>

SYStem.ACCESS (deprecated)
CPU
Real-time memory access during program execution to target is enabled.
Denied
Real-time memory access during program execution to target is disabled.
Default: Denied.
15
SYStem.Mode
Establish the communication with the CPU
Format:
SYStem.Mode <mode>
<mode>:
Attach
Down
Go
NoDebug
Prepare
StandBy
Up
Default: Down.
Selects the target operating mode.
Debug mode is active means the communication channel via debug port (JTAG) is established. The
features of the on-chip debug support (OCDS) are enabled and available.
Attach
User program remains running (no reset). Debug mode is active. This mode can
be entered from state NoDebug, if debugging should be enabled without a
target reset. After this command the user program can be stopped with the
break command or if any break condition occurs.
XC2xxx: Attach is only possible if a pull-up resistor is on TRST pin.
Down
The CPU is in reset. Debug mode is not active. Default state and state after fatal
errors.
Go
The user application is running. Debug mode is active. After this command the
program can be stopped with the break command or if any break condition
occurs.
NoDebug
The user application is running. Debug mode is not active. Debug port is
tristate. In this mode the target should behave as if the debugger is not
connected.
Prepare
ICD-166CBC: The CPU is halted. Communication to CPU is established. In this

mode memory access is possible, run control (step, go, break) is not available.
This command can be entered in the command line, only. A valid user program
after power on is not required. See \demo\c166\etc\egold\up.cmm.
ICD-166SV2: Behaves as UP
StandBy
This mode is not supported.
Up
The CPU runs in debug monitor routine (ICD-166CBC) or is in halt mode (ICD166SV2). Debug mode is active. In this mode the user application can be
started and stopped. This is the most typical way to activate debugging.
16
If the mode Go or Attach or Prepare is selected, this mode will be entered, but the control button in the
SYStem window jumps to the mode UP.
The Emulate LED on the debug module is on when the debug mode is active and the CPU is running.
XC2xxx: If the routing of the JTAG pins is changed (Register DBGPRR), only mode Attach and Go are
possible.
SYStem.LOCK
Format:
Lock and tristate the debug port
SYStem.LOCK [ON | OFF]
Default: OFF.
If the system is locked, no access to the debug port will be performed by the debugger. While locked, the
debug connector of the debugger is tristated. The main intention of the lock command is to give debug
access to another tool.
17
SYStem.CONFIG
Configure debugger according to target topology
Format:
SYStem.CONFIG <parameter> <number_or_address>

SYStem.MultiCore <parameter> <number_or_address> (deprecated)
<parameter>
(General):
state
CORE
(JTAG):
DRPRE <bits>
DRPOST <bits>
IRPRE
<bits>
IRPOST <bits>
TAPState <state>
TCKLevel <level>
TriState [ON | OFF]
Slave
[ON | OFF]
<core>
The four parameters IRPRE, IRPOST, DRPRE, DRPOST are required to inform the debugger about the
TAP controller position in the JTAG chain, if there is more than one core in the JTAG chain (e.g. ARM +
DSP). The information is required before the debugger can be activated e.g. by a SYStem.Up. See Daisychain Example.
For some CPU selections (SYStem.CPU) the above setting might be automatically included, since the
required system configuration of these CPUs is known.
TriState has to be used if several debuggers (via separate cables) are connected to a common JTAG port
at the same time in order to ensure that always only one debugger drives the signal lines. TAPState and
TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate
mode. Please note: nTRST must have a pull-up resistor on the target, TCK can have a pull-up or pull-down
resistor, other trigger inputs needs to be kept in inactive state.
Multicore debugging is not supported for the DEBUG INTERFACE (LA-7701).
18
state
Show multicore settings.
CORE
For multicore debugging one TRACE32 GUI has to be started per core.
To bundle several cores in one processor as required by the system this
command has to be used to define core and processor coordinates within
the system topology.
Further information can be found in SYStem.CONFIG.CORE.
DRPRE
(default: 0) <number> of TAPs in the JTAG chain between the core of

interest and the TDO signal of the debugger. If each core in the system
contributes only one TAP to the JTAG chain, DRPRE is the number of
cores between the core of interest and the TDO signal of the debugger.
DRPOST
(default: 0) <number> of TAPs in the JTAG chain between the TDI signal
of the debugger and the core of interest. If each core in the system
contributes only one TAP to the JTAG chain, DRPOST is the number of
cores between the TDI signal of the debugger and the core of interest.
IRPRE
(default: 0) <number> of instruction register bits in the JTAG chain

between the core of interest and the TDO signal of the debugger. This is
the sum of the instruction register length of all TAPs between the core of
interest and the TDO signal of the debugger.
IRPOST
(default: 0) <number> of instruction register bits in the JTAG chain

between the TDI signal and the core of interest. This is the sum of the
instruction register lengths of all TAPs between the TDI signal of the
debugger and the core of interest.
TAPState
(default: 7 = Select-DR-Scan) This is the state of the TAP controller when

the debugger switches to tristate mode. All states of the JTAG TAP
controller are selectable.
TCKLevel
(default: 0) Level of TCK signal when all debuggers are tristated.
TriState
(default: OFF) If several debuggers share the same debug port, this
option is required. The debugger switches to tristate mode after each
debug port access. Then other debuggers can access the port. JTAG:
This option must be used, if the JTAG line of multiple debug boxes are
connected by a JTAG joiner adapter to access a single JTAG chain.
Slave
(default: OFF) If more than one debugger share the same debug port, all
except one must have this option active.
JTAG: Only one debugger - the master - is allowed to control the signals
nTRST and nSRST (nRESET).
19
Daisy-chain Example
TDI
Core A
Core B
Core C
Chip 0
Core D
TDO
Chip 1
Below, configuration for core C.

Instruction register length of
Core A: 3 bit
Core B: 5 bit
Core D: 6 bit
SYStem.CONFIG.IRPRE 6
; IR Core D
SYStem.CONFIG.IRPOST 8
; IR Core A + B
SYStem.CONFIG.DRPRE 1
; DR Core D
SYStem.CONFIG.DRPOST 2
; DR Core A + B
SYStem.CONFIG.CORE 0. 1.
; Target Core C is Core 0 in Chip 1
20
TapStates
0
Exit2-DR
Exit1-DR
Shift-DR
Pause-DR
Select-IR-Scan
Update-DR
Capture-DR
Select-DR-Scan
Exit2-IR
Exit1-IR
10
Shift-IR
11
Pause-IR
12
Run-Test/Idle
13
Update-IR
14
Capture-IR
15
Test-Logic-Reset
21
SYStem.CONFIG.CORE
Assign core to TRACE32 instance
Format:
SYStem.CONFIG.CORE <coreindex> <chipindex>

SYStem.MultiCore.CORE <coreindex> <chipindex> (deprecated)
<chipindex>:
1i
<coreindex>:
1k
Default coreindex: depends on the CPU, usually 1. for generic chips

Default chipindex: derived from CORE= parameter of the configuration file (config.t32). The CORE
parameter is defined according to the start order of the GUI in T32Start with ascending values.
To provide proper interaction between different parts of the debugger the systems topology must be mapped
to the debuggers topology model. The debugger model abstracts chips and sub-cores of these chips. Every
GUI must be connect to one unused core entry in the debugger topology model. Once the SYStem.CPU is
selected a generic chip or none generic chip is created at the default chipindex.
None Generic Chips
None generic chips have a fixed amount of sub-cores with a fixed CPU type.
First all cores have successive chip numbers at their GUIs. Therefore you have to assign the coreindex and
the chipindex for every core. Usually the debugger does not need further information to access cores in
none generic chips, once the setup is correct.
Generic Chips
Generic chips can accommodate an arbitrary amount of sub-cores. The debugger still needs information
how to connect to the individual cores e.g. by setting the JTAG chain coordinates.
Start-up Process
The debug system must not have an invalid state where a GUI is connected to a wrong core type of a none
generic chip, two GUI are connected to the same coordinate or a GUI is not connected to a core. The initial
state of the system is value since every new GUI uses a new chipindex according to its CORE= parameter
of the configuration file (config.t32). If the system contains fewer chips than initially assumed, the chips must
be merged by calling SYStem.CONFIG.CORE.
22
SYStem.CONFIG.DAP
Define mapping for DAP pins
The SYStem.CONFIG.DAP commands are used to map the unused JTAG pins for additional features.
SYStem.CONFIG.DAP.BreakPIN
Format:
Define mapping of break pins
SYStem.CONFIG.DAP.BPIN [PortPort | TdiPort | PortTdo | TdiTdo]
Default: PortONLY.
This command maps a Break Bus to either a GPIO port pin or an unused JTAG pin. It is dependent on the
Interface Mode which Break Bus can be mapped to which pin:
Break Bus 0
Break Bus 1
PortPort
GPIO port pin
GPIO port pin
TdiPort
TDI pin
GPIO port pin
PortTDO
GPIO port pin
TDO pin
TdiTdo
TDI pin
TDO pin
SYStem.CONFIG.DAP.DAPENable
Format:
Enable DAP mode on PORST
SYStem.CONFIG.DAP.DAPEN [TARGET | ON | OFF]
Default: TARGET.
Defines if the the DAP Interface of the CPU is enabled during a Power On Reset (PORST). This command
requires that the debugger DAP Interface is enabled by SYStem.CONFIG.Interface before.
For target boards where a pull-up resistor on nTRST line permanently enables the DAP Interface the
TARGET setting is required.
In case the CPU DAP Interface should not be enabled although a debugger is attached to the target board,
the OFF setting is recommended. When performing a SYStem.Mode Go or SYStem.Mode Up, the
debugger enables the CPU DAP Interface automatically when performing the PORST. Note that a
SYStem.Mode Attach is not possible in this case.
23
If the CPU DAP Interface should be enabled as long as the debugger is attached, the ON setting is required.
All SYStem.Mode options are possible in this case, including hot attach.
See Application Note Debug Cable TriCore (tricore_app_ocds.pdf) for details.
SYStem.CONFIG.DAP.USERn
Configure and set USER pins
Format:
SYStem.CONFIG.DAP.USER0 [In | Out | Set <level>]

SYStem.CONFIG.DAP.USER1 [In | Out | Set <level>]
<level>
Low | High
Default: Out and Low.

Configures the USER0 and USER1 pins of the 10 pin DAP Debug Connector as input or output. The ouput
level can be Low or High.
Use the general functions DAP.USER0() and DAP.USER1() for reading the current status.
The availability of the USER pins depends on the Debug Cable, the selected Interface Mode and the DAP
Enabling Mode. See Application Note Debug Cable TriCore (tricore_app_ocds.pdf) for details.
SYStem.CONFIG.DEBUGPORTTYPE
Format:
Set debug cable interface mode
SYStem.CONFIG.DEBUGPORTTYPE [JTAG | DAP2 | SPD]

SYStem.CONFIG.Interface [JTAG | DAP2 | SPD (deprecated)
Default: JTAG.
This command is used to configure the Interface Mode used by the Debugger. Both CPU and Debug Cable
must support this mode, see Application Note Debug Cable TriCore (tricore_app_ocds.pdf) for details.
24
SYStem.Option DUALPORT
Format:
Run-time memory access for all windows
SYStem.Option DUALPORT [ON | OFF]
Default: OFF.
The JTAG debugger use the Debug Peripheral Event Controller (DPEC) to access memory. This acts like a
cycle stealing DMA. Therefore memory access can be done even while the CPU is running. On activating
this option the opened data windows will also be refreshed while a user program is running. Please consider
that in this mode the user program will not be executed at full speed.
SYStem.Option IDLEFIX
Format:
Periodically activate/deactivate JTAG connection
SYStem.Option IDLEFIX [ON | OFF]
Default: OFF.
This is a bug fix for PMB7850 which is only available on obsolete ICD hardware. The permanent JTAG
connection did not allow the processor to switch to idle mode which was required for flash programming.
SYStem.Option IMASKASM
Format:
Disable interrupts while single stepping
SYStem.Option IMASKASM [ON | OFF]
Default: OFF.
If enabled, the interrupt mask bits of the CPU will be set during assembler single-step operations. The
interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are
restored to the value before the step.
SYStem.Option IMASKHLL
Format:
Disable interrupts while HLL single stepping
SYStem.Option IMASKHLL [ON | OFF]
Default: OFF.
25
If enabled, the interrupt mask bits of the CPU will be set during HLL single-step operations. The interrupt
routine is not executed during single-step operations. After single step the interrupt mask bits are restored to
the value before the step.
SYStem.Option MonBase
Format:
Define start address of debug monitor
SYStem.Option MonBase <start_address>
ICD-166CBC only. Default: 0x1fffc0.

This is the start address where the exception routine is or will be loaded. The size of the exception routine is
at the moment 32/48 (ICD/AICD) bytes.
SYStem.Option PERSTOP
Format:
Enable global peripheral suspend signal
SYStem.Option PERSTOP [ON | OFF]
Default: OFF.
This controls the operation mode of the peripherals (e.g. timer), when a debug event is raised. A debug
event causes the peripherals to suspend, if this option is activated and the suspend enable bit in the
peripheral module is set.
SYStem.Option PERSTOPFIX
Format:
Break CPU via ONCHIP break register
SYStem.Option PERSTOPFIX [ON | OFF]
Default: OFF.
If asynchronous Break is used and SYStem.Option PERSTOP is set, then this option should be set, too.
Workaround to use complete functionality of peripheral suspend (XC2xxx and XC16x)
26
SYStem.Option BRKOUT
Format:
Activates BRKOUT signal
SYStem.Option BRKOUT [ON | OFF]
Default: OFF.
Activates the BRKOUT signal on the DEBUG connector. Must be connected to the CPU pin.
SYStem.Option WATCHDOG
Format:
Disable or serve watchdog
SYStem.Option WATCHDOG [ON | OFF]
Default: OFF.
This controls if the watchdog is active (on) during the debug session or not (off). See also chapter Monitor
Routine.
SYStem.Option TRACEENABLE
Format:
Disable traceport
SYStem.Option TRACEENABLE [ON | OFF]
Only PMB7890 and XGOLD110.

Default: OFF with Debugger. ON with Combiprobe
Disable/enable trace port from the PMB7890 and XGOLD110.
27
SYStem.Option DebugLevel
Debug level
Format:
SYStem.Option DebugLevel <level>
<level>:
1. 15. TRAP ATOMIC
Only CPUs with C166SV2 core

Default : TRAP
The CPU can be interrupted. The debug level defined the level, where all lower and equal level interrupts are
breaked.
28
SYStem.Option BootModeIndex
BootModeIndex
Format:
SYStem.Option BootModeIndex <interface>
<interface>:
JTAG1, JTAG2, JTAG3, JTAG4, JTAG5, JTAG6, JTAG7, JTAG8,

DAP1, DAP2, SPD
Only XC2xxxLE and XC2xxxULE CPUs

Selects the Debug Interface which is programmed via ASC with the SYStem.Mode Prepare
JTAG1 Mode: TCK=P2.9 TMS=P5.4 TDI=P5.2 TDO=P10.12
DAP1 Mode: DAP0=P2.9 DAP1=P10.12
DAP2 Mode: DAP0=P10.9 DAP1=P10.12
SPD Mode: at P10.12
29
SYStem.Option ICFLUSH
Format:
Flush instruction cache
SYStem.Option ICFLUSH [ON | OFF]
Default: ON.
If enabled, the InstructionCache will be flushed before GO or Step operations. This is required to enforce
consistency between cache and external program memory when the program memory was updated (e.g.
for setting software breakpoints). Typically the option shall be left enabled except when debugging cache
consistency problems in the target. The option is only relevant for XC22xxI, XC23xxE and XC27x8X
because they have a program cache.
SYStem.Option IDLEDEBUG
Format:
Debug in IDLE state
SYStem.Option IDLEDEBUG [ON | OFF]
Only XGOLD110 ES2

If enabled, it is possible to break the aplication if the CPU is in IDLE state. Access to the peripheral register
via real-time access is also possible.
SYStem.Option WaitReset
Delay between PORST and JTAG shifts
Format:
SYStem.Option WaitReset <time>
<time>:
800.ms ... 5000.ms
Only XC2xxx and XE16x.

Default: 1750.ms.
Change the delay between the rising edge of the POST line and the first shifts from the Debugger. Only
necessary to change the delay if a SYStem.Mode Up dont stops a the reset vector.
30
MCDS Onchip Trace
MCDS Onchip Trace Features

Onchip tracing is only possible with an Infineon Emulation Device (ED), offering the MCDS (MultiCore
Debug Solution) for implementing trace triggers, filteres and generation of trace messages (MCDS
messages).
Use Trace.METHOD Onchip for selecting the onchip trace.
Supported Features
Program Flow Trace
Data Trace
Ownership Trace
Timestamps
See the Onchip.Mode commands for a general setup of the on-chip trace, and the MCDS commands for a
detailed setup of the on-chip MCDS resources.
Trace Control
The On-chip settings can be done with the Onchip commands, e.g. from the Onchip.view window. .

Additionally triggers and filters on data address and data value can be configured.
Trace all
Trace to
Trace from
Trace from to
Trigger
Enable
31
MCDS Onchip Trace
MCDS uses compression to efficiently use the limited amount of on-chip trace
memory. TRACE32 requires a synchonization point to decode all consecutive trace
messages.
Examples
A successfully loaded target application is needed for the following examples.
Example 1: Trace function sieve() only
MCDS.view
; show MCDS setup window
; enable C166 program flow trace
Onchip.List
; show trace list window
Break.Set v.range(sieve) /Program

/Onchip /TraceEnable
; enable the trace as long as

; function sieve() is executed
Enable the trace as long as the function sieve() is executed. Execution in sub-functions is not recorded.
Example 2: Trace function sieve() and sub-functions
MCDS.view
Onchip.List
Break.Set sieve /Program /Onchip

/TraceON
; enable trace on entering

; function sieve()
Break.Set y.exit(sieve) /Program

/Onchip /TraceOFF
; disable trace on leaving

; function sieve()
Trace the complete function sieve(), including execution in any sub-function.
32
MCDS Onchip Trace
Example 3: Trace until
MCDS.view
Onchip.List
Break.Set v.end(sieve) /Program /

Onchip /TraceTrigger
; disable trace on leaving

; function sieve()
Stop tracing when end of function sieve() is reached, C166 keeps running. Onchip.TDelay can be used
to stop recording after a programmable period (percentage of the trace memory). See the Trace.Trigger
command for more information.
Example 4: Trace write accesses to a variable
MCDS.view
MCDS.SOURCE C166 FlowTrace OFF
; disable C166 program flow

; trace
MCDS.SOURCE C166 WriteAddr ON

MCDS.SOURCE C166 WriteData ON
; enable C166 write address

; and write data trace
Onchip.List
Break.Set flags+0x0C /Write /Onchip

/TraceEnable
; enable recording when C166

; writes to address flags+0x0C
Trace all write accesses to variable flags with offset 0xc, Program Flow trace is disabled to save on-chip
trace memory.
33
MCDS Onchip Trace
Example 5: Trace specific write accesses to a variable
MCDS.view


Onchip.List
Break.Set flags+0x0C /Write

/Data.Byte 0x01 /Onchip
/TraceEnable

; writes 0x01 to address flags+0x0C
Enable recording when TriCore writes 0x01 with an access width of 8 bits to address flags+0x0C. The code
that triggered the write access is also recorded. Due to pipeline effects and internal delays the recorded
code may not exactly match the write instruction.
Example 6: Trace specific write accesses to a variable
MCDS.view


Onchip.List
Break.Set v.range(sieve)
/MemoryWrite flags+0x0C
/Data.Byte 0x01 /Onchip
/TraceEnable

; writes 0x01 to address flags+0x0C
while executing function sieve()
Enable recording when C166 writes 0x01 with an access width of 8 bits to address flags+0x0C while
executing function sieve() (excluding sub-function). The code that triggered the write access is also
recorded. Due to pipeline effects and internal delays the recorded code may not exactly match the write
instruction.
34
MCDS Onchip Trace
BenchMarkCounter
The BenchMarkCounter are only available with a XC2000ED device.
For information about architecture-independent BMC commands, refer to BMC (general_ref_b.pdf).
For information about architecture-specific BMC commands, see command descriptions below.
BMC.CNTx.EVENT
Configure the performance monitor
Format:
BMC.CNT0 | CNT1 .... CNT7.EVENT <event>
<event>:
NONE
Delta
Echo
NINST
IDLE
STALL
IRA
SYNC_RQ
NONE
Switch off the performance monitor
Delta
Counts hits of the Delta-Marker, if specified.
Echo
Counts hits of the Echo-Marker, if specified.
NINST
Counts the number of instructions.
IDLE
Counts the number of idle cycles.
STALL
Counts the number of stall cycles.
IRA
Counts the number of interrupts acknowledged.
SYNCH_RQ
The counter is incremented at the beginning of a new paragraph of the trace

buffer memory.
35
BenchMarkCounter
Useful Features
This chapter gives an overview on some useful features. Please consult the documentation of the
corresponding commands for more information.
Runtime Measurement
MCDS.view
SETUP.PreFetch 0 2
; sets Prefetch 0 and Alignment 2
MCDS.SOURCE C166 FlowTrace OFF
; disable C166 program flow trace
MCDS.TimeStamp Relative
; sets relative timestamp messages
MCDS.Clock SYStem 80.MHz
; sets system clock
Break.Set sieve /Program /Onchip

/TraceEnable
; enable trace on entering

; function sieve()
Break.Set y.exit(sieve) /Program

/Onchip /TraceEnable
; enable trace on leaving

; function sieve()
Break.SetFunc sieve
; sets marker Alpha at begin and

marker Beta at end of function
sieve()
Trace.STATistic.DURation
; analyze the time between sieve()

entry and sieve() exit
Program BootModeIndex (only XC2xxxULE/LE)
SYStem.CPU XC2210U-8F
; select CPU
SYStem.CONFIG.Interface DAP
; select DAP interface
SYStem.Option BootModeIndex DAP1
; select the desired Interface
SYStem.JtagClock 9600.
; selects the ASC speed 9600 BAUD
SYStem.Mode Prepare
; programs the BootModeIndex
This chapter describes the possibility to program the BootModeIndex via the Debug Cable
This is only possible if the LA-3815 Conv. 16 Pin JTAG to DAP is used.
36
Useful Features
Breakpoints
There are two types of breakpoints available: Software breakpoints and on-chip breakpoints.
Software Breakpoints on Instructions

Software breakpoints are the default breakpoints. They can only be used in RAM areas.There is no
restriction in the number of software breakpoints.
On-chip Breakpoints
The following list gives an overview of the usage of the on-chip breakpoints by
TRACE32-ICD:
On-chip breakpoints: Total amount of available on-chip breakpoints.
Instruction breakpoints: Number of on-chip breakpoints that can be used for program and spot
breakpoints
Data breakpoints: Number of on-chip breakpoints that can be used as read or write
breakpoints.
On-chip Breakpoints
Instruction Breakpoints
Data Breakpoints
up to 4
up to 4 write
up to 1 read
You can check your currently set breakpoints with the command Break.List
If no more on-chip breakpoints are available you will get a message on trying to set a on-chip breakpoint.
On-chip Breakpoints in FLASH/ROM

With the command MAP.BOnchip <range> it is possible to inform the debugger where you have ROM
(FLASH,EPROM) on the target. If a breakpoint is set within the specified address range the debugger uses
automatically the available on-chip breakpoints.
37
Breakpoints
Example for Breakpoints

Assume you have a target with FLASH from 0 to 0xFFFFF and RAM from 0x100000 to 0x11FFFF. The
command to configure TRACE32 correctly for this configuration is:
Map.BOnchip 0x0--0x07FFFF
You inform the debugger that he shall use on-chip breakpoints instead of software breakpoints in the
address range 0-7FFFH (though your flash is up to address FFFFFH).
Examples for instruction breakpoints:
; software breakpoint, instruction
Break.Set 0xx /Program
Three instruction breakpoints are set. Software breakpoints are used.

; on-chip breakpoint, instruction
Break.Set 0x0ff00 /Program
Two instruction breakpoints are set. On-chip breakpoints are used, because of the MAP.BOnchip command.
Break.Set 0x9FFFF /P /Onchip
A instruction breakpoint is set. On-chip breakpoint is used, because of the /Onchip option.
Break.Set 0x8FFFF /Program
; error message
This causes an error, because the debugger tries to set a software breakpoint at this location.
Break.Set 0x8FFFF++0x100 /P
; on-chip breakpoint, instruction,

; range
Breakpoint on an instruction range 8FFFF-900FFH will be set, even if this range is not declared by
MAP.BOnchip command. The reason is, that for range events always on-chip breakpoints will be used.
Examples for breakpoints on data:
Break.Set 0x100000 /Write
; on-chip Breakpoint, data write access
38
Breakpoints
Breakpoint on write access to 100000H.

Break.Set 0x9FFFF /Read
; on-chip Breakpoint, data read access
Breakpoint if read access to 9FFFFH. For breakpoints on data always on-chip breakpoint will be used.
39
Breakpoints
TrOnchip Commands
TrOnchip.view
Format:
Display on-chip trigger window
TrOnchip.view
Open TrOnchip window.
TrOnchip.CONVert
Format:
Adjust range breakpoint in on-chip resource
TrOnchip.CONVert [ON | OFF]
The on-chip breakpoints can only cover specific ranges. If a range cannot be programmed into the
breakpoint it will automatically be converted into a single address breakpoint when this option is active. This
is the default. Otherwise an error message is generated.
TrOnchip.CONVert ON
Break.Set 0x1000--0x17ff /Write
; sets breakpoint at range

; 1000--17ff sets single breakpoint
; at address 1001
TrOnchip.CONVert OFF
; sets breakpoint at range

; 1000--17ff
; gives an error message
TrOnchip.RESet
Format:
Set on-chip trigger to default state
TrOnchip.RESet
Sets the TrOnchip settings and trigger module to the default settings.
40
TrOnchip Commands
TrOnchip.TEnable
Format:
Set filter for the trace
TrOnchip.TEnable <par>
Obsolete command. Refer to the Break.Set command to set trace filters.
TrOnchip.TOFF
Format:
Switch the sampling to the trace to OFF
TrOnchip.TOFF
TrOnchip.TON
Format:
Switch the sampling to the trace to ON
TrOnchip.TON EXT | Break
TrOnchip.TTrigger
Format:
Set a trigger for the trace
TrOnchip.TTrigger <par>
Obsolete command. Refer to the Break.Set command to set a trigger for the trace.
41
TrOnchip Commands
TrOnchip.VarCONVert
Format:
Adjust complex breakpoint in on-chip resource
TrOnchip.VarCONVert [ON | OFF]
The on-chip breakpoints can only cover specific ranges. If you want to set a marker or breakpoint to a
complex variable, the on-chip break resources of the CPU may be not powerful enough to cover the whole
structure. If the option TrOnchip.VarCONVert is ON the breakpoint will automatically be converted into a
single address breakpoint. This is the default setting. Otherwise an error message is generated.
TrOnchip.Address
Format:
Define address selector
TrOnchip.Address Alpha | Beta | Charly | Delta | Echo
The address/range for an address selector can not be defined directly. Set an breakpoint of the type Alpha,
Beta or Charly to the address/range.
Break.Set 1000 /Alpha
/Onchip
; set an Alpha breakpoint to 1000

; use Alpha breakpoint as address
; selector for the TrOnchip unit
TrOnchip.CYcle
Format:
Define access type
TrOnchip.CYcle Read | Write | eXecute
Defines on which cycle the program execution stop
Read
Stop the program execution on a read access.
Write
Stop the program execution on a write access.
eXecute
Stop the program execution on an instruction is executed.
42
TrOnchip Commands
TrOnchip.Data
Format:
Define data selector
TrOnchip.Data [<range> <value> <bitmask>]
TrOnchip.NoMatch
Format:
Define match or nomatch comparison
TrOnchip.NoMatch [ON | OFF]
default off
TrOnchip.TaskID
Format:
Define TASKID comparison
TrOnchip.TaskID [<value> <bitmask>]
The application must write to the DTIDR (Task ID Register) at address D:0xF0D8. This register is intendend
to be used by advanced real time operating systems to store the task ID of the active task.
43
TrOnchip Commands
Connectors
JTAG Connector
Signal
TMS
TDO
CPUCLOCK
TDI
TRSTTCLK
BRKINN/C
Pin
1
3
5
7
9
11
13
15
Pin
2
4
6
8
10
12
14
16
Signal
VCCS
GND
GND
RESETBRKOUTGND
N/C
GND
A standard 2 x 8 pin header (pin to pin spacing: 0.1 inch = 2.54 mm) is required on the target.
Do not connect the reserved pins.
Do connect all GND pins for shielding purpose, though they are connected on the debugger. It is
recommended to connect also the N/C pin to GND.
At least the signals TMS, VCCS, TDO, GND, TDI, /RESET, /TRST, TCLK are required.
CPUCLOCK is only necessary if it should be used as jtag clock source. It is not used on AICD. /BrkIN, /
BrkOUT are used for trigger input / output feature.
VCCS is the processor power supply voltage. It is used to detect if target power is on and it is used to supply
the output buffers of the debugger (it takes about 2 mA). That means the output voltage of the debugger
signals (TMS, TDI, /TRST, TCLK, /BrkIN) depends directly on VCCS. VCCS can be 2.25 5.5 V.
/RESET is controlled by an open drain driver. (An external watchdog must be switched off if the In-Circuit
Debugger is used.)
VIHmin = 2.0 V, VILmax = 0.8 V for the input pins VCCS, TDO, CPUCLOCK, /BrkOUT.
When having multiple JTAG TAP controllers in the chain, make sure that the C166 is the first device in the
chain. It is not possible to have another XC2000, XC16x or TriCore in the same chain.
44
Connectors
DAP Connector
Signal
VREF
GND
GND
GND
GND
Pin
1
3
5
7
9
Pin
2
4
6
8
10
Signal
DAP1
DAP0
USER0
DAPEN- (TRST-)
RESET- (PORST-)
only possible with Whisker Debug Cable and LA-3815 Conv. 16 Pin JTAG to DAP
On the target board the standard connector is a 0.05 inch double row 10 pins micro terminal, which is
available from many sources e.g. Samtec FTSH (SMT Mount) series. It is offered as a standard dual
row header 1.27 mm x 1.27 mm with 0.4 mm square pins.
45
Connectors
Troubleshooting
SYStem.Up Errors
The SYStem.Up command is the first command of a debug session where communication with the target is
required. If you receive error messages while executing this command this may have the following reasons.
The target has no power.
ICD-166CBC only: The trap program routine is not available or the MONBASE address is not
correct or the jump to this function at 20H is missing (see Monitor). Another restriction is that a
valid program which disables the debugger must start after power on. If one of these conditions
are not fulfilled (e.g. if there is no program on the target) it can be helpful to activate the debugger
by SYStem.Mode Prepare to do some initialization with the debuggers help. See also the batch
files in \demo\c166\etc\.
ICD-166CBC only: Unfortunately it is possible that a faulty user program which starts after power
on produces a situation where it is not possible for the debugger to establish communication with
the processor. To avoid this situation we recommend to place a endless loop (after disabling the
watchdog and settings like stack and chip selects) at the begin of the user application. Then the
debugger can establish the communication and you can step through the program to come closer
to the faulty program part. It is also useful to have the possibility (jumper on chip select signal) to
switch off the program memory on the target. Even if you already have the situation I described
above, you can then use SYStem.Mode Prepare to establish communication and for example reprogram the program memory if it is placed in a flash device.
External controlled /RESET line:

The debugger controls the processor reset and use the /RESET line to reset the CPU on most of
the SYStem.Mode commands. Therefore only not active, open-drain driver may be connected to
this /RESET signal.
There are additional loads or capacities on the JTAG lines or the JTAG cable is elongated.
46
Troubleshooting
FAQ
Debugging via
VPN
The debugger is accessed via Internet/VPN and the performance is very

slow. What can be done to improve debug performance?
The main cause for bad debug performance via Internet or VPN are low data
throughput and high latency. The ways to improve performance by the debugger
are limited:
in practice scripts, use "SCREEN.OFF" at the beginning of the script and
"SCREEN.ON" at the end. "SCREEN.OFF" will turn off screen updates.
Please note that if your program stops (e.g. on error) without executing
"SCREEN.OFF", some windows will not be updated.
"SYStem.POLLING SLOW" will set a lower frequency for target state
checks (e.g. power, reset, jtag state). It will take longer for the debugger to
recognize that the core stopped on a breakpoint.
"SETUP.URATE 1.s" will set the default update frequency of Data.List/
Data.dump/Variable windows to 1 second (the slowest possible setting).
prevent unneeded memory accesses using "MAP.UPDATEONCE
[address-range]" for RAM and "MAP.CONST [address--range]" for ROM/
FLASH. Address ranged with "MAP.UPDATEONCE" will read the specified
address range only once after the core stopped at a breakpoint or manual
break. "MAP.CONST" will read the specified address range only once per
SYStem.Mode command (e.g. SYStem.Up).
47
FAQ
Setting a
Software
Breakpoint fails
What can be the reasons why setting a software breakpoint fails?

Setting a software breakpoint can fail when the target HW is not able to
implement the wanted breakpoint.
Possible reasons:
The wanted breakpoint needs special features that are only possible to
realize by the trigger unit inside the controller.
Example: Read, write and access (Read/Write) breakpoints ("type" in Break.Set
window). Breakpoints with checking in real-time for data-values ("Data").
Breakpoints with special features ("action") like TriggerTrace, TraceEnable,
TraceOn/TraceOFF.
TRACE32 can not change the memory.
Example: ROM and Flash when no preparation with FLASH.Create,
FLASH.TARGET and FLASH.AUTO was made. All type of memory if the
memory device is missing the necessary control signals like WriteEnable or
settings of registers and SpecialFunctionRegisters (SFR).
Contrary settings in TRACE32.
Like: MAP.BOnchip for this memory range. Break.SELect.<breakpoint-type>
Onchip (HARD is only available for ICE and FIRE).
RTOS and MMU:
If the memory can be changed by Data.Set but the breakpoint doesn't work it
might be a problem of using an MMU on target when setting the breakpoint to a
symbolic address that is different than the writable and intended memory
location.
"SYStem.Up"
does not work
The installation is ok, but when trying "SYStem.Up" the debugger

responds with the error message "emulation debug port time-out".
See chapter "Trouble-Shooting" in the "ICD Targets" guide in the online help.
Debugging in
Idle Mode
Why does the debugger switch to 'DOWN' mode when idle mode is entered
by the processor?
When the processor enters the idle mode the communication channel to the
debugger will be cut off. Debugging is not possible in this mode.
Single Step on
Extended
Sequence
Why does extended register, page or segment commands overstep the

next commands?
For execution of a single step a debug trap is used. During the execution of
these extended sequences the software trap is locked. Affected commands are
EXTR, EXTP, EXTPR, EXTS, EXTSR.
Software
Breakpoint on
extended
Sequence
Why do I get wrong program behavior when setting a software breakpoint

on an extended sequence?
A software breakpoint within an extended sequence aborts the extended
sequence. Therefore do not use a software breakpoint within the extended
sequence or use a hardware breakpoint instead. Affected commands are EXTR,
EXTP, EXTPR, EXTS, EXTSR.
48
FAQ
49
FAQ
Technical Data
Operation Voltage
Adapter
OrderNo
Voltage Range
OCDS Debugger for C166CBC (ICD)
LA-7755
2.5 .. 5.2 V
Adapter
OrderNo
Voltage Range
OCDS Debugger for XC2000/C166S V2 (ICD)

OCDS Debugger for XC2000/C166S V2 Additional
LA-7759
LA-7759A
2.5 .. 5.2 V
2.5 .. 5.2 V
50
Technical Data
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
ICD
DEBUG
ICE
PMB7890
PMB7900
XC161CJ
XC161CS
XC164CM
XC164CS
XC164D
XC164GM
XC164KM
XC164LM
XC164N
XC164S
XC164SM
FIRE
YES YES YES YES

YES YES YES YES
YES YES YES YES
YES YES YES
YES YES YES
YES YES YES
YES YES YES YES
YES YES YES
YES YES YES
YES YES YES
YES YES YES
YES YES YES
CPU
C161U
C165H
C165UTAH
C166CBC
INCA-P
PMB2850_E-GOLD
PMB6850_E-GOLD+
PMB7850_E-GOLD+
PMB7860
PMB7870
PMB7880
SDA6000_M2
FIRE
ICE
CPU
Available Tools
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
51
Support
YES YES YES

YES YES YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
YES YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
XC164TM
XC167CI
XC2000ED
XC2210U
XC2220L
XC2220U
XC2224L
XC2230L
XC2234L
XC2234N
XC2236N
XC2237M
XC2238M
XC2238N
XC2263M
XC2263N
XC2264
XC2265M
XC2265N
XC2267
XC2267M
XC2268I
XC2268N
XC2269I
XC2285
XC2285M
XC2286
XC2286M
XC2287
XC2287M
XC2288H
XC2288I
XC2289H
XC2289I
XC2297H
XC2298H
XC2299H
XC2310S
XC2320D
XC2320S
XC2321D
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
52
Support
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
XC2330D
XC2331D
XC2336A
XC2336B
XC2361A
XC2361B
XC2361E
XC2363A
XC2363B
XC2364A
XC2364B
XC2365
XC2365A
XC2365B
XC2367E
XC2368E
XC2385A
XC2387
XC2387A
XC2387C
XC2387E
XC2388C
XC2388E
XC2712X
XC2722X
XC2723X
XC2733X
XC2734X
XC2735X
XC2764X
XC2765X
XC2766X
XC2768X
XC2785X
XC2786X
XC2787X
XC2788X
XC2797X
XE160FU
XE161FL
XE161FU
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
53
Support
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
XE162FL
XE162FM
XE162FN
XE162HM
XE162HN
XE164F
XE164FM
XE164FN
XE164G
XE164GM
XE164GN
XE164H
XE164HM
XE164HN
XE164K
XE164KM
XE164KN
XE167F
XE167FH
XE167FM
XE167G
XE167GM
XE167H
XE167HM
XE167K
XE167KM
XE169FH
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Compilers
Language
Compiler
Company
Option
C
C
C
C166
XC16X/ST10
GNU-GCC166
EOMF-166
ELF/DWARF
DBX
C
C++
C166
GNU-CPP166
C++
CP166
ARM Germany GmbH

Cosmic Software
HighTec EDV-Systeme
GmbH
TASKING
HighTec EDV-Systeme
GmbH
TASKING
Comment
IEEE
DBX
IEEE
54
Support
Realtime Operation Systems

Name
Company
Comment
ARTX-166
CMX-RTX
Elektrobit tresos
Erika
Nucleus PLUS
osCAN
OSE Basic
OSE Epsilon
OSEK
ProOSEK
PXROS
RTX166/-tiny
RTXC 3.2
RTXC Quadros
Rubus OS
SDT-Cmicro
uC/OS-II
ARM Germany GmbH

CMX Systems Inc.
Elektrobit Automotive GmbH
Evidence
Mentor Graphics Corporation
Vector
Enea OSE Systems
Enea OSE Systems
Elektrobit Automotive GmbH
HighTec EDV-Systeme GmbH
ARM Germany GmbH
Quadros Systems Inc.
Quadros Systems Inc.
Articus Systems AB
IBM Corp.
Micrium Inc.
via ORTI
via ORTI
via ORTI
(OS166)
(OS166), 3.x
via ORTI
via ORTI
2.0 to 2.92
3rd Party Tool Integrations

CPU
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
Host
Windows
Windows
Windows
Code Confidence Ltd
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
Windows
Windows
Windows
Windows
Windows
Windows
55
Support
CPU
Tool
Company
Host
ALL
UML DEBUGGER
Windows
ALL
ALL
ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
C166
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
SDT CMICRO
Windows
Windows
NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
IBM Corp.
Windows
56
Support
Products
Product Information
OrderNo Code
Text
LA-7755
OCDS-C166CBC
supports E-GOLD, E-GOLD+, DOLCE, UTAH, M2, X-GOLD101

includes software for Windows, Linux and MacOSX
requires Power Debug Module
debug cable with 16 pin connector
OrderNo Code
Text
LA-7759
OCDS-C166S-V2
supports C166S V2, XC16x, XE166, XC2000, X-GOLD102

includes software for Windows, Linux and MacOSX
requires Power Debug Module
supports 16-pin standard JTAG
10-pin DAP interface requires LA-3815
and debug cable with serial number higher
than C0809xxxxxxx
LA-7759A
OCDS-C166S-V2-A
supports C166S V2, XC16x, XE166, XC2000, X-GOLD102

please add the serial number of the base debug
cable or CombiProbe to your order
LA-7975X
Off-Chip Trace for MCDS of C166S-V2
OFFCHIP-TRACE-C166S
supports X-GOLD102 (PMB7890) and X-GOLD110 (PMB7900)

MCDS features of C166S-V2 family through JTAG
Supports 4-Bit program trace by using
LA-4506 CombiProbe C166V2-Debugger and 4-Bit Trace
LA-3797X
Onchip Trace for XC2000/C166S V2
ONCHIP-TRACE-C166SV2
supports SMARTi_LU, XC2xxx, XE16x

Onchip Trace and MCDS features through JTAG/DAP
please provide the serial number for LA-7759
together with the order
LA-3815
Conv. 16 Pin JTAG to DAP for TriCore/XC2000
CON-JTAG16-DAP
Converter 16 Pin JTAG to 10 Pin

Halfe-Size-Connector DAP Interface
for TriCore / XC2000
requires
LA-7759 (OCDS Debugger for XC2000/C166S V2)
or
LA-7756 (OCDS Debugger for TriCore)
Order Information
Order No.
Code
Text
LA-7755
OCDS-C166CBC

57
Products
Order No.
Code
Text
Additional Options
LA-7789A JTAG-OAK-SEIB-A
JTAG Debugger for TeakLite/OAK SEIB (ICD)
Order No.
Code
Text
LA-7759
LA-7759A
LA-7975X
LA-3797X
LA-3815
OCDS-C166S-V2
OCDS-C166S-V2-A
OFFCHIP-TRACE-C166S
ONCHIP-TRACE-C166SV2
CON-JTAG16-DAP

Off-Chip Trace for MCDS of C166S-V2
Onchip Trace for XC2000/C166S V2
Conv. 16 Pin JTAG to DAP for TriCore/XC2000
Additional Options
LA-7789A JTAG-OAK-SEIB-A
LA-7756A OCDS-TRICORE-A
JTAG Debugger for TeakLite/OAK SEIB (ICD)

Debugger for TriCore Standard Additional
58
Products

Debugger 166cbc

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XC2000/XC16x/C166CBC Debugger

TRACE32 Online Help

ICD In-Circuit Debugger ................................................................................................................

Processor Architecture Manuals ..............................................................................................

C166 Family .............................................................................................................................

XC2000/XC16x/C166CBC Debugger ...................................................................................

General Note ......................................................................................................................

Brief Overview of Documents for New Users .................................................................

Monitor Routine .................................................................................................................

Quick Start .........................................................................................................................

Quick Start for Tracing with MCDS On-chip Trace

1. Start and Stop Tracing

2. Specify Trace Source and Recording Options

3. Start and Stop Tracing

4. View the Results

Memory Classes ................................................................................................................

Define JTAG frequency

Select the CPU

Run-time memory access (intrusive)

Define the JTAG frequency

Real-time memory access (non-intrusive)

Establish the communication with the CPU

Lock and tristate the debug port

Configure debugger according to target topology

Assign core to TRACE32 instance

Define mapping for DAP pins

Define mapping of break pins

Enable DAP mode on PORST

Configure and set USER pins

Set debug cable interface mode

Run-time memory access for all windows

Periodically activate/deactivate JTAG connection

Disable interrupts while single stepping

Disable interrupts while HLL single stepping

Define start address of debug monitor

Enable global peripheral suspend signal

Break CPU via ONCHIP break register

Activates BRKOUT signal

Disable or serve watchdog

Flush instruction cache

Debug in IDLE state

Delay between PORST and JTAG shifts

MCDS Onchip Trace ..........................................................................................................

MCDS Onchip Trace Features

Simple Trace Control

Configure the performance monitor

Useful Features .................................................................................................................

Software Breakpoints on Instructions

On-chip Breakpoints in FLASH/ROM

Example for Breakpoints

TrOnchip Commands ........................................................................................................

Display on-chip trigger window

Adjust range breakpoint in on-chip resource

Set on-chip trigger to default state

Set filter for the trace

Switch the sampling to the trace to OFF

Switch the sampling to the trace to ON

Set a trigger for the trace

Adjust complex breakpoint in on-chip resource

Define address selector

Define access type

Define data selector

Define match or nomatch comparison

Define TASKID comparison