Debugger Cortexm

Cortex-M Debugger
TRACE32 Online Help

TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................
ICD In-Circuit Debugger ................................................................................................................
Processor Architecture Manuals ..............................................................................................
ARM/CORTEX/XSCALE ...........................................................................................................
Cortex-M Debugger ..............................................................................................................
Brief Overview of Documents for New Users .................................................................
Warning ..............................................................................................................................
Quick Start of the JTAG Debugger ..................................................................................
Troubleshooting ................................................................................................................
Communication between Debugger and Processor can not be established
FAQ .....................................................................................................................................
Trace Extensions ...............................................................................................................
10
Cortex-M Specific Implementations ................................................................................
11
Breakpoints
11
Software Breakpoints
11
On-chip Breakpoints for Instructions
11
On-chip Breakpoints for Data
11
Example for Standard Breakpoints
14
Trigger
16
Virtual Terminal
16
Semihosting
16
Runtime Measurement
18
Memory Classes
19
Cortex-M specific Onchip Commands ............................................................................

Onchip.Mode RAMPRIV
21
SRAM privilege access
21
Onchip.Mode SFRWPRIV
Special function register write access
21
Onchip.Mode TSTARTEN
Enable TSTART signal
21
Onchip.Mode TSTOPEN
Enable TSTOP signal
21
Base address of the trace buffer
22
Cortex-M specific SYStem Commands ...........................................................................
23
Onchip.TBADDRESS
SYStem.BdmClock
Define JTAG frequency

1989-2016 Lauterbach GmbH
Cortex-M Debugger
23
SYStem.CLOCK
Inform debugger about core clock
SYStem.CONFIG
Configure debugger according to target topology
23
23
<parameter> General
29
<parameter> describing the Debugport
30
<parameter> describing the JTAG scan chain and signal behavior
35
<parameter> describing a system level TAP Multitap
39
<parameter> configuring a CoreSight Debug Access Port DAP
41
<parameter> describing debug and trace Components
45
<parameter> which are Deprecated
54
SYStem.CPU
SYStem.CpuAccess
Select the used CPU
58
Run-time memory access (intrusive)
59
60
Tristate the JTAG port
62
SYStem.JtagClock
SYStem.LOCK
SYStem.MemAccess
SYStem.Mode
Run-time memory access
63
Establish the communication with the target
65
Select AHB-AP HPROT bits.
66
ACE enable flag of the AXI-AP
66
SYStem.Option AHBHPROT
SYStem.Option AXIACEEnable
SYStem.Option AXICACHEFLAGS
Select AXI-AP CACHE bits.
66
SYStem.Option AXIHPROT
Select AXI-AP HPROT bits.
66
Define byte order (endianess)
67
AHB-AP type of the Cortex-M
67
No DAP instruction register check
67
Rearrange DAP memory map
68
Options for debug port handling
68
Activate more log messages
69
SYStem.Option BigEndian
SYStem.Option CORTEXMAHB
SYStem.Option DAPNOIRCHECK
SYStem.Option DAPREMAP
SYStem.Option DEBUGPORTOptions
SYStem.Option DIAG
SYStem.Option DISableSOFTRESet
Disable software reset
69
Define disassembler mode
70
Implicitly use run-time memory access
70
Allow the debugger to drive nSRST
71
SYStem.Option DisMode
SYStem.Option DUALPORT
SYStem.Option EnReset
SYStem.Option IMASKASM
SYStem.Option IMASKHLL
Disable interrupts while single stepping
71
Disable interrupts while HLL single stepping
71
Debugging of an Intel SOC
71
Disable all interrupts
72
SYStem.Option IntelSOC
SYStem.Option INTDIS
SYStem.Option LOCKRES
Go to 'Test-Logic Reset' when locked
72
Select memory-AP HPROT bits
72
Enable multiple address spaces support
72
No check of the running state
73
SYStem.Option MEMORYHPROT
SYStem.Option MMUSPACES
SYStem.Option NoRunCheck
SYStem.Option OVERLAY
Enable overlay support
73
Mode to handle special power recovery
74
SYStem.Option ResBreak
Halt the core after reset
75
SYStem.Option RESetREGister
Generic software reset
76
SYStem.Option PWRDWNRecover
SYStem.Option RisingTDO
Target outputs TDO on rising edge
77
Select Cortex-M DAP
77
SYStem.Option SELECTDAP
Cortex-M Debugger
SYStem.Option SOFTLONG
SYStem.Option SOFTWORD
Use 32-bit access to set breakpoint
77
77
Use software breakpoints for ASM stepping
78
SYStem.Option DAPSYSPWRUPREQ
Force system power in DAP
78
SYStem.Option DAP2SYSPWRUPREQ
Force system power in DAP2
78
SYStem.Option STEPSOFT
SYStem.Option TRST
SYStem.Option WaitReset
Allow debugger to drive TRST
79
Wait with JTAG activities after deasserting reset
79
Set acknowledge after wakeup
79
Enable symbol management for ARM zones
80
SYStem.Option WakeUpACKnowledge
SYStem.Option ZoneSPACES
SYStem.RESetOut
Performs a reset
85
Display SYStem.state window
85
ARM Specific Benchmarking Commands .......................................................................
86
SYStem.state
BMC.Trace
Activate BMC trace
86
ARM specific TrOnchip Commands ................................................................................
87
TrOnchip.view
TrOnchip.CONVert
Display on-chip trigger window
87
Extend the breakpoint range
87
Reserve on-chip breakpoint comparators
87
Reset on-chip trigger settings
88
Set bits in the vector catch register
89
Convert variable breakpoints
90
JTAG Connection ..............................................................................................................
91
Support ...............................................................................................................................
92
TrOnchip.RESERVE
TrOnchip.RESet
TrOnchip.Set
TrOnchip.VarCONVert
Available Tools
92
Compilers
140
Realtime Operation System
141
3rd Party Tool Integrations
141
Products .............................................................................................................................
143
Product Information
143
Order Information
144
Cortex-M Debugger
Cortex-M Debugger
Version 24-May-2016
Brief Overview of Documents for New Users

Architecture-independent information:
Debugger Basics - Training (training_debugger.pdf): Get familiar with the basic features of a
TRACE32 debugger.
T32Start (app_t32start.pdf): T32Start assists you in starting TRACE32 PowerView instances

for different configurations of the debugger. T32Start is only available for Windows.
General Commands (general_ref_<x>.pdf): Alphabetic list of debug commands.
Architecture-specific information:
Processor Architecture Manuals: These manuals describe commands that are specific for the
processor architecture supported by your debug cable. To access the manual for your processor
architecture, proceed as follows:
-
Choose Help menu > Processor Architecture Manual.
RTOS Debugger (rtos_<x>.pdf): TRACE32 PowerView can be extended for operating systemaware debugging. The appropriate RTOS manual informs you how to enable the OS-aware
debugging.
If you are using a TRACE32 CombiProbe, please refer also to CombiProbe for Cortex-M Users
Guide (combiprobe_cortexm.pdf)
Cortex-M Debugger
Brief Overview of Documents for New Users
Warning
NOTE:
To prevent debugger and target from damage it is recommended to connect or

disconnect the debug cable only while the target power is OFF.
Recommendation for the software start:
1.
Disconnect the debug cable from the target while the target power is
off.
2.
Connect the host system, the TRACE32 hardware and the debug
cable.
3.
Power ON the TRACE32 hardware.
4.
Start the TRACE32 software to load the debugger firmware.
5.
Connect the debug cable to the target.
6.
Switch the target power ON.
7.
Configure your debugger e.g. via a start-up script.
Power down:
1.
Switch off the target power.
2.
Disconnect the debug cable from the target.
3.
Close the TRACE32 software.
4.
Power OFF the TRACE32 hardware.
Cortex-M Debugger
Warning
Quick Start of the JTAG Debugger

Starting up the debugger is done as follows:
1.
Select the device prompt for the ICD Debugger and reset the system.
b::
RESet
The device prompt B:: is normally already selected in the command line. If this is not the case enter
B:: to set the correct device prompt. The RESet command is only necessary if you do not start
directly after booting the TRACE32 development tool.
2.
Specify the core specific settings.

SYStem.CPU <cputype>
SYStem.Option EnReset [ON|OFF]
The default values of all other option are set in such a way that it should be possible to work without
modification. Please consider that this is probably not the best configuration for your target.
3.
Inform the debugger about read only address ranges (ROM, FLASH).
MAP.BOnchip 0x100000++0x0fffff
The B(reak)Onchip information is necessary to decide where on-chip breakpoints must be used. Onchip breakpoints are necessary to set program breakpoints to FLASH/ROM.
4.
Enter debug mode.

SYStem.Up
This command resets the core and enters debug mode. After this command is executed it is possible
to access memory and registers.
5.
Load stack pointer and program counter from the vector table.
Register.Init
Cortex-M Debugger
6.
Load the program.

Data.LOAD.AIF armf
(aif specifies the format,

armf is the file name)
The format of the Data.LOAD command depends on the file format generated by the compiler. Refer
to Supported Compilers to find the command, that is necessary for your compiler.
A detailed description of the Data.LOAD command and all available options is given in the General
Commands Reference.
A typical start sequence is shown below. This sequence can be written to an ASCII file (script
file) and executed with the command DO <filename>.
WinClear
;Clear all windows
SYStem.CPU CORTEXM3
;Select the core type
MAP.BOnchip 0x100000++0xfffff
;Specify where FLASH/ROM is
SYStem.Up
;Reset the target and enter debug mode
Register.Init
;Load stack pointer and program

;counter
Data.LOAD.AXF armf
;Load the application
Register.Set PC main
;Set the PC to function main
Register.Set R13 0x8000
;Set the stack pointer to address 8000
Data.List
;Open source code window *)
Register /SpotLight
;Open register window
Frame.view /Locals /Caller
;Open the stack frame with

;local variables
*)
Break.Set 0x1000 /p
;Set software breakpoint to address

;1000 (address 1000 outside of BOnchip
;range)
Break.Set 0x101000 /p
;Set on-chip breakpoint to address

;101000 (address 101000 is within
;BOnchip range)
*)
*) These commands open windows on the screen. The window position can be specified with the WinPOS
command.
Cortex-M Debugger
Troubleshooting
Communication between Debugger and Processor can not be established

Typically the SYStem.Up command is the first command of a debug session where communication with the
target is required. If you receive error messages like debug port fail or debug port timeout while executing
this command this may have the reasons below. target processor in reset is just a follow-up error message.
Open the AREA window to see all error messages.
The target has no power or the debug cable is not connected to the target. This results in the
error message target power fail.
You did not select the correct core type SYStem.CPU <type>.
There is an issue with the JTAG interface. See ARM JTAG Interface Specifications
(app_arm_jtag.pdf) and the manuals or schematic of your target to check the physical and
electrical interface. Maybe there is the need to set jumpers on the target to connect the correct
signals to the JTAG connector.
There is the need to enable (jumper) the debug features on the target. It will e.g. not work if
nTRST signal is directly connected to ground on target side.
The debug access port is in an unrecoverable state. Re-power your target and try again.
The target can not communicate with the debugger while in reset. Try SYStem.Mode Attach
followed by Break instead of SYStem.UP or use SYStem.Option EnReset OFF.
The default JTAG clock speed is too fast, especially if you emulate your core or if you use an
FPGA based target. In this case try SYStem.JtagClock 50kHz and optimize the speed when you
got it working.
The core is used in a multicore system and the appropriate multicore settings for the debugger
are missing. See for example SYStem.CONFIG DAPIRPRE. This is the case if you get a value
IR_Width > 4 when you enter DIAG 3400 and AREA. If you get IR_Width = 4, then you have
just the Cortex-M3 and you do not need to set these options. If the value can not be detected,
then you might have a JTAG interface issue.
The core has no clock.
The core is kept in reset.
There is a watchdog which needs to be deactivated.
Your target needs special debugger settings. Check the directory \demo\arm if there is an
suitable PRACTICE script file (*.cmm) for your target.
Cortex-M Debugger
Troubleshooting
FAQ
No information available
Cortex-M Debugger
FAQ
Trace Extensions
A Embedded Trace Macrocell (ETM) might be integrated into the core. The Embedded Trace Macrocell
provides program and data flow information plus trigger and filter features.
Please refer to the online help books ARM-ETM Trace (trace_arm_etm.pdf) and ARM-ETM
Programming Dialog (trace_arm_etm_dialog.pdf) for detailed information about the usage of ETM.
Please note that you need to inform the debugger in the start-up script about the location of the trace control
register and funnel configuration in case a trace bus is used. See SYStem.CONFIG ETMBASE,
SYStem.CONFIG FUNNELBASE, SYStem.CONFIG TPIUBASE, SYStem.CONFIG ETMFUNNELPORT.
In case a HTM or ITM module is available and shall be used you need also settings for that.
Cortex-M Debugger
10
Trace Extensions
Cortex-M Specific Implementations
Breakpoints
Software Breakpoints
If a software breakpoint is used, the original code at the breakpoint location is patched by a breakpoint code.
On-chip Breakpoints for Instructions

If on-chip breakpoints are used, the resources to set the breakpoints are provided by the core. On-chip
breakpoints are usually needed for instructions in FLASH/ROM. On Cortex-M on-chip breakpoints can only
be used in the address range 0x00000000 - 0x1fffffff.
With the command MAP.BOnchip <range> it is possible to tell the debugger where you have ROM / FLASH
on the target. If a breakpoint is set into a location mapped as BOnchip one on-chip breakpoint is
automatically programmed.
On-chip Breakpoints for Data

To stop the core after a read or write access to a memory location on-chip breakpoints are required. In the
ARM notation these breakpoints are called watchpoints.
Cortex-M Debugger
11
Overview
On-chip breakpoints: Total amount of available on-chip breakpoints.
Instruction breakpoints: Number of on-chip breakpoints that can be used to set program
breakpoints into ROM/FLASH/EPROM.
Read/Write breakpoints: Number of on-chip breakpoints that can be used as Read or Write
breakpoints.
Data breakpoint: Number of on-chip data breakpoints that can be used to stop the program
when a specific data value is written to an address or when a specific data value is read from an
address
On-chip
Breakpoints
Instruction
Breakpoints
Read/Write
Breakpoints
Data
Breakpoint
Cortex-M0/
M0+
1-4 (by BU Breakpoint Unit)

1-2 (by DW - Data
Watchpoint Unit)
1-4 (BU)
single address
(onchip flash
only) and
1-2 (DW unit)
range as bit
mask
1-2 (DW unit)

range as bit
mask
Cortex-M1
2/4 (by BU Breakpoint Unit)

1/2 (by DW - Data
Watchpoint Unit)
2 or 4 (BU)
single address
(onchip flash
only) and
1 or 2 (DW unit)
range as bit
mask
1 or 2 (DW unit)
range as bit
mask
Cortex-M3
6 (by FPB - Flash

Patch and
Breakpoint Unit)
4 (by DWT - Data
Watchpoint and
Trace Unit)
6 (FPB)
single address
(onchip flash
only) and
4 (DWT )
range as bit
mask
4 (DWT)
range as bit
mask
1
needs two DWT
comparators
Cortex-M4
2/6 (by FPB - Flash

Patch and
Breakpoint Unit)
1/4 (by DWT - Data
Watchpoint and
Trace Unit)
2 or 6 (FPB)
single address
(onchip flash
only) and
1 or 4 (DWT )
range as bit
mask
1 or 4 (DWT)
range as bit
mask
0 or 1
needs two DWT
comparators
Cortex-M Debugger
12
Cortex-M7
4/8 (by FPB - Flash

Patch and
Breakpoint Unit)
2/4 (by DWT - Data
Watchpoint and
Trace Unit)
4 or 8 (FPB)
single address
(onchip flash
only) and
2 or 4 (DWT )
range as bit
mask
2 or 4 (DWT)
range as bit
mask
1
needs two DWT
comparators
Cortex-M Debugger
13
Example for Standard Breakpoints

Assume you have a target with
FLASH from 0x0--0xfffff
RAM from 0x100000--0x11ffff
The command to configure TRACE32 correctly for this configuration is:

Map.BOnchip 0x0--0xfffff
The following standard breakpoint combinations are possible.
1.
2.
3.
Unlimited breakpoints in RAM and one breakpoint in ROM/FLASH

Break.Set 0x100000 /Program
Software breakpoint 1
Break.Set addr /Program
On-chip breakpoint
Unlimited breakpoints in RAM and one breakpoint on a read or write access

Break.Set addr /Program
Break.Set 0x108000 /Write
On-chip breakpoint-
Two breakpoints in ROM/FLASH

On-chip breakpoint 1
Cortex-M Debugger
14
4.
5.
Two breakpoints on a read or write access

Break.Set 0x108000 /Write
Break.Set 0x108010 /Read
One breakpoint in ROM/FLASH and one breakpoint on a read or write access

Break.Set 0x108010 /Read
Cortex-M Debugger
15
Trigger
A bidirectional trigger system allows the following two events:
trigger an external system (e.g. logic analyzer) if the program execution is stopped.
stop the program execution if an external trigger is asserted.
For more information refer to the TrBus command.
Virtual Terminal
The command TERM opens a terminal window in the debugger which allows to communicate with the
program running on the Cortex-M. All data received are displayed in this window and all data inputs to this
window are sent to the program running on the Cortex-M.
The TERM.METHOD command selects which method is used for the communication.
The Cortex-M does not have a Debug Communication Channel (DCC) as other Cortex cores but even better
its system memory can be accessed by the debugger during run time. Therefore you can e.g. reserve a
single memory byte for input data and one for output data somewhere in the system memory. The following
command tells the debugger the addresses of the reserved bytes which shall be used for the
communication. You can use address values or symbol names as command parameter:
TERM.METHOD SingleE E:<byte_address_to_debugger> E:<byte_address_from_debugger>
A data value of 0 in the byte buffer indicates an empty byte buffer. This is the way the handshake works. After
data is read a 0 is placed in the buffer to indicate the data is taken and a new byte can be sent.
The TRACE32 demo/arm/etc/terminal directory contains an example of this method.
Alternatively BufferE method could be used which works quite similar but with a bigger buffer to transfer
more than one byte at once.
Semihosting
Semihosting is a technique for an application program running on an ARM processor to communicate with
the host computer of the debugger. This way the application can use the I/O facilities of the host computer
like keyboard input, screen output, and file I/O. This is especially useful if the target platform does not yet
provide these I/O facilities or in order to output additional debug information in printf() style.
Normally semihosting is invoked by code within the C library functions of the ARM RealView compiler like
printf() and scanf(). The application can also invoke the operations used for keyboard input, screen output,
and file I/O directly. The operations are described in the RealView Compilation Tools Developer Guide from
ARM in the chapter Semihosting Operations.
Cortex-M Debugger
16

+"
! "

( "
,-

.
# /
# $%
& '
&
)*

A semihosting call from the application causes a BKPT exception in the semihosting library function. The
immediate BKPT parameter 0xAB is indicating a semihosting request. The type of operation is passed in
R0. R1 points to the other parameters. The debugger handles the request while the application is stopped,
provides the required communication with the host, and restarts the application.
This mode is enabled by TERM.METHOD ARMSWI and by opening a TERM.GATE window for the
semihosting screen output. The handling of the semihosting requests is only active when the TERM.GATE
window is existing.
TERM.HEAPINFO defines the system stack and heap location. The C library reads these memory
parameters by a SYS_HEAPINFO semihosting call and uses them for initialization.
An code example can be found in demo/arm/etc/semihosting_arm_emulation.
The Cortex-M does not have a Debug Communication Channel (DCC) like other Cortex cores. Therefore
this mode can not be used. Alternatively, to avoid stopping the application, the BufferE method can be used.
Then the semihosting requests are processed via a buffer located in the system memory which can be
accessed by the debugger without stopping the core. There is an example in demo/arm/etc/
semihosting_trace32_dcc which uses the TRACE32 proprietary semihosting functions. And there is an
example in demo/arm/etc/semihosting_arm_syscalls which allow to use the ARM semihosting library
functions with BufferE method.
Cortex-M Debugger
17
Runtime Measurement
The command RunTime allows run time measurement based on polling the core run status by software.
Therefore the result will be about few milliseconds higher than the real value.
If the signal DBGACK on the JTAG connector is available, the measurement will automatically be based on
this hardware signal which delivers very exact results.
Cortex-M Debugger
18
Memory Classes
The following memory classes are available.
Memory Class
Description
Data Memory
Program Memory
SD
Supervisor Data Memory (privileged access)
UD
User Data Memory (non-privileged access)
SP
Supervisor Program Memory (privileged access)
UP
User Program Memory (non-privileged access)
ST
Supervisor Thumb Memory (privileged access)
UT
User Thumb Memory (non-privileged access)
Thumb Memory
User Memory (non-privileged access)
Supervisor Memory (privileged access)
VM
Virtual Memory (memory on the debug system)
USR
Access to Special Memory via User Defined Access Routines
DAP
Memory access via Debug Access Port (CoreSight, Cortex). The access
port specified by SYStem.CONFIG DEBUGACCESSPORT is used which
is typically the APB-AP.

(see SYStem.CpuAccess and SYStem.MemAccess)
D, P, SD, UD, SP, UP, ST, UT, T, U, S or no class at all accesses the memory through the MEM-AP AHB via
DAP (Debug Access Port) when the core is in debug mode (= halted).
The memory class E allows access through alternative access paths which are defined by
SYStem.MemAccess when the core is not in debug mode (= running). The DAP can access the memory
through MEM-AP AHB even when the core is running. Therefore this will normally be the best selection for
SYStem.MemAccess.
If you want to see memory or peripheral registers independent if the core is running or not, you can use
SYStem.Option DUALPORT ON together with SYStem.MemAccess DAP. Then all windows showing
memory will be handled as if you have opened them with the E memory class.
Cortex-M Debugger
19
The virtual memory VM is a memory provided by the debugger (memory on the host). It can not be
accessed by the core.
Cortex-M Debugger
20
Cortex-M specific Onchip Commands
Onchip.Mode RAMPRIV
Format:
SRAM privilege access
Onchip.Mode RAMPRIV [ON | OFF]
Enable SRAM privilege access.
Onchip.Mode SFRWPRIV
Format:
Special function register write access
Onchip.Mode SFRWPRIV [ON | OFF]
Enable privilege write access to the Special Function Register.
Onchip.Mode TSTARTEN
Format:
Enable TSTART signal
Onchip.Mode TSTARTEN [ON | OFF]
Enables the external control of the trace by the TSTART signal. If set to ON and the TSTART signal is set
HIGH, then the trace gets starts recording.
Onchip.Mode TSTOPEN
Format:
Enable TSTOP signal
Onchip.Mode TSTOPEN [ON | OFF]
Enables the external control of the trace by the TSTOP signal. If set to ON and the TSTOP signal is set
HIGH, then the trace stops recording.
Cortex-M Debugger
21
Onchip.TBADDRESS
Format:
Base address of the trace buffer
Onchip.TBADDRESS <address>
Setup the base address of the trace buffer inside the internal SRAM. The part of the SRAM must not be
used by the target application as long as the trace is used.
Cortex-M Debugger
22
Cortex-M specific SYStem Commands
SYStem.BdmClock
Obsolete command syntax. It has the same effect as SYStem.JtagClock. Use SYStem.JtagClock instead.
SYStem.CLOCK
Format:
Inform debugger about core clock
SYStem.CLOCK <freq>
The command informs the debugger about the core clock frequency. The information is used for
analysis functions where the core frequency needs to be known. This command is only available if the
debugger is used as front end for virtual prototyping.
SYStem.CONFIG
Configure debugger according to target topology
Format:
SYStem.CONFIG <parameter>
SYStem.MultiCore <parameter> (deprecated syntax)
<parameter>:
(General)
state
Cortex-M Debugger
23
<parameter>:
(Debugport)
CJTAGFLAGS <flags>
CJTAGTCA <value>
CONNECTOR [MIPI34 | MIPI20T]
CORE <core> <chip>
CoreNumber <number>
DEBUGPORT [DebugCable0 | DebugCableA | DebugCableB]
DEBUGPORTTYPE [JTAG | SWD | CJTAG | CJTAGSWD]
NIDNTTRSTTORST [ON | OFF]
NIDNTPSRISINGEDGE [ON | OFF]
NIDNTRSTPOLARITY [High | Low]
PortSHaRing [ON | OFF | Auto]
Slave [ON | OFF]
SWDP [ON | OFF]
SWDPIDLEHIGH [ON | OFF]
SWDPTargetSel <value>
TriState [ON | OFF]
<parameter>:
(JTAG)
CHIPDRLENGTH <bits>
CHIPDRPATTERN [Standard | Alternate <pattern>]
CHIPDRPOST <bits>
CHIPDRPRE <bits>
CHIPIRLENGTH <bits>
CHIPIRPATTERN [Standard | Alternate <pattern>]
CHIPIRPOST<bits>
CHIPIRPRE <bits>
DAP2DRPOST <bits>
DAP2DRPRE <bits>
<parameter>:
(JTAG contd)
DAP2IRPOST <bits>
DAP2IRPRE <bits>
DAPDRPOST <bits>
DAPDRPRE <bits>
DAPIRPOST <bits>
DAPIRPRE <bits>
DRPOST <bits>
DRPRE <bits>
ETBDRPOST <bits>
ETBDRPRE <bits>
ETBIRPOST <bits>
ETBIRPRE <bits>
IRPOST<bits>
IRPRE <bits>
Cortex-M Debugger
24
<parameter>:
(JTAG contd)
NEXTDRPOST <bits>
NEXTDRPRE <bits>
NEXTIRPOST<bits>
NEXTIRPRE <bits>
RTPDRPOST <bits>
RTPDRPRE <bits>
RTPIRPOST <bits>
RTPIRPRE <bits>
Slave [ON | OFF]
TAPState <state>
TCKLevel <level>
TriState [ON | OFF]
<parameter>:
(Multitap)
CFGCONNECT <code>
DAP2TAP <tap>
DAPTAP <tap>
DEBUGTAP <tap>
ETBTAP <tap>
MULTITAP [NONE | IcepickA | IcepickB | IcepickC | IcepickD | IcepickBB |
IcepickBC | IcepickCC | IcepickDD | STCLTAP1 | STCLTAP2 |
STCLTAP3 |
MSMTAP <irlength> <irvalue> <drlength> <drvalue>]
NJCR <tap>
RTPTAP <tap>
SLAVETAP <tap>
<parameter>:
(DAP)
AHBACCESSPORT <port>
APBACCESSPORT <port>
AXIACCESSPORT <port>
COREJTAGPORT <port>
DAP2AHBACCESSPORT <port>
DAP2APBACCESSPORT <port>
DAP2AXIACCESSPORT <port>
DAP2COREJTAGPORT <port>
DAP2DEBUGACCESSPORT <port>
DAP2JTAGPORT <port>
DAP2AHBACCESSPORT <port>
DEBUGACCESSPORT <port>
JTAGACCESSPORT <port>
MEMORYACCESSPORT <port>
Cortex-M Debugger
25
<parameter>:
(Components)
ADTF.Base <address>
ADTF.RESET
AET.Base <address>
AET.RESET
BMC.Base <address>
BMC.RESET
CMI.Base <address>
CMI.RESET
CMI.TraceID <id>
COREDEBUG.Base <address>
COREDEBUG.RESET
CTI.Base <address>
CTI.Config [NONE | ARMV1 | ARMPostInit | OMAP3 | TMS570 | CortexV1 |
QV1]
CTI.RESET
DRM.Base <address>
DRM.RESET
Cortex-M Debugger
26
DTM.RESET
DTM.Type [None | Generic]
DWT.Base <address>
DWT.RESET
EPM.Base <address>
EPM.RESET
ETB2AXI.Base <address>
ETB2AXI.RESET
ETB.ATBSource <source>
ETB.Base <address>
ETB.RESET
ETB.Size <size>
ETF.ATBSource <source>
ETF.Base <address>
ETF.RESET
ETM.Base <address>
ETM.RESET
ETR.ATBSource <source>
ETR.Base <address>
ETR.RESET
FUNNEL.ATBSource <sourcelist>
FUNNEL.Base <address>
FUNNEL.Name <string>
FUNNEL.RESET
HSM.Base <address>
HSM.RESET
HTM.Base <address>
HTM.RESET
ICE.Base <address>
ICE.RESET
ITM.Base <address>
ITM.RESET
OCP.Base <address>
OCP.RESET
OCP.TraceID <id>
OCP.Type <type>
PMI.Base <address>
PMI.RESET
PMI.TraceID <id>
RTP.Base <address>
RTP.PerBase <address>
RTP.RamBase <address>
RTP.RESET
SC.Base <address>
SC.RESET
SC.TraceID <id>
STM.Base <address>
STM.Mode [NONE | XTIv2 | SDTI | STP | STP64 | STPv2]
STM.RESET
STM.Type [None | Generic | ARM | SDTI | TI]
TPIU.ATBSource <source>
Cortex-M Debugger
27
TPIU.Base <address>
TPIU.RESET
TPIU.Type [CoreSight | Generic]
<parameter>:
(Deprecated)
BMCBASE <address>
BYPASS <seq>
COREBASE <address>
CTIBASE <address>
CTICONFIG [NONE | ARMV1 | ARMPostInit | OMAP3 | TMS570 | CortexV1 |
QV1]
DEBUGBASE <address>
DTMCONFIG [ON | OFF]
DTMETBFUNNELPORT <port>
DTMFUNNEL2PORT <port>
DTMFUNNELPORT <port>
DTMTPIUFUNNELPORT <port>
DWTBASE <address>
ETB2AXIBASE <address>
ETBBASE <address>
ETBFUNNELBASE <address>
ETFBASE <address>
ETMBASE <address>
ETMETBFUNNELPORT <port>
ETMFUNNEL2PORT <port>
ETMFUNNELPORT <port>
ETMTPIUFUNNELPORT <port>
FILLDRZERO [ON | OFF]
FUNNEL2BASE <address>
FUNNELBASE <address>
HSMBASE <address>
HTMBASE <address>
HTMETBFUNNELPORT <port>
HTMFUNNEL2PORT <port>
HTMFUNNELPORT <port>
HTMTPIUFUNNELPORT <port>
ITMBASE <address>
ITMETBFUNNELPORT <port>
ITMFUNNEL2PORT <port>
ITMFUNNELPORT <port>
ITMTPIUFUNNELPORT <port>
PERBASE <address>
RAMBASE <address>
RTPBASE <address>
SDTIBASE <address>
STMBASE <address>
STMETBFUNNELPORT<port>
STMFUNNEL2PORT<port>
STMFUNNELPORT<port>
STMTPIUFUNNELPORT<port>
TIADTFBASE <address>
TIDRMBASE <address>
Cortex-M Debugger
28
TIEPMBASE <address>
TIICEBASE <address>
TIOCPBASE <address>
TIOCPTYPE <type>
TIPMIBASE <address>
TISCBASE <address>
TISTMBASE <address>
TPIUBASE <address>
TPIUFUNNELBASE <address>
TRACEETBFUNNELPORT <port>
TRACEFUNNELPORT<port>
TRACETPIUFUNNELPORT <port>
view
The SYStem.CONFIG commands inform the debugger about the available on-chip debug and trace
components and how to access them.
This is a common description of the SYStem.CONFIG command group for the ARM, CevaX, TI DSP and
Hexagon debugger. Each debugger will provide only a subset of these commands. Some commands need
a certain CPU type selection (SYStem.CPU <type>) to become active and it might additionally depend on
further settings.
Ideally you can select with SYStem.CPU the chip you are using which causes all setup you need and you do
not need any further SYStem.CONFIG command.
The SYStem.CONFIG command information shall be provided after the SYStem.CPU command which
might be a precondition to enter certain SYStem.CONFIG commands and before you start up the debug
session e.g. by SYStem.Up.
Syntax remarks:
The commands are not case sensitive. Capital letters show how the command can be shortened.
Example: SYStem.CONFIG.DWT.Base 0x1000 -> SYS.CONFIG.DWT.B 0x1000
The dots after SYStem.CONFIG can alternatively be a blank.
Example: SYStem.CONFIG.DWT.Base 0x1000 or SYStem.CONFIG DWT Base 0x1000.
<parameter> General
state
Opens a window showing most of the SYStem.CONFIG settings

and allows to modify them.
Cortex-M Debugger
29
<parameter> describing the Debugport
CJTAGFLAGS <flags>
Activates bug fixes for cJTAG implementations.

Bit 0: Disable scanning of cJTAG ID.
Bit 1: Target has no keeper.
Bit 2: Inverted meaning of SREDGE register.
Bit 3: Old command opcodes.
Bit 4: Unlock cJTAG via APFC register.
Default: 0
CJTAGTCA <value>
Selects the TCA (TAP Controller Address) to address a device in a

cJTAG Star-2 configuration. The Star-2 configuration requires a
unique TCA for each device on the debug port.
CONNECTOR
[MIPI34 | MIPI20T]
Specifies the connector MIPI34 or MIPI20T on the target. This

is mainly needed in order to notify the trace pin location.
Default: MIPI34 if CombiProbe is used.
Cortex-M Debugger
30
CORE <core> <chip>
The command helps to identify debug and trace resources which

are commonly used by different cores. The command might be
required in a multicore environment if you use multiple debugger
instances (multiple TRACE32 GUIs) to simultaneously debug
different cores on the same target system.
Because of the default setting of this command
debugger#1: <core>=1 <chip>=1
...
each debugger instance assumes that all notified debug and trace
resources can exclusively be used.
But some target systems have shared resources for different
cores. For example a common trace port. The default setting
causes that each debugger instance will control the (same) trace
port. Sometimes it does not hurt if such a module will be controlled
twice. So even then it might work. But the correct specification
which might be a must is to tell the debugger that these cores
sharing resources are on the same <chip>. Whereby the chip
does not need to be identical with the device on your target board:
For cores on the same <chip> the debugger assumes they share
the same resource if the control registers of the resource has the
same address.
Default:
<core> depends on CPU selection, usually 1.
<chip> derives from CORE= parameter in the configuration file
(config.t32), usually 1. If you start multiple debugger instances with
the help of t32start.exe you will get ascending values (1, 2, 3,...).
CoreNumber <number>
Number of cores considered in an SMP (symmetric

multiprocessing) debug session. There are core types like
ARM11MPCore, CortexA5MPCore, CortexA9MPCore and
Scorpion which can be used as a single core processor or as a
scalable multicore processor of the same type. If you intend to
debug more than one such core in an SMP debug session you
need to specify the number of cores you intend to debug.
Default: 1.
DEBUGPORT
[DebugCable0 | DebugCableA | DebugCableB]
It specifies which probe cable shall be used e.g. DebugCableA or

DebugCableB. At the moment only the CombiProbe allows to
connect more than one probe cable.
Default: depends on detection.
Cortex-M Debugger
31
DEBUGPORTTYPE
[JTAG | SWD | CJTAG |
CJTAGSWD]
It specifies the used debug port type JTAG, SWD, CJTAG,

CJTAG-SWD. It assumes the selected type is supported by the
target.
Default: JTAG.
What is NIDnT?
NIDnT is an acronym for Narrow Interface for Debug and Test.
NIDnT is a standard from the MIPI Alliance, which defines how to
reuse the pins of an existing interface (like for example a microSD
card interface) as a debug and test interface.
To support the NIDnT standard in different implementations,
TRACE32 has several special options:
NIDNTPSRISINGEDGE
[ON | OFF]
Send data on rising edge for NIDnT PS switching.

NIDnT specifies how to switch, for example, the microSD card
interface to a debug interface by sending in a special bit sequence
via two pins of the microSD card.
TRACE32 will send the bits of the sequence incident to the falling
edge of the clock, because TRACE32 expects that the target
samples the bits on the rising edge of the clock.
Some targets will sample the bits on the falling edge of the clock
instead. To support such targets, you can configure TRACE32 to
send bits on the rising edge of the clock by using
SYStem.CONFIG NIDNTPSRISINGEDGE ON
NOTE: Only enable this option right before you send the NIDnT
switching bit sequence.
Make sure to DISABLE this option, before you try to connect to the
target system with for example SYStem.Up.
NIDNTRSTPOLARITY
[High | Low]
Usually TRACE32 requires that the system reset line of a target

system is low active and has a pull-up on the target system.
When connecting via NIDnT to a target system, the reset line
might be a high-active signal.
To configure TRACE32 to use a high-active reset signal, use
SYStem.CONFIG NIDNTRSTPOLARITY High
This option must be used together with
SYStem.CONFIG NIDNTTRSTTORST ON
because you also have to use the TRST signal of an ARM debug
cable as reset signal for NIDnT in this case.
Cortex-M Debugger
32
NIDNTTRSTTORST
[ON | OFF]
Usually TRACE32 requires that the system reset line of a target

system is low active and has a pull-up on the target system.
This is how the system reset line is usually implemented on regular
ARM-based targets.
When connecting via NIDnT (e.g. a microSD card slot) to the
target system, the reset line might not include a pull-up on the
target system.
To circumvent problems, TRACE32 allows to drive the target reset
line via the TRST signal of an ARM debug cable.
Enable this option if you want to use the TRST signal of an ARM
debug cable as reset signal for a NIDnT.
PortSHaRing [ON | OFF |

Auto]
Configure if the debug port is shared with another tool, e.g. an

ETAS ETK.
OFF: Default. Communicate with the target without sending
requests.
ON: Request for access to the debug port and wait until the access
is granted before communicating with the target.
Auto: Automatically detect a connected tool on next
SYStem.Mode Up, SYStem.Mode Attach or SYStem.Mode Go. If
a tool is detected switch to mode ON else switch to mode OFF.
The current setting can be obtained by the PORTSHARING()
function, immediate detection can be performed using
SYStem.DETECT PortSHaRing.
Slave [ON | OFF]
If several debuggers share the same debug port, all except one
must have this option active.
JTAG: Only one debugger - the master - is allowed to control the
signals nTRST and nSRST (nRESET). The other debugger need
to have Slave=OFF.
Default: OFF; ON if CORE=... >1 in config file (e.g. config.t32).
SWDP [ON | OFF]
With this command you can change from the normal JTAG
interface to the serial wire debug mode. SWDP (Serial Wire Debug
Port) uses just two signals instead of five. It is required that the
target and the debugger hard- and software supports this
interface.
Default: OFF.
Cortex-M Debugger
33
SWDPIdleHigh
[ON | OFF]
Keep SWDIO line high when idle. Only for Serialwire Debug mode.
Usually the debugger will pull the SWDIO data line low, when no
operation is in progress, so while the clock on the SWCLK line is
stopped (kept low).
You can configure the debugger to pull the SWDIO data line
high, when no operation is in progress by using
SYStem.CONFIG SWDPIDLEHIGH ON
Default: OFF.
SWDPTargetSel <value>
Device address in case of a multidrop serial wire debug port.

Default: 0.
TriState [ON | OFF]
TriState has to be used if several debug cables are connected to a

common JTAG port. TAPState and TCKLevel define the TAP state
and TCK level which is selected when the debugger switches to
tristate mode. Please note: nTRST must have a pull-up resistor on the
target, TCK can have a pull-up or pull-down resistor, other trigger
inputs needs to be kept in inactive state.
Default: OFF.
Cortex-M Debugger
34
<parameter> describing the JTAG scan chain and signal behavior

With the JTAG interface you can access a Test Access Port controller (TAP) which has implemented a state
machine to provide a mechanism to read and write data to an Instruction Register (IR) and a Data Register
(DR) in the TAP. The JTAG interface will be controlled by 5 signals: nTRST(reset), TCK (clock), TMS (state
machine control), TDI (data input), TDO (data output). Multiple TAPs can be controlled by one JTAG
interface by daisy-chaining the TAPs (serial connection). If you want to talk to one TAP in the chain you need
to send a BYPASS pattern (all ones) to all other TAPs. For this case the debugger needs to know the
position of the TAP he wants to talk to which can be notified with the first four commands in the table below.
... DRPOST <bits>
Defines the TAP position in a JTAG scan chain. Number of TAPs

in the JTAG chain between the TDI signal and the TAP you are
describing. In BYPASS mode each TAP contributes one data
register bit. See possible TAP types and example below.
Default: 0.
... DRPRE <bits>
Defines the TAP position in a JTAG scan chain. Number of TAPs

in the JTAG chain between the TAP you are describing and the
TDO signal. In BYPASS mode each TAP contributes one data
register bit. See possible TAP types and example below.
Default: 0.
... IRPOST <bits>
Defines the TAP position in a JTAG scan chain. Number of

Instruction Register (IR) bits of all TAPs in the JTAG chain
between TDI signal and the TAP you are describing. See
possible TAP types and example below.
Default: 0.
... IRPRE <bits>
Defines the TAP position in a JTAG scan chain. Number of

Instruction Register (IR) bits of all TAPs in the JTAG chain
between the TAP you are describing and the TDO signal. See
possible TAP types and example below.
Default: 0.
CHIPDRLENGTH <bits>
Number of Data Register (DR) bits which needs to get a certain

BYPASS pattern.
CHIPDRPATTERN [Standard | Alternate <pattern>]
Data Register (DR) pattern which shall be used for BYPASS

instead of the standard (1...1) pattern.
CHIPIRLENGTH <bits>
Number of Instruction Register (IR) bits which needs to get a

certain BYPASS pattern.
CHIPIRPATTERN [Standard
| Alternate <pattern>]
Instruction Register (IR) pattern which shall be used for BYPASS

instead of the standard pattern.
Cortex-M Debugger
35
Slave [ON | OFF]
If several debugger share the same debug port, all except one
must have this option active.
JTAG: Only one debugger - the master - is allowed to control
the signals nTRST and nSRST (nRESET). The other debugger
need to have Slave=OFF.
Default: OFF; ON if CORE=... >1 in config file (e.g. config.t32).
For CortexM: Please check also
SYStem.Option DISableSOFTRES [ON | OFF]
TAPState <state>
This is the state of the TAP controller when the debugger

switches to tristate mode. All states of the JTAG TAP controller
are selectable.
0 Exit2-DR
1 Exit1-DR
2 Shift-DR
3 Pause-DR
4 Select-IR-Scan
5 Update-DR
6 Capture-DR
7 Select-DR-Scan
8 Exit2-IR
9 Exit1-IR
10 Shift-IR
11 Pause-IR
12 Run-Test/Idle
13 Update-IR
14 Capture-IR
15 Test-Logic-Reset
Default: 7 = Select-DR-Scan.
TCKLevel <level>
Level of TCK signal when all debuggers are tristated. Normally

defined by a pull-up or pull-down resistor on the target.
Default: 0.
TriState [ON | OFF]
TriState has to be used if several debug cables are connected to a

common JTAG port. TAPState and TCKLevel define the TAP state
and TCK level which is selected when the debugger switches to
tristate mode. Please note: nTRST must have a pull-up resistor on
the target, TCK can have a pull-up or pull-down resistor, other
trigger inputs needs to be kept in inactive state.
Default: OFF.
Cortex-M Debugger
36
TAP types:
Core TAP providing access to the debug register of the core you intend to debug.
-> DRPOST, DRPRE, IRPOST, IRPRE.
DAP (Debug Access Port) TAP providing access to the debug register of the core you intend to debug. It
might be needed additionally to a Core TAP if the DAP is only used to access memory and not to access the
core debug register.
-> DAPDRPOST, DAPDRPRE, DAPIRPOST, DAPIRPRE.
DAP2 (Debug Access Port) TAP in case you need to access a second DAP to reach other memory
locations.
-> DAP2DRPOST, DAP2DRPRE, DAP2IRPOST, DAP2IRPRE.
ETB (Embedded Trace Buffer) TAP if the ETB has an own TAP to access its control register (typical with
ARM11 cores).
-> ETBDRPOST, ETBDRPRE, ETBIRPOST, ETBIRPRE.
NEXT: If a memory access changes the JTAG chain and the core TAP position then you can specify the new
values with the NEXT... parameter. After the access for example the parameter NEXTIRPRE will replace the
IRPRE value and NEXTIRPRE becomes 0. Available only on ARM11 debugger.
-> NEXTDRPOST, NEXTDRPRE, NEXTIRPOST, NEXTIRPRE.
RTP (RAM Trace Port) TAP if the RTP has an own TAP to access its control register.
-> RTPDRPOST, RTPDRPRE, RTPIRPOST, RTPIRPRE.
CHIP: Definition of a TAP or TAP sequence in a scan chain that needs a different Instruction Register
(IR) and Data Register (DR) pattern than the default BYPASS (1...1) pattern.
-> CHIPDRPOST, CHIPDRPRE, CHIPIRPOST, CHIPIRPRE.
Example:
TDI
ARM11 TAP
ETB TAP
OfNoInterest TAP
DAP TAP
IR: 5bit
IR: 4bit
IR: 7bit
IR: 4bit
SYStem.CONFIG
SYStem.CONFIG
SYStem.CONFIG
SYStem.CONFIG
SYStem.CONFIG
SYStem.CONFIG
SYStem.CONFIG
SYStem.CONFIG
TDO
IRPRE 15.
DRPRE 3.
DAPIRPOST 16.
DAPDRPOST 3.
ETBIRPOST 5.
ETBDRPOST 1.
ETBIRPRE 11.
ETBDRPRE 2.
Cortex-M Debugger
37
Cortex-M Debugger
38
<parameter> describing a system level TAP Multitap

A Multitap is a system level or chip level test access port (TAP) in a JTAG scan chain. It can for example
provide functions to re-configure the JTAG chain or view and control power, clock, reset and security of
different chip components.
At the moment the debugger supports three types and its different versions:
Icepickx, STCLTAPx, MSMTAP:
Example:
JTAG
TDI
Multitap
IcepickC
ARM11
TAP
DAP
TAP
ETB
TAP
TDO
MULTITAP
DEBUGTAP
DAPTAP
ETBTAB
TMS
TCK
IcepickC
1
4
5
nTRST
CFGCONNECT <code>
The <code> is a hexadecimal number which defines the JTAG

scan chain configuration. You need the chip documentation to
figure out the suitable code. In most cases the chip specific
default value can be used for the debug session.
Used if MULTITAP=STCLTAPx.
DAPTAP <tap>
Specifies the TAP number which needs to be activated to get the

DAP TAP in the JTAG chain.
Used if MULTITAP=Icepickx.
DAP2TAP <tap>
Specifies the TAP number which needs to be activated to get a

2nd DAP TAP in the JTAG chain.
Cortex-M Debugger
39
DEBUGTAP <tap>

core TAP in the JTAG chain. E.g. ARM11 TAP if you intend to
debug an ARM11.
ETBTAP <tap>

ETB TAP in the JTAG chain.
Used if MULTITAP=Icepickx. ETB = Embedded Trace Buffer.
MULTITAP
[NONE | IcepickA | IcepickB
| IcepickC | IcepickD |
IcepickBB | IcepickBC |
IcepickCC | IcepickDD |
STCLTAP1 | STCLTAP2 |
STCLTAP3 | MSMTAP
<irlength> <irvalue>
<drlength> <drvalue>]
Selects the type and version of the MULTITAP.
NJCR <tap>
Number of a Non-JTAG Control Register (NJCR) which shall be

used by the debugger.
In case of MSMTAP you need to add parameters which specify

which IR pattern and DR pattern needed to be shifted by the
debugger to initialize the MSMTAP. Please note some of these
parameters need a decimal input (dot at the end).
IcepickXY means that there is an Icepick version X which
includes a subsystem with an Icepick of version Y.
RTPTAP <tap>

RTP TAP in the JTAG chain.
Used if MULTITAP=Icepickx. RTP = RAM Trace Port.
SLAVETAP <tap>
Specifies the TAP number to get the Icepick of the sub-system in

the JTAG scan chain.
Used if MULTITAP=IcepickXY (two Icepicks).
Cortex-M Debugger
40
<parameter> configuring a CoreSight Debug Access Port DAP

A Debug Access Port (DAP) is a CoreSight module from ARM which provides access via its debugport
(JTAG, cJTAG, SWD) to:
1. Different memory busses (AHB, APB, AXI). This is especially important if the on-chip debug register
needs to be accessed this way. You can access the memory buses by using certain access classes with the
debugger commands: AHB:, APB:, AXI:, DAP, E:. The interface to these buses is called Memory
Access Port (MEM-AP).
2. Other, chip-internal JTAG interfaces. This is especially important if the core you intend to debug is
connected to such an internal JTAG interface. The module controlling these JTAG interfaces is called JTAG
Access Port (JTAG-AP). Each JTAG-AP can control up to 8 internal JTAG interfaces. A port number between
0 and 7 denotes the JTAG interfaces to be addressed.
3. At emulation or simulation system with using bus transactors the access to the busses must be specified
by using the transactor identification name instead using the access port commands. For emulations/
simulations with a DAP transactor the individual bus transactor name dont need to be configured. Instead of
this the DAP transactor name need to be passed and the regular access ports to the busses.
Cortex-M Debugger
41
Debug Access Port (DAP)
Debugger
0 Memory Access Port

(MEM-AP)
Debug Port
JTAG or
cJTAG or
SWD
System Memory
Debug Bus (APB)
Chip
System Bus (AHB)
Example:
Debug Register
Trace Register
1 Memory Access Port

(MEM-AP)
ROM Table
0 JTAG
2 JTAG Access Port
(JTAG-AP)
7 JTAG
AHBACCESSPORT 0
MEMORYACCESSPORT 0
APBACCESSPORT 1
DEBUGACCESSPORT 1
JTAGACCESSPORT 2
ARM9
COREJTAGPORT 7
AHBACCESSPORT <port>
DAP access port number (0-255) which shall be used for AHB:
access class. Default: <port>=0.
APBACCESSPORT <port>
DAP access port number (0-255) which shall be used for APB:
access class. Default: <port>=1.
AXIACCESSPORT <port>
DAP access port number (0-255) which shall be used for AXI:
access class. Default: port not available
COREJTAGPORT <port>
JTAG-AP port number (0-7) connected to the core which shall be

debugged.
Cortex-M Debugger
42
DAP2AHBACCESSPORT
<port>
DAP2 access port number (0-255) which shall be used for

AHB2: access class. Default: <port>=0.
DAP2APBACCESSPORT
<port>

APB2: access class. Default: <port>=1.
DAP2AXIACCESSPORT
<port>

AXI2: access class. Default: port not available
DAP2DEBUGACCESSPORT <port>
DAP2 access port number (0-255) where the debug register can
be found (typically on APB). Used for DAP2: access class.
Default: <port>=1.
DAP2COREJTAGPORT
<port>
JTAG-AP port number (0-7) connected to the core which shall be

debugged. The JTAG-AP can be found on another DAP (DAP2).
DAP2JTAGPORT <port>
JTAG-AP port number (0-7) for an (other) DAP which is

connected to a JTAG-AP.
DAP2MEMORYACCESSPORT <port>
DAP2 access port number where system memory can be

accessed even during runtime (typically on AHB). Used for E:
access class while running, assuming SYStem.MemoryAccess
DAP2. Default: <port>=0.
DEBUGACCESSPORT
<port>
DAP access port number (0-255) where the debug register can
be found (typically on APB). Used for DAP: access class.
Default: <port>=1.
JTAGACCESSPORT <port>
DAP access port number (0-255) of the JTAG Access Port.
MEMORYACCESSPORT
<port>
DAP access port number where system memory can be

accessed even during runtime (typically on AHB). Used for E:
DAP. Default: <port>=0.
AHBNAME <name>
AHB bus transactor name that shall be used for AHB: access
class.
APBNAME <name>
APB bus transactor name that shall be used for APB: access
class.
AXINAME <name>
AXI bus transactor name that shall be used for AXI: access
class.
DAP2AHBNAME <name>
AHB bus transactor name that shall be used for AHB2: access
class.
Cortex-M Debugger
43
DAP2APBNAME <name>
APB bus transactor name that shall be used for APB2: access
class.
DAP2AXINAME <name>
AXI bus transactor name that shall be used for AXI2: access
class.
DAP2DEBUGBUSNAME
<name>
APB bus transactor name identifying the bus where the debug
register can be found. Used for DAP2: access class.
DAP2MEMORYBUSNAME
<name>
AHB bus transactor name identifying the bus where system

memory can be accessed even during runtime. Used for E:
DAP2.
DEBUGBUSNAME <name>
APB bus transactor name identifying the bus where the debug
register can be found. Used for DAP: access class.
MEMORYBUSNAME
<name>
AHB bus transactor name identifying the bus where system

memory can be accessed even during runtime. Used for E:
DAP.
DAPNAME <name>
DAP transactor name that shall be used for DAP access ports.
DAP2NAME <name>
DAP transactor name that shall be used for DAP access ports of
2nd order.
Cortex-M Debugger
44
<parameter> describing debug and trace Components

In the Components folder in the SYStem.CONFIG.state window you can comfortably add the debug and
trace components your chip includes and which you intend to use with the debuggers help.
Each configuration can be done by a command in a script file as well. Then you do not need to enter
everything again on the next debug session. If you press the button with the three dots you get the
corresponding command in the command line where you can view and maybe copy it into a script file.
Cortex-M Debugger
45
You can have several of the following components: CMI, ETB, ETF, ETR, FUNNEL, STM.
Example: FUNNEL1, FUNNEL2, FUNNEL3,...
The <address> parameter can be just an address (e.g. 0x80001000) or you can add the access class in
front (e.g. AHB:0x80001000). Without access class it gets the command specific default access class which
is EDAP: in most cases.
Example:
Core
ETM
Core
ETM
0
1
FUNNEL
0
FUNNEL
STM
TPIU
SYStem.CONFIG.COREDEBUG.Base 0x80010000 0x80012000

SYStem.CONFIG.BMC.Base 0x80011000 0x80013000
SYStem.CONFIG.ETM.Base 0x8001c000 0x8001d000
SYStem.CONFIG.STM1.Base EAHB:0x20008000
SYStem.CONFIG.STM1.Type ARM
SYStem.CONFIG.STM1.Mode STPv2
SYStem.CONFIG.FUNNEL1.Base 0x80004000
SYStem.CONFIG.FUNNEL2.Base 0x80005000
SYStem.CONFIG.TPIU.Base 0x80003000
SYStem.CONFIG.FUNNEL1.ATBSource ETM.0 0 ETM.1 1
SYStem.CONFIG.FUNNEL2.ATBSource FUNNEL1 0 STM1 7
SYStem.CONFIG.TPIU.ATBSource FUNNEL2
Cortex-M Debugger
46
... .ATBSource <source>
Specify for components collecting trace information from where the

trace data are coming from. This way you inform the debugger
about the interconnection of different trace components on a
common trace bus.
You need to specify the ... .Base <address> or other attributes
that define the amount of existing peripheral modules before you
can describe the interconnection by ... .ATBSource <source>.
A CoreSight trace FUNNEL has eight input ports (port 0-7) to
combine the data of various trace sources to a common trace
stream. Therefore you can enter instead of a single source a list
of sources and input port numbers.
Example:
SYStem.CONFIG FUNNEL.ATBSource ETM 0 HTM 1 STM 7
Meaning: The funnel gets trace data from ETM on port 0, from
HTM on port 1 and from STM on port 7.
In an SMP (Symmetric MultiProcessing) debug session where
you used a list of base addresses to specify one component per
core you need to indicate which component in the list is meant:
Cortex-M Debugger
47
Example: Four cores with ETM modules.

SYStem.CONFIG ETM.Base 0x1000 0x2000 0x3000 0x4000
SYStem.CONFIG FUNNEL1.ATBSource ETM.0 0 ETM.1 1
ETM.2 2 ETM.3 3
"...2" of "ETM.2" indicates it is the third ETM module which has
the base address 0x3000. The indices of a list are 0, 1, 2, 3,...
If the numbering is accelerating, starting from 0, without gaps,
like the example above then you can shorten it to
SYStem.CONFIG FUNNEL1.ATBSource ETM
Example: Four cores, each having an ETM module and an ETB
module.
SYStem.CONFIG ETM.Base 0x1000 0x2000 0x3000 0x4000
SYStem.CONFIG ETB.Base 0x5000 0x6000 0x7000 0x8000
SYStem.CONFIG ETB.ATBSource ETM.2 2
The third "ETM.2" module is connected to the third ETB. The last
"2" in the command above is the index for the ETB. It is not a port
number which exists only for FUNNELs.
For a list of possible components including a short description
see Components and available commands.
... .BASE <address>
This command informs the debugger about the start address of

the register block of the component. And this way it notifies the
existence of the component. An on-chip debug and trace
component typically provides a control register block which
needs to be accessed by the debugger to control this
component.
Example: SYStem.CONFIG ETMBASE APB:0x8011c000
Meaning: The control register block of the Embedded Trace
Macrocell (ETM) starts at address 0x8011c000 and is accessible
via APB bus.
In an SMP (Symmetric MultiProcessing) debug session you can
enter for the components BMC, COREBEBUG, CTI, ETB, ETF,
ETM, ETR a list of base addresses to specify one component per
core.
Example assuming four cores: SYStem.CONFIG
COREDEBUG.Base 0x80001000 0x80003000 0x80005000
0x80007000
... .RESET
Undo the configuration for this component. This does not cause a
physical reset for the component on the chip.
Cortex-M Debugger
48
... .TraceID <id>
Identifies from which component the trace packet is coming from.

Components which produce trace information (trace sources) for a
common trace stream have a selectable .TraceID <id>.
If you miss this SYStem.CONFIG command for a certain trace
source (e.g. ETM) then there is a dedicated command group for
this component where you can select the ID (ETM.TraceID <id>).
The default setting is typically fine because the debugger uses
different default TraceIDs for different components.
CTI.Config <type>
Informs about the interconnection of the core Cross Trigger

Interfaces (CTI). Certain ways of interconnection are common
and these are supported by the debugger e.g. to cause a
synchronous halt of multiple cores.
NONE: The CTI is not used by the debugger.
ARMV1: This mode is used for ARM7/9/11 cores which support
synchronous halt, only.
ARMPostInit: Like ARMV1 but the CTI connection differs from the
ARM recommendation.
OMAP3: This mode is not yet used.
TMS570: Used for a certain CTI connection used on a TMS570
derivative.
CortexV1: The CTI will be configured for synchronous start and
stop via CTI. It assumes the connection of DBGRQ, DBGACK,
DBGRESTART signals to CTI are done as recommended by
ARM. The CTIBASE must be notified. CortexV1 is the default
value if a Cortex-R/-A core is selected and the CTIBASE is
notified.
QV1: This mode is not yet used.
ARMV8V1: Channel 0 and 1 of the CTM are used to distribute
start/stop events from and to the CTIs. ARMv8 only.
ARMV8V2: Channel 2 and 3 of the CTM are used to distribute
start/stop events from and to the CTIs. ARMv8 only.
Informs the debugger that a customer proprietary Data Trace

Message (DTM) module is available. This causes the debugger
to consider this source when capturing common trace data.
Trace data from this module will be recorded and can be
accessed later but the unknown DTM module itself will not be
controlled by the debugger.
ETB.Size <size>
Specifies the size of the Embedded Trace Buffer. The ETB size
can normally be read out by the debugger. Therefore this
command is only needed if this can not be done for any reason.
Cortex-M Debugger
49
It is possible that different funnels have the same address for

their control register block. This assumes they are on different
buses and for different cores. In this case it is needed to give the
funnel different names to differentiate them.
OCP.Type <type>
Specifies the type of the OCP module. The <type> is just a

number which you need to figure out in the chip documentation.
PERBASE specifies the base address of the core peripheral

registers which accesses shall be traced. PERBASE is needed
for the RAM Trace Port (RTP) which is available on some
derivatives from Texas Instruments. The trace packages include
only relative addresses to PERBASE and RAMBASE.
RAMBASE is the start address of RAM which accesses shall be

traced. RAMBASE is needed for the RAM Trace Port (RTP)
which is available on some derivatives from Texas Instruments.
The trace packages include only relative addresses to PERBASE
and RAMBASE.
STM.Mode [NONE | XTIv2 |

SDTI | STP | STP64 | STPv2]
Selects the protocol type used by the System Trace Module (STM).
STM.Type [None | Generic |

ARM | SDTI | TI]
Selects the type of the System Trace Module (STM). Some types
allow to work with different protocols (see STM.Mode).
TPIU.Type [CoreSight |
Generic]
Selects the type of the Trace Port Interface Unit (TPIU).

CoreSight: Default. CoreSight TPIU. TPIU control register
located at TPIU.Base <address> will be handled by the
debugger.
Generic: Proprietary TPIU. TPIU control register will not be
handled by the debugger.
Components and available commands
See the description of the commands above. Please note that there is a common description for
... .ATBSource, ... .Base, , ... .RESET, ... .TraceID.
ADTF.Base <address>
ADTF.RESET
AMBA trace bus DSP Trace Formatter (ADTF) - Texas Instruments
Module of a TMS320C5x or TMS320C6x core converting program and data trace information in ARM
CoreSight compliant format.
AET.Base <address>
AET.RESET
Advanced Event Triggering unit (AET) - Texas Instruments
Trace source module of a TMS320C5x or TMS320C6x core delivering program and data trace information.
Cortex-M Debugger
50
BMC.Base <address>
BMC.RESET
Performance Monitor Unit (PMU) - ARM debug module, e.g. on Cortex-A/R
Bench-Mark-Counter (BMC) is the TRACE32 term for the same thing.
The module contains counter which can be programmed to count certain events (e.g. cache hits).
CMI.Base <address>
CMI.RESET
CMI.TraceID <id>
Clock Management Instrumentation (CMI) - Texas Instruments
Trace source delivering information about clock status and events to a system trace module.
COREDEBUG.RESET
Core Debug Register - ARM debug register, e.g. on Cortex-A/R
Some cores do not have a fix location for their debug register used to control the core. In this case it is
essential to specify its location before you can connect by e.g. SYStem.Up.
CTI.Base <address>
CTI.Config [NONE | ARMV1 | ARMPostInit | OMAP3 | TMS570 | CortexV1 | QV1]
CTI.RESET
Cross Trigger Interface (CTI) - ARM CoreSight module
If notified the debugger uses it to synchronously halt (and sometimes also to start) multiple cores.
DRM.Base <address>
DRM.RESET
Debug Resource Manager (DRM) - Texas Instruments
It will be used to prepare chip pins for trace output.
DTM.RESET
Data Trace Module (DTM) - generic, CoreSight compliant trace source module
If specified it will be considered in trace recording and trace data can be accessed afterwards.
DTM module itself will not be controlled by the debugger.
DWT.Base <address>
DWT.RESET
Data Watchpoint and Trace unit (DWT) - ARM debug module on Cortex-M cores
Normally fix address at 0xE0001000 (default).
EPM.Base <address>
EPM.RESET
Emulation Pin Manager (EPM) - Texas Instruments
It will be used to prepare chip pins for trace output.
ETB2AXI.RESET
ETB to AXI module
Similar to an ETR.
Cortex-M Debugger
51
ETB.ATBSource <source>
ETB.Base <address>
ETB.RESET
ETB.Size <size>
Embedded Trace Buffer (ETB) - ARM CoreSight module
Enables trace to be stored in a dedicated SRAM. The trace data will be read out through the debug port after
the capturing has finished.
ETF.ATBSource <source>
ETF.Base <address>
ETF.RESET
Embedded Trace FIFO (ETF) - ARM CoreSight module
On-chip trace buffer used to lower the trace bandwidth peaks.
ETM.Base <address>
ETM.RESET
Embedded Trace Macrocell (ETM) - ARM CoreSight module
Program Trace Macrocell (PTM) - ARM CoreSight module
Trace source providing information about program flow and data accesses of a core.
The ETM commands will be used even for PTM.
ETR.ATBSource <source>
ETR.Base <address>
ETR.RESET
Embedded Trace Router (ETR) - ARM CoreSight module
Enables trace to be routed over an AXI bus to system memory or to any other AXI slave.
FUNNEL.ATBSource <sourcelist>
FUNNEL.Base <address>
FUNNEL.RESET
CoreSight Trace Funnel (CSTF) - ARM CoreSight module
Combines multiple trace sources onto a single trace bus (ATB = AMBA Trace Bus)
HSM.Base <address>
HSM.RESET
Hardware Security Module (HSM) - Infineon
HTM.Base <address>
HTM.RESET
AMBA AHB Trace Macrocell (HTM) - ARM CoreSight module
Trace source delivering trace data of access to an AHB bus.
ICE.Base <address>
ICE.RESET
ICE-Crusher (ICE) - Texas Instruments
ITM.Base <address>
ITM.RESET
Instrumentation Trace Macrocell (ITM) - ARM CoreSight module
Trace source delivering system trace information e.g. sent by software in printf() style.
Cortex-M Debugger
52
OCP.Base <address>
OCP.RESET
OCP.TraceID <id>
OCP.Type <type>
Open Core Protocol watchpoint unit (OCP) - Texas Instruments
Trace source module delivering bus trace information to a system trace module.
PMI.Base <address>
PMI.RESET
PMI.TraceID <id>
Power Management Instrumentation (PMI) - Texas Instruments
Trace source reporting power management events to a system trace module.
RTP.Base <address>
RTP.RESET
RAM Trace Port (RTP) - Texas Instruments
Trace source delivering trace data about memory interface usage.
SC.Base <address>
SC.RESET
SC.TraceID <id>
Statistic Collector (SC) - Texas Instruments
Trace source delivering statistic data about bus traffic to a system trace module.
STM.Base <address>
STM.Mode [NONE | XTIv2 | SDTI | STP | STP64 | STPv2]
STM.RESET
STM.Type [None | Generic | ARM | SDTI | TI]
System Trace Macrocell (STM) - MIPI, ARM CoreSight, others
Trace source delivering system trace information e.g. sent by software in printf() style.
TPIU.ATBSource <source>
TPIU.Base <address>
TPIU.RESET
TPIU.Type [CoreSight | Generic]
Trace Port Interface Unit (TPIU) - ARM CoreSight module
Trace sink sending the trace off-chip on a parallel trace port (chip pins).
Cortex-M Debugger
53
<parameter> which are Deprecated

In the last years the chips and its debug and trace architecture became much more complex. Especially the
CoreSight trace components and their interconnection on a common trace bus required a reform of our
commands. The new commands can deal even with complex structures.
... BASE <address>
This command informs the debugger about the start address of

the register block of the component. And this way it notifies the
existence of the component. An on-chip debug and trace
component typically provides a control register block which
needs to be accessed by the debugger to control this
component.
Example: SYStem.CONFIG ETMBASE APB:0x8011c000
Meaning: The control register block of the Embedded Trace
Macrocell (ETM) starts at address 0x8011c000 and is accessible
via APB bus.
In an SMP (Symmetric MultiProcessing) debug session you can
enter for the components BMC, CORE, CTI, ETB, ETF, ETM, ETR a
list of base addresses to specify one component per core.
Example assuming four cores: SYStem.CONFIG COREBASE
0x80001000 0x80003000 0x80005000 0x80007000.
COREBASE (old syntax: DEBUGBASE): Some cores e.g. CortexA or Cortex-R do not have a fix location for their debug register
which are used for example to halt and start the core. In this case it
is essential to specify its location before you can connect by e.g.
SYStem.UP.
PERBASE and RAMBASE are needed for the RAM Trace Port
(RTP) which is available on some derivatives from Texas
Instruments. PERBASE specifies the base address of the core
peripheral registers which accesses shall be traced, RAMBASE
is the start address of RAM which accesses shall be traced. The
trace packages include only relative addresses to PERBASE and
RAMBASE.
Cortex-M Debugger
54
... PORT <port>
Informs the debugger about which trace source is connected to

which input port of which funnel. A CoreSight trace funnel
provides 8 input ports (port 0-7) to combine the data of various
trace sources to a common trace stream.
Example: SYStem.CONFIG STMFUNNEL2PORT 3
Meaning: The System Trace Module (STM) is connected to input
port #3 on FUNNEL2.
On an SMP debug session some of these commands can have a
list of <port> parameter.
In case there are dedicated funnels for the ETB and the TPIU
their base addresses are specified by ETBFUNNELBASE,
TPIUFUNNELBASE respectively. And the funnel port number for
the ETM are declared by ETMETBFUNNELPORT,
ETMTPIUFUNNELPORT respectively.
TRACE... stands for the ADTF trace source module.
BYPASS <seq>
With this option it is possible to change the JTAG bypass

instruction pattern for other TAPs. It works in a multi-TAP JTAG
chain for the IRPOST pattern, only, and is limited to 64 bit. The
specified pattern (hexadecimal) will be shifted least significant bit
first. If no BYPASS option is used, the default value is 1 for all
bits.
CTICONFIG <type>
Informs about the interconnection of the core Cross Trigger

Interfaces (CTI). Certain ways of interconnection are common
and these are supported by the debugger e.g. to cause a
synchronous halt of multiple cores.
NONE: The CTI is not used by the debugger.
ARMV1: This mode is used for ARM7/9/11 cores which support
synchronous halt, only.
ARMPostInit: Like ARMV1 but the CTI connection differs from the
ARM recommendation.
OMAP3: This mode is not yet used.
TMS570: Used for a certain CTI connection used on a TMS570
derivative.
CortexV1: The CTI will be configured for synchronous start and
stop via CTI. It assumes the connection of DBGRQ, DBGACK,
DBGRESTART signals to CTI are done as recommended by
ARM. The CTIBASE must be notified. CortexV1 is the default
value if a Cortex-R/-A core is selected and the CTIBASE is
notified.
QV1: This mode is not yet used.
Cortex-M Debugger
55
Informs the debugger that a customer proprietary Data Trace

Message (DTM) module is available. This causes the debugger
to consider this source when capturing common trace data.
Trace data from this module will be recorded and can be
accessed later but the unknown DTM module itself will not be
controlled by the debugger.
This changes the bypass data pattern for other TAPs in a multiTAP JTAG chain. It changes the pattern from all 1 to all 0. This
is a workaround for a certain chip problem. It is available on the
ARM9 debugger, only.
TIOCPTYPE <type>
Specifies the type of the OCP module from Texas Instruments

(TI).
view
Opens a window showing most of the SYStem.CONFIG settings

and allows to modify them.
Deprecated versa new command
In the following you find the list of deprecated commands which can still be used for compatibility reasons
and the corresponding new command.
SYStem.CONFIG <parameter>
<parameter>:
(Deprecated)
<parameter>:
(New)
BMCBASE <address>
BMC.Base <address>
BYPASS <seq>
CHIPIRPRE <bits>
CHIPIRLENGTH <bits>
CHIPIRPATTERN.Alternate <pattern>
COREBASE <address>
CTIBASE <address>
CTI.Base <address>
CTICONFIG <type>
CTI.Config <type>
DEBUGBASE <address>
DTM.Type.Generic
DTMETBFUNNELPORT <port>
FUNNEL4.ATBSource DTM <port> (1)
DTMFUNNEL2PORT <port>
DTMFUNNELPORT <port>
DTMTPIUFUNNELPORT <port>
DWTBASE <address>
DWT.Base <address>
ETB2AXIBASE <address>
Cortex-M Debugger
56
ETBBASE <address>
ETB1.Base <address>
ETBFUNNELBASE <address>
FUNNEL4.Base <address>
ETFBASE <address>
ETF1.Base <address>
ETMBASE <address>
ETM.Base <address>
ETMETBFUNNELPORT <port>
FUNNEL4.ATBSource ETM <port> (1)
ETMFUNNEL2PORT <port>
ETMFUNNELPORT <port>
ETMTPIUFUNNELPORT <port>
CHIPDRPRE 0
CHIPDRPOST 0
CHIPDRLENGTH <bits_of_complete_DR_path>
CHIPDRPATTERN.Alternate 0
FUNNEL2BASE <address>
FUNNELBASE <address>
HSMBASE <address>
HSM.Base <address>
HTMBASE <address>
HTM.Base <address>
HTMETBFUNNELPORT <port>
FUNNEL4.ATBSource HTM <port> (1)
HTMFUNNEL2PORT <port>
HTMFUNNELPORT <port>
HTMTPIUFUNNELPORT <port>
ITMBASE <address>
ITM.Base <address>
ITMETBFUNNELPORT <port>
FUNNEL4.ATBSource ITM <port> (1)
ITMFUNNEL2PORT <port>
ITMFUNNELPORT <port>
ITMTPIUFUNNELPORT <port>
PERBASE <address>
RAMBASE <address>
RTPBASE <address>
RTP.Base <address>
SDTIBASE <address>
STM1.Base <address>
STM1.Mode SDTI
STM1.Type SDTI
STMBASE <address>
STM1.Base <address>
STM1.Mode STPV2
STM1.Type ARM
STMETBFUNNELPORT <port>
FUNNEL4.ATBSource STM1 <port> (1)
STMFUNNEL2PORT <port>
STMFUNNELPORT <port>
STMTPIUFUNNELPORT <port>

Cortex-M Debugger
57
TIADTFBASE <address>
ADTF.Base <address>
TIDRMBASE <address>
DRM.Base <address>
TIEPMBASE <address>
EPM.Base <address>
TIICEBASE <address>
ICE.Base <address>
TIOCPBASE <address>
OCP.Base <address>
TIOCPTYPE <type>
OCP.Type <type>
TIPMIBASE <address>
PMI.Base <address>
TISCBASE <address>
SC.Base <address>
TISTMBASE <address>
STM1.Base <address>
STM1.Mode STP
STM1.Type TI
TPIUBASE <address>
TPIU.Base <address>
TPIUFUNNELBASE <address>
TRACEETBFUNNELPORT <port>
FUNNEL4.ATBSource ADTF <port> (1)
TRACEFUNNELPORT <port>
TRACETPIUFUNNELPORT <port>
view
state
(1) Further <component>.ATBSource <source> commands might be needed to describe the full trace data
path from trace source to trace sink.
SYStem.CPU
Select the used CPU
Format:
SYStem.CPU <cpu>
<cpu>:
CORTEXM3
Selects the processor type. If your ASIC is not listed, select the type of the integrated ARM core.
Default selection: CORTEXM3
Cortex-M Debugger
58
SYStem.CpuAccess
Format:
Run-time memory access (intrusive)
SYStem.CpuAccess Enable | Denied | Nonstop
Default: Denied.
Enable
Allow intrusive run-time memory access.
Denied
Lock intrusive run-time memory access.
Nonstop
Lock all features of the debugger that affect the run-time behavior.
If SYStem.CpuAccess Enable is set, it is possible to read from memory, to write to memory and to set
software breakpoints while the core is executing the program. On-chip breakpoints can always be set while
program execution is running. To make this possible, the program execution is shortly stopped by the
debugger. Each stop takes 0.1-100 ms depending on the speed of the JTAG port and the operations that
should be performed. A red S in the state line of the TRACE32 screen warns you, that the program is no
longer running in realtime.
If specific windows, that display memory or variables should be updated while the program is running select
the memory class E: or the format option %E.
Data.dump E:0x100
Var.View %E first
Cortex-M Debugger
59
SYStem.JtagClock
Format:
SYStem.JtagClock [<frequency> | RTCK | ARTCK <frequency> | CTCK

<frequency> | CRTCK <frequency>]
<frequency>:
6 kHz80 MHz
Default frequency: 10 MHz.

Selects the JTAG port frequency (TCK) used by the debugger to communicate with the DAP. This can
influence e.g. the download speed. It could be required to reduce the JTAG frequency if there are buffers,
additional loads or high capacities on the JTAG lines or if VTREF is very low. A very high frequency will not
work on all systems and will result in an erroneous data transfer. Therefore we recommend to use the default
setting if possible.
<frequency>:
The debugger can not select all frequencies accurately. It chooses the next possible frequency and displays
the real value in the System Settings window.
Besides a decimal number like 100000. also short forms like 10kHz or 15MHz can be used. The short
forms implies a decimal value, although no . is used.
RTCK: The JTAG clock is controlled by the RTCK signal (Returned TCK).
On some multicore systems there is the need to synchronize the processor clock and the JTAG clock. In this
case RTCK shall be selected. Synchronization is maintained, because the debugger does not progress to
the next TCK edge until after an RTCK edge is received.
In case you have a processor derivative requiring a synchronization of the processor clock and the JTAG
clock, but your target does not provide a RTCK signal, you need to select a fix JTAG clock below which is low
enough to be adequate to the speed you would reach if RTCK is available.
When RTCK is selected, the frequency depends on the processor clock and on the propagation delays. The
maximum reachable frequency is about 16 MHz.
Example: SYStem.JtagClock RTCK
The clock mode RTCK can not be used if a debug cable with 14-pin flat cable
(LA-7740) is used. And it is required that the target provides a RTCK signal.
Cortex-M Debugger
60
ARTCK: Accelerated method to control the JTAG clock by the RTCK signal (Accelerated Returned TCK).
RTCK mode allows theoretical frequencies up to 1/6 or 1/8 of the processor clock. For designs using a very
low processor clock we offer a different mode (ARTCK) which does not work as recommended by ARM and
might not work on all target systems. In ARTCK mode the debugger uses a fixed JTAG frequency for TCK,
independent of the RTCK signal. This frequency must be specified by the user and has to be below 1/3 of
the processor clock speed. TDI and TMS will be delayed by 1/2 TCK clock cycle. TDO will be sampled with
RTCK
The mode ARTCK can not be used if a debug cable with 14-pin flat cable (LA7740) is used. And it is required that the target provides a RTCK signal.
CTCK: With this option higher JTAG speeds can be reached. The TDO signal will be sampled by a signal
which derives from TCK, but which is timely compensated regarding the debugger internal driver
propagation delays (Compensation by TCK). This feature can be used with a debug cable versions 3b or
newer. If it is selected, although the debug cable is not suitable, a fix JTAG clock will be selected instead
(minimum of 10 MHz and selected clock).
This feature can be used with a debug cable versions 3 or newer.
CRTCK: With this option higher JTAG speeds can be reached. The TDO signal will be sampled by the
RTCK signal. This compensates the debugger internal driver propagation delays, the delays on the cable
and on the target (Compensation by RTCK). This feature requires that the target provides a RTCK signal.
Other as on RTCK option, the TCK is always output with the selected, fix frequency.
The mode CRTCK can not be used if a debug cable with 14-pin flat cable (LA7740) is used. And it is required that the target provides a RTCK signal.
Cortex-M Debugger
61
SYStem.LOCK
Format:
Tristate the JTAG port
SYStem.LOCK [ON | OFF]
Default: OFF.
If the system is locked no access to the JTAG port will be performed by the debugger. While locked the JTAG
connector of the debugger is tristated. The intention of the lock command is for example to give JTAG
access to another tool. The process can also be automated, see SYStem.CONFIG TriState.
It must be ensured that the state of the DAP JTAG state machine remains unchanged while the system is
locked. To ensure correct hand over the options SYStem.CONFIG TAPState and SYStem.CONFIG
TCKLevel must be set properly. They define the TAP state and TCK level which is selected when the
debugger switches to tristate mode. Please note: nTRST must have a pull-up resistor on the target,
EDBGRQ must have a pull-down resistor.
There is a single cable contact on the casing of the debug cable. This contact can be used to detect if the
JTAG connector is tristated. If tristated also this signal is tristated, it is pulled low otherwise.
Cortex-M Debugger
62
SYStem.MemAccess
Format:
SYStem.MemAccess <mode>
<mode>:
CPU
DAP
TSMON3
PTMON3
UDMON3
RealMON
TrkMON
GdbMON
Denied
Default: Denied.
If SYStem.MemAccess is not Denied, it is possible to read from memory, to write to memory and to set
software breakpoints while the core is executing the program. This requires one of the following methods.
CPU
A run-time memory access is made without core intervention while the program
is running. This is only possible on the instruction set simulator.
DAP
A run-time memory access is done through the MEM-AP AHB via DAP (Debug
Access Port). Since this is nearly non-intrusive and does not require any
monitor running on the target, it normally will be the best selection for Cortex-M.
TSMON
TSMON uses a data format which shall not be used anymore. It still works for
compatibility reasons. TSMON3 shall be used.
TSMON3
A run-time memory access is done via a Time Sharing Monitor.

The application is responsible for calling the monitor polling code periodically.
The call is typically included in a periodic interrupt or in the idle task of the
kernel.
Handling of interrupts when the application is stopped is possible when the
background monitor is activated. Manual break is not possible and can only be
emulated by polling the DCC port.
See also the example in the demo/arm/etc/tsmon directory.
PTMON
PTMON uses a data format which shall not be used anymore. It still works for
compatibility reasons. PTMON3 shall be used.
Cortex-M Debugger
63
PTMON3
A run-time memory access is done via a Pulse Triggered Monitor.

Whenever the debugger wants to perform a memory access while the program
is running, the debugger generates a trigger for the trigger bus. If the trigger bus
is configured appropriate (TrBus), this trigger is output via the TRIGGER
connector of the TRACE32 development tool. The TRIGGER output can be
connected to an external interrupt in order to call a monitor.
UDMON
UDMON uses a data format which shall not be used anymore. It still works for
compatibility reasons. UDMON3 shall be used.
UDMON3
A run-time memory access is done via a Usermode Debug Monitor.

The application is responsible for calling the monitor polling code periodically.
The call is typically included in a periodic interrupt or in the idle task of the
kernel.
Handling of interrupts when the application is stopped is possible when the
background monitor is activated. On-chip breakpoints and manual program
break are only possible when the core is in USR mode.
See also the example in the demo/arm/etc/udmon directory.
RealMON
A run-time memory access is done via the Real Monitor from ARM.
TrkMON
A run-time memory access is done via the TRKMON from Symbian.
GdbMON
A run-time memory access is done via the GDB Server from Linux.
Denied
No memory access is possible while the CPU is executing the program.
If specific windows, that display memory or variables should be updated while the program is running select
the memory class E: or the format option %E. If you want this for all your windows then select
SYStem.Option DUALPORT ON
Data.dump E:0x100
Var.View %E first
Cortex-M Debugger
64
SYStem.Mode
Establish the communication with the target
Format:
SYStem.Mode <mode>
<mode>:
Down
NoDebug
Go
Attach
StandBy
Up
Prepare
Down
Disables the debugger (default). The state of the core remains unchanged. The
JTAG port is tristated.
NoDebug
Disables the debugger. The state of the core remains unchanged. The JTAG
port is tristated.
Go
Resets the target and enables the debugger and start the program execution.
The nSRST signal will be pulsed and a software reset will be performed.
Program execution can be stopped by the break command or external trigger.
Attach
The mode of the core (running or halted) does not change, but debugging will
be initialized. After this command the user program can be stopped with the
break command or if any break condition occurs.
StandBy
Resets the target, waits until power is detected, restores the debug registers
(e.g. breakpoints, trace control), releases reset to start the program execution.
When power goes down again, it switches automatically back to this state. This
allows debugging of a power cycle, because debug register will be restored on
power up. Please note that the debug register require a halt/go sequence to
become active. It is not sufficient to set breakpoints in DOWN mode and switch
to STANDBY mode. Exception: On-chip breakpoints and vector catch register
can be set while the program is running. This mode is not yet available.
Up
Resets the target, sets the core to debug mode and stops the core. The nSRST
signal will be pulsed and a software reset will be performed. After the execution
of this command the core is stopped and all register are set to the default level.
You need to execute Register.Init to force the debugger to read out the program
counter and stack pointer address.
Prepare
Resets the target, initializes the JTAG interface, but does not connect to the
ARM core. This debugger startup is used if no ARM core shall be debugged. It
can be used if a user program or proprietary debugger uses the TRACE32 API
(application programming interface) to access the JTAG interface via the
TRACE32 debugger hardware.
Cortex-M Debugger
65
SYStem.Option AHBHPROT
Format:
Select AHB-AP HPROT bits.
SYStem.Option AHBHPROT <value>
Default: 0
This option selects the value used for the HPROT bits in the Control Status Word (CSW) of an AHB Access
Port of a DAP, when using the AHB: memory class.
SYStem.Option AXIACEEnable
Format:
ACE enable flag of the AXI-AP
SYStem.Option AXIACEEnable [ON | OFF]
Default: OFF
Enable ACE transactions on the DAP AXI-AP, including barriers.
SYStem.Option AXICACHEFLAGS
Format:
Select AXI-AP CACHE bits.
SYStem.Option AXICACHEFLAGS <value>
Default: 0
This option selects the value used for the CACHE bits in the Control Status Word (CSW) of an AXI Access
Port of a DAP, when using the AXI: memory class.
SYStem.Option AXIHPROT
Format:
Select AXI-AP HPROT bits.
SYStem.Option AXIHPROT <value>
Default: 0
This option selects the value used for the HPROT bits in the Control Status Word (CSW) of an AXI Access
Port of a DAP, when using the AXI: memory class.
Cortex-M Debugger
66
SYStem.Option BigEndian
Format:
Define byte order (endianess)
SYStem.Option BigEndian [ON | OFF]
This option is normally not needed because Cortex-M is always little endian. But there are special chip
designs where the debugger needs to handle the data as big endian.
SYStem.Option CORTEXMAHB
Format:
AHB-AP type of the Cortex-M
SYStem.Option CORTEXMAHB [ON | OFF]
Default: ON
This option needs to be turned off, if the Cortex-M core is accessed via a standard AHB Access Port
provided by the ARM CoreSight design kit, that needs to be handled different than the Cortex-M AHB
Access Port.
SYStem.Option DAPNOIRCHECK
Format:
No DAP instruction register check
SYStem.Option DAPNOIRCHECK [ON | OFF]
Default: OFF.
Bug fix for derivatives which do not return the correct pattern on a DAP (ARM CoreSight Debug Access Port)
instruction register (IR) scan. When activated the returned pattern will not be checked by the debugger.
Cortex-M Debugger
67
SYStem.Option DAPREMAP
Format:
Rearrange DAP memory map
SYStem.Option DAPREMAP <address_range> <address> ...
The Debug Access Port (DAP) can be used for memory access during runtime. If the mapping on the
DAP is different than the processor view, then this re-mapping command can be used.
NOTE:
Up to 16 <address_range>/<address> pairs are possible.
SYStem.Option DEBUGPORTOptions
Options for debug port handling
Format:
SYStem.Option DEBUGPORTOptions <option>
<option>:
JTAGTOSWD [auto | CORTEX | LUMINARY | None]

SWDDORMANT [auto | WakeUp | NoWakeUp]
Default: auto.
This option is only required for expert users in case a non standard SWD implementation is used.
JTAGTOSWD tells the debugger what to do when switching from JTAG to SWD mode:
auto
Auto detection.
The debugger tries to detect the correct SWD to JTAG shift sequence.
CORTEX
Switching procedure like it should be done for Cortex cores.
LUMINARY
Switching procedure like it should be done for LuminaryMicro devices.
None
Do not send any SWD to JTAG sequence.
SWDDORMANT tells the debugger how to handle a dormant state when switching to SWD:
auto
Auto detection.
WakeUp
Wake up the debug port without prior checks by sending DORMANT to SWD
sequence.
NoWakeUp
Do not wake up the debug port by suppressing the DORMANT to SWD

sequence.
Cortex-M Debugger
68
SYStem.Option DIAG
Format:
Activate more log messages
SYStem.Option DIAG [ON | OFF]
Default: OFF.
Adds more information to the report in the SYStem.LOG.List window.
SYStem.Option DISableSOFTRESet
Format:
Disable software reset
SYStem.Option DISableSOFTRESet [ON | OFF]
Default: OFF.
This option disables the additional software reset by the APINTRESCON register of Cortex-M cores on
SYStem.Up and SYStem.Mode Go.
Please note that some devices (e.g. STM32) output such an software reset on the RESET pin. Especially if
such an device is daisy-chained with other chips (Multicore/chip debugging) it might cause a reset on other
devices. Its recommended to set SYStem.Option DISableSOFTReset ON additionally to
SYStem.CONFIG.Slave ON in such environments.
Cortex-M Debugger
69
SYStem.Option DisMode
Define disassembler mode
Format:
SYStem.Option DisMode <option>
<option>:
AUTO
ACCESS
ARM
THUMB
THUMBEE
This command specifies the selected disassembler. Default: AUTO.

AUTO
The information provided by the compiler output file is used for the
disassembler selection. If no information is available it has the same behavior
as the option ACCESS.
ACCESS
The selected disassembler depends on the T bit in the CPSR or on the selected
access class. (e.g. Data.List SR:0 for ARM mode or Data.List ST:0 for
THUMB mode).
ARM
Only the ARM disassembler is used (highest priority).
THUMB
Only the THUMB disassembler is used (highest priority).
THUMBEE
Only the THUMB disassembler is used which supports the Thumb-2 Execution
Environment extension (highest priority).
SYStem.Option DUALPORT
Format:
Implicitly use run-time memory access
SYStem.Option DUALPORT [ON | OFF]
All TRACE32 windows that display memory are updated while the processor is executing code (e.g.
Data.dump, Data.List, Per.view, Var.View). This setting has no effect if SYStem.Option.MemAccess is
disabled.
Cortex-M Debugger
70
SYStem.Option EnReset
Format:
Allow the debugger to drive nSRST
SYStem.Option EnReset [ON | OFF]
Default: ON.
If this option is disabled the debugger will never drive the nSRST line on the JTAG connector. This is
necessary if nSRST is no open collector or tristate signal.
From the view of the Cortex-M it is not necessary that nSRST becomes active at the start of a debug
session (SYStem.Up), but there may be other logic on the target which requires a reset.
SYStem.Option IMASKASM
Format:
Disable interrupts while single stepping
SYStem.Option IMASKASM [ON | OFF]
Default: OFF.
If enabled, interrupt are disabled during assembler single-step operations.
SYStem.Option IMASKHLL
Format:
Disable interrupts while HLL single stepping
SYStem.Option IMASKHLL [ON | OFF]
Default: OFF.
If enabled, the interrupt mask bits of the core will be set during HLL single-step operations. The interrupt
routine is not executed during single-step operations. After single step the interrupt mask bits are restored to
the value before the step.
SYStem.Option IntelSOC
Format:
Debugging of an Intel SOC
SYStem.Option IntelSOC [ON | OFF]
Need to be enabled for some SOCs from intel.
Cortex-M Debugger
71
SYStem.Option INTDIS
Format:
Disable all interrupts
SYStem.Option INTDIS [ON | OFF]
Default: OFF.
If this option is ON all interrupts to the Cortex-M core are disabled.
SYStem.Option LOCKRES
Format:
Go to "Test-Logic Reset" when locked
SYStem.Option LOCKRES [ON | OFF]
This command is only available on obsolete ICD hardware. The state machine of the JTAG TAP controller is
switched to Test-Logic Reset state (ON) or to Run-Test/Idle state (OFF) before a SYStem.LOCK ON is
executed.
SYStem.Option MEMORYHPROT
Format:
Select memory-AP HPROT bits
SYStem.Option MEMORYHPROT <value>
Default: 0
This option selects the value used for the HPROT bits in the Control Status Word (CSW) of an Memory
Access Port of a DAP, when using the E: memory class.
SYStem.Option MMUSPACES
Format:
Enable multiple address spaces support
SYStem.Option MMUSPACES [ON | OFF]

SYStem.Option MMU [ON | OFF] (deprecated)
Default: OFF.
Enables the usage of the MMU to support multiple address spaces. The command should not be used if
only one translation table is used. Enabling the option will extend the address scheme of the debugger by a
16 bit memory space identifier. You should activate the option first, and then load the symbols.
Cortex-M Debugger
72
SYStem.Option NoRunCheck
Format:
No check of the running state
SYStem.Option NoRunCheck [ON | OFF]
Default: OFF.
This option advises the debugger not to do any running check. In this case the debugger does not even
recognize that there will be no response from the processor. Therefore there is always the message
"running" independent if the core is in power down or not. This can be used to overcome power saving
modes in case the user knows when this happens and that he can manually de-activate and re-activate the
running check.
SYStem.Option OVERLAY
Format:
Enable overlay support
SYStem.Option OVERLAY [ON | OFF | WithOVS]
Default: OFF.
ON
Activates the overlay extension and extends the address scheme of the
debugger with a 16 bit virtual overlay ID. Addresses therefore have the
format <overlay_id>:<address>. This enables the debugger to
handle overlaid program memory.
OFF
Disables support for code overlays.
WithOVS
Like option ON, but also enables support for software breakpoints. This
means that TRACE32 writes software breakpoint opcodes both to the
execution area (for active overlays) and to the storage area. In this way, it is
possible to set breakpoints into inactive overlays. Upon activation of the
overlay, the target's runtime mechanisms copies the breakpoint opcodes to
execution area. For using this option, the storage area must be readable and
writable for the debugger.
SYStem.Option OVERLAY ON
Data.List 0x2:0x11c4
; Data.List <overlay_id>:<address>
Cortex-M Debugger
73
SYStem.Option PWRDWNRecover
Format:
Mode to handle special power recovery
SYStem.Option PWRDWNRecover [ON | OFF]
Some power saving states of Cortex-M controller additionally turn off the debug interface. The debugger
usually would go into SYStem.Down state with a emulation debug port fail error message. Turining on this
option the debugger assumes, that the target has entered a power saving state and permanently tries to
reconnect to the device, so that the debug session will not go lost. Additionally the debugger tries to restore
all debug and trace registers, if possible.
Attention: This option will turn off basic debug connectivity checks. If there are problems with the debug
port, then they might not be detected. Instead of this false power down messages will be displayed.
Cortex-M Debugger
74
SYStem.Option ResBreak
Format:
Halt the core after reset
SYStem.Option ResBreak [ON | OFF]
Default: ON.
This option has to be disabled if the nTRST line is connected to the nSRST line on the target. In this case
the core executes some cycles while the SYStem.Up command is executed. The reason for this behavior is
the fact that it is necessary to halt the core (enter debug mode) by a JTAG sequence. This sequence is only
possible while nTRST is inactive. In the following figure the time between the deassertion of reset and the
entry to debug mode is the time for this JTAG sequence.
nSRST
nTRST
CPU State
<5ms
reset
running
debug
If nTRST is available and not connected to nSRST it is possible to force the core directly after reset (without
cycles) into debug mode. This is also possible by pulling nTRST fixed to VCC (inactive), but then there is the
problem that it is normally not ensured that the JTAG port is reset in normal operation. If the ResBreak
option is enabled the debugger first deasserts nTRST, then it executes a JTAG sequence to force the core to
halt immediately after reset and then it deasserts nSRST.
nSRST
nTRST
CPU State
reset
debug
Cortex-M Debugger
75
SYStem.Option RESetREGister
Generic software reset
Format:
SYStem.Option.RESetRegister NONE
SYStem.Option.RESetRegister <address>
<mask>
<assert_value>
<deassert_value>
[/<width>]
<width>:
Byte
Word
Long
Quad
The command is used to specify a register on target side, which allows the debugger to assert a software
reset, in case no nReset line is present on the JTAG header. The reset is asserted on SYStem.Up,
SYStem.Mode.Go and SYStem.RESetOut. The specified address need to be accessible during runtime (for
example E, DAP, AXI, AHB, APB).
address
Specifies the address of the target reset register.
mask
The assert vaule and deassert value are written in a read-modify-write

operation. The mask specifies, which bits are changed by the debugger.
Bits of the mask value, which are 1 are not changed inside the reset
register.
assert_value
Value, that is written to assert reset
deassert_value
Value, that is written to deassert reset
Cortex-M Debugger
76
SYStem.Option RisingTDO
Format:
Target outputs TDO on rising edge
SYStem.Option RisingTDO [ON | OFF]
Default: OFF.
Bug fix for chips which output the TDO on the rising edge instead of on the falling.
SYStem.Option SELECTDAP
Format:
Select Cortex-M DAP
SYStem.Option SELECTDAP [DAP | DAP2]
Select, if the Cortex-M core is debugged via the DAP (default) or DAP2. For debugging via DAP2 a second
DAP need to be present in the chip and need to be configured by SYStem.CONFIG.
SYStem.Option SOFTLONG
Format:
SYStem.Option SOFTLONG [ON | OFF]
Default: OFF.
This option instructs the debugger to use 32-bit accesses to patch the software breakpoint code.
SYStem.Option SOFTWORD
Format:
SYStem.Option SOFTWORD [ON | OFF]
Default: OFF.
This option instructs the debugger to use 16-bit accesses to patch the software breakpoint code.
Cortex-M Debugger
77
SYStem.Option STEPSOFT
Format:
Use software breakpoints for ASM stepping
SYStem.Option STEPSOFT [ON | OFF]
Default: OFF.
If this option is ON software breakpoints are used for single stepping on assembler level (advanced users
only).
SYStem.Option DAPSYSPWRUPREQ
Format:
Force system power in DAP
SYStem.Option DAPSYSPWRUPREQ [ON | OFF]
Default: ON.
This option controls the SYSPWRUPREQ bit of the CTRL/STAT register of the Debug Access Port (DAP). If
the option is ON, system power will be requested by the debugger on a debug session start.
This option is for target processors having a Debug Access Port (DAP) e.g., Cortex-A or Cortex-R.
SYStem.Option DAP2SYSPWRUPREQ
Format:
Force system power in DAP2
SYStem.Option DAP2SYSPWRUPREQ [ON | OFF]
Default: ON.
This option controls the SYSPWRUPREQ bit of the CTRL/STAT register of a second Debug Access Port
(DAP2). If the option is ON, system power will be requested by the debugger on a debug session start.
This option is for target processors having a second Debug Access Port (DAP2).
Cortex-M Debugger
78
SYStem.Option TRST
Format:
Allow debugger to drive TRST
SYStem.Option TRST [ON | OFF]
Default: ON. If this option is disabled the nTRST line is never driven by the debugger. Instead five
consecutive TCK pulses with TMS high are asserted to reset the TAP controller which have the same effect.
SYStem.Option WaitReset
Format:
Wait with JTAG activities after deasserting reset
SYStem.Option WaitReset [ON | OFF]
Default: OFF.
If SYStem.Option WaitReset is enabled and SYStem.Option ResBreak is disabled the debugger waits
after the deassertion of nSRST and nTRST before the first JTAG activity starts. It waits for at least 1 s, then it
waits until nSRST is released from target side, but at maximum 35 s. During this time the core may execute
some code, e.g to enable the JTAG port. If SYStem.Option ResBreak is enabled the
SYStem.Option WaitReset is ignored.
nRESET/nSRST
nTRST
CPU State
>1s
reset
running
SYStem.Option WakeUpACKnowledge
Format:
debug
Set acknowledge after wakeup
SYStem.Option WakeUpACKnowledge [ON | OFF]
Some targets additionally need an acknowledge by the debugger after a wakeup to be sure, that debug and
trace are working correctly after leaving a deep sleep or power off state. Additionally to get this option to take
effect is, to set SYStem.Option PWRDWNRecover ON.
Attention: Depending on the target setting this option may have an impact to the clock and power
managment of the chip. The target software might behave differently, when this opiton is set.
Cortex-M Debugger
79
SYStem.Option ZoneSPACES
Format:
Enable symbol management for ARM zones
SYStem.Option ZoneSPACES [ON | OFF]
Default: OFF
The SYStem.Option ZoneSPACES command is relevant if an ARM CPU with TrustZone or
VirtualizationExtension is debugged. In these ARM CPUs, the processor has two or more CPU operation
modes called:
Nonsecure mode
Secure mode
Hypervisor mode
Within TRACE32, these CPU operation modes are referred to as zones.

In each CPU operation mode (zone), the CPU uses separate MMU translation tables for memory accesses
and separate register sets. Consequently, in each zone, different code and data can be visible on the same
logical addresses.
To ease debug-scenarios where the CPU operation mode switches between nonsecure, secure or
hypervisor mode, it is helpful to load symbol sets for each used zone.
OFF
(Default)
TRACE32 does not separate symbols by access class. Loading two or more
symbol sets with overlapping address ranges will result in unpredictable
behavior. Loaded symbols are independent of ARM zones.
ON
Separate symbol sets can be loaded for each zone, even with
overlapping address ranges. Loaded symbols are specific to one of the
ARM zones - each symbol carries one of the access classes N:, Z:, or H:
For details and examples, see below.
Cortex-M Debugger
80
SYStem.Option ZoneSPACES ON
If the ZoneSPACES option is enabled (ON), TRACE32 enforces any memory address specified in a
TRACE32 command to have an access class which clearly indicates to which zone it belongs.
If an address specified in a command is not clearly attributed to N: Z: or H:, the access class of the current
PC context is used to complete the addresses access class.
Every loaded symbol is attributed to either nonsecure (N:), secure (Z:) or hypervisor (H:) zone. If a symbol is
referenced by name, the associated access class (N: Z: or H:) will be used automatically, so that the memory
access is done within the correct CPU mode context. This implies that the symbols logical address will be
translated to the physical address with the correct MMU translation table.
NOTE:
The loaded symbols and their associated access class can be examined with
command sYmbol.List or sYmbol.Browse or sYmbol.INFO.
Example 1 - Loading Symbols
SYStem.Option ZONESPACES ON
; 1. Load the vmlinux symbols for nonsecure mode (access classes N:, NP:
; and ND: used for the symbols):
Data.LOAD.ELF vmlinux N:0x0 /NoCODE
; 2. Load the sysmon symbols for secure mode (access classes Z:, ZP: and
; ZD: used for the symbols):
Data.LOAD.ELF sysmon Z:0x0 /NoCODE
; 3. Load the xen-syms symbols for hypervisor mode (access classes H:,
; HP: and HD: used for the symbols):
Data.LOAD.ELF xen-syms H:0x0 /NoCODE
; 4. Load the sieve symbols without specification of a target access
; class:
Data.LOAD.ELF sieve /NoCODE
; Assuming that the current CPU mode is nonsecure in this example, the
; symbols of sieve will get the access classes N:, NP: and ND: assigned
; during loading.
Cortex-M Debugger
81
Example 2 - Symbolic memory access:
; dump the address on symbol swapper_pg_dir which belongs

; to the nonsecure symbol set "vmlinux" we have loaded above:
Data.Dump swapper_pg_dir
; This will automatically use access class N: for the memory access,
; even if the CPU is currently not in nonsecure mode.
Example 3 - Deleting Zone-specific Symbols:

To delete a complete symbol set belonging to a specific zone, e.g. the nonsecure zone, use the following
command to delete all symbols in the specified address range:
sYmbol.Delete N:0x0--0xffffffff
; nonsecure mode (access classes N:)
Zone-specific Debugger Address Translation Setup

If option ZoneSPACES is enabled and the debugger address translation is used (TRANSlation commands),
a strict zone separation of the address translations is enforced. Also, common address ranges will always be
specific for a certain zone (command TRANSlation.COMMON).
This example shows how to define separate translations for zones N: and H:
Data.LOAD.Elf sysmon Z:0 /NoCODE
Data.LOAD.Elf usermode N:0 /NoCODE /NoClear
; set up address translation for secure mode
TRANSlation.Create Z:0xC0000000++0x0fffffff A:0x10000000
; set up address translation for nonsecure mode
TRANSlation.Create N:0xC0000000++0x1fffffff A:0x40000000
; enable address translation and table walk
TRANSlation.ON
; check the complete translation setup
TRANSlation.List
Operation System Support

If the CPUs virtualization extension is used to virtualize one or more guest systems, the hypervisor always
runs in the CPUs hypervisor mode (zone H:), and the current guest system (if a ready-to-run guest is
configured at all by the hypervisor) will run in the CPUs nonsecure mode (zone N:).
Often, an operation system (such as a Linux kernel) runs in the context of the guest system.
Cortex-M Debugger
82
In such a setup with hypervisor and guest OS, it is possible to load both the hypervisor symbols to H: and all
OS-related symbols to N:
A TRACE32 OS awareness can be loaded in TRACE32 to support the work with the OS in the guest
system. This is done as follows:
1.
2.
Configure the OS awareness as for a non-virtualized system. See:

-
Training Linux Debugging (training_rtos_linux.pdf)
TASK.CONFIG command
Additionally set the default access class of the OS awareness to the nonsecure zone:
TASK.ACCESS N:
The TRACE32 OS awareness is now configured to find guest OS kernel symbols in the nonsecure
zone.
NOTE:
This debugger setup based on option ZoneSPACES will only allow to view and
work with one guest system simultaneously.
If the hypervisor has configured more than one guest, only the guest that is active in
the nonsecure CPU mode is visible.
To work with another guest, the system must continue running until an inactive
guest becomes the active guest.
Currently, only one OS awareness can be loaded into TRACE32. To debug more than one OS, the OS
awareness must be reloaded after each switch to another OS.
Cortex-M Debugger
83
Example setup for a guest OS and a hypervisor:

In this example, the hypervisor is configured to run in zone H: and a Linux kernel with OS awareness as
current guest OS in zone N:
; within the OS awareness we need the space ID to separate address spaces
; of different processes / tasks
SYStem.Option MMUSPACES ON
; here we let the target system boot the hypervisor. The hypervisor will
; set up the guest and boot Linux on the guest system.
...
; load the hypervisor symbols
Data.LOAD.Elf xen-syms H:0 /NoCODE
Data.LOAD.Elf usermode N:0 /NoCODE /NoClear
; set up the Linux OS awareness
TASK.CONFIG ~~/demo/arm/kernel/linux/linux-3.x/linux3
MENU.ReProgram ~~/demo/arm/kernel/linux/linux-3.x/linux
; instruct the OS awareness to access all OS related symbols with
; access class N:
TASK.ACCESS N:
; set up the debugger address translation for the guest OS
; Note that the default address translation in the following command
; defines a translation of the logical kernel addresses
; N:0xC0000000++0xFFFFFFF to intermediate physical address I:0x40000000
MMU.FORMAT linux swapper_pg_dir N:0xC0000000++0xFFFFFFF I:0x40000000
; define the common address range for the guest kernel symbols
TRANSlation.COMMON N:0xC0000000--0xFFFFFFFF
; enable the address translation and the table walk
TRANSlation.TableWalk ON
TRANSlation.ON
NOTE:
If SYStem.Option MMUspaces ON is used, all addresses for all zones will show
a space ID extension (such as N:0x024A:0x00320100), even if the OS
awareness runs only in one zone (as defined with command TASK.ACCESS).
TRACE32 will always show a space ID of 0x0000 for any address belonging to
the other zones.
Any command related to task handling, such as TRANSlation.List.TaskPageTable <taskname>, will

automatically refer to tasks running in the zone where the OS awareness runs in.
Cortex-M Debugger
84
SYStem.RESetOut
Format:
Performs a reset
SYStem.RESetOut
This command asserts the nSRST line on the JTAG connector and performs a software reset. This
command can be used independent if the core is running or halted.
SYStem.state
Format:
Display SYStem.state window
SYStem.state
Displays the SYStem.state window for Cortex-M.
Cortex-M Debugger
85
ARM Specific Benchmarking Commands

The BMC (BenchMark Counter) commands provide control of counters in the data watchpoint and trace unit
(DWT). The DWT can generate statistics on the operation of the processor and the memory system.
The counters of the DWT can be read at run-time, but the limited counter size (8 bit) leads to quick counter
overflows. A meaningful benchmarking analysis is possible if you let the ITM emit a trace packet each time
the counter overflows.
For information about architecture-independent BMC commands, refer to BMC (general_ref_b.pdf).
For information about architecture-specific BMC commands, see command descriptions below.
BMC.Trace
Format:
Activate BMC trace
BMC.Trace [ON | OFF]
Default: OFF.
Switches the ITM on in order to output the benchmark counter values through the instrumentation trace.
Cortex-M Debugger
86
ARM Specific Benchmarking Commands
ARM specific TrOnchip Commands
TrOnchip.view
Format:
Display on-chip trigger window
TrOnchip.view
Open TrOnchip window.
TrOnchip.CONVert
Format:
Extend the breakpoint range
TrOnchip.CONVert [ON | OFF]
The Cortex-M does not provide resources to set an on-chip breakpoint to an address range. Only bit masks
can be used to mark a memory range with a breakpoint.
If TrOnchip.CONVert is set to ON (default) and a breakpoint is set to a range, this range is extended to the
next possible bit mask. The result is, that in most cases a bigger address range is marked by the specified
breakpoint. This can be easily controlled by the Data.View command.
If TrOnchip.CONVert is set to OFF, the debugger will only accept breakpoints which exactly fit to the on-chip
breakpoint hardware.
TrOnchip.RESERVE
Format:
Reserve on-chip breakpoint comparators
TrOnchip.RESERVE FPx [ON | OFF]
Reserve on-chip breakpoint comparators to be used by the target application.

OFF (default): The on-chip breakpoint can be used by the debugger.
ON: The on-chip breakpoint is used by the target application.
Cortex-M Debugger
87
TrOnchip.RESet
Format:
Reset on-chip trigger settings
TrOnchip.RESet
Resets all TrOnchip settings.
Cortex-M Debugger
88
TrOnchip.Set
Set bits in the vector catch register
Format:
TrOnchip.Set <exception> [ON | OFF]
<exception>:
HARDERR
INTERR
BUSERR
STATERR
CHKERR
NOCPERR
MMERR
CORERESET]
Default: ON.
Sets/resets the corresponding bits for vector catching. The bit causes a debug entry when the specified
vector is committed for execution.
HARDERR
Debug trap on hard fault.
INTERR
Debug trap on interrupt/exception service errors. These are a subset of other

faults and catches before BUSERR or HARDERR.
BUSERR
Debug trap on normal bus error.
STATERR
Debug trap on usage fault state errors.
CHKERR
Debug trap on usage fault enabled checking errors.
NOCPERR
Debug trap on usage fault access to coprocessor which is not present or

marked as not present in CAR register.
MMERR
Debug trap on memory management faults.
CORERESET
Reset vector catch. Halt running system if core reset occurs.
Cortex-M Debugger
89
TrOnchip.VarCONVert
Format:
Convert variable breakpoints
TrOnchip.VarCONVert [ON | OFF]
The Cortex-M does not provide resources to set an on-chip breakpoint to an address range. Only bit masks
can be used to mark a memory range with a breakpoint.
If TrOnchip.VarCONVert is set to ON and a breakpoint is set to a scalar variable then it is converted into a
single address breakpoint.
If TrOnchip.VarCONVert is set to OFF variable breakpoints will be set to an address range covering the
whole variable.
Cortex-M Debugger
90
JTAG Connection
Pinout of the 20-pin Debug Cable:
Signal
VREF-DEBUG
TRSTTDI
TMS|TMSC|SWDIO
TCK|TCKC|SWCLK
RTCK
TDO
RESETDBGRQ
DBGACK
Pin
1
3
5
7
9
11
13
15
17
19
Pin
2
4
6
8
10
12
14
16
18
20
Signal
VSUPPLY (not used)
GND
GND
GND
GND
GND
GND
GND
GND
GND
For details on logical functionality, physical connector, alternative connectors, electrical characteristics,
timing behavior and printing circuit design hints refer to ARM JTAG Interface Specifications
(arm_app_jtag.pdf).
Cortex-M Debugger
91
JTAG Connection
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
A2F060
A2F200
A2F500
ADSP-CM402F
ADSP-CM403F
ADSP-CM407F
ADSP-CM408F
ADUCM360
ADUCM361
AM3352
AM3354
AM3356
AM3357
AM3358
AM3359
AT91SAM3A4C
AT91SAM3A8C
AT91SAM3N00A
AT91SAM3N00B
AT91SAM3N0A
AT91SAM3N0B
AT91SAM3N0C
AT91SAM3N1A
AT91SAM3N1B
AT91SAM3N1C
AT91SAM3N2A
AT91SAM3N2B
AT91SAM3N2C
AT91SAM3N4A
AT91SAM3N4B
AT91SAM3N4C
AT91SAM3S16C
AT91SAM3S1A
AT91SAM3S1B
FIRE
ICE
CPU
Available Tools
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
92
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
AT91SAM3S1C
AT91SAM3S2A
AT91SAM3S2B
AT91SAM3S2C
AT91SAM3S4A
AT91SAM3S4B
AT91SAM3S4C
AT91SAM3S8B
AT91SAM3S8C
AT91SAM3SD8B
AT91SAM3SD8C
AT91SAM3U1C
AT91SAM3U1E
AT91SAM3U2C
AT91SAM3U2E
AT91SAM3U4C
AT91SAM3U4E
AT91SAM3X4C
AT91SAM3X4E
AT91SAM3X8C
AT91SAM3X8E
ATSAM4E16C
ATSAM4E16E
ATSAM4E8C
ATSAM4E8E
ATSAM4LC2A
ATSAM4LC2B
ATSAM4LC2C
ATSAM4LC4A
ATSAM4LC4B
ATSAM4LC4C
ATSAM4LC8A
ATSAM4LC8B
ATSAM4LC8C
ATSAM4LS2A
ATSAM4LS2B
ATSAM4LS2C
ATSAM4LS4B
ATSAM4LS4C
ATSAM4LS8A
ATSAM4LS8B
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
93
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
ATSAM4LS8C
ATSAM4N16C
ATSAM4N8A
ATSAM4N8B
ATSAM4N8C
ATSAM4S16A
ATSAM4S16B
ATSAM4S16C
ATSAM4S8A
ATSAM4S8B
ATSAM4S8C
ATSAM4SA16B
ATSAM4SA16C
ATSAM4SD16B
ATSAM4SD16C
ATSAM4SD32B
ATSAM4SD32C
ATSAMD20E14
ATSAMD20E15
ATSAMD20E16
ATSAMD20E17
ATSAMD20G14
ATSAMD20G15
ATSAMD20G16
ATSAMD20G17
ATSAMD20G18
ATSAMD20J14
ATSAMD20J15
ATSAMD20J16
ATSAMD20J17
ATSAMD20J18
ATSAMD21E15A
ATSAMD21E16A
ATSAMD21E17A
ATSAMD21E18A
ATSAMD21G15A
ATSAMD21G16A
ATSAMD21G17A
ATSAMD21G18A
ATSAMD21J15A
ATSAMD21J16A
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
94
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
ATSAMD21J17A
ATSAMD21J18A
ATSAMG51
ATSAMG53
CORTEX-M0
CORTEX-M0+
CORTEX-M1
CORTEX-M3
CORTEX-M4
CY8C5245
CY8C5246
CY8C5247
CY8C5248
CY8C5385
CY8C5386
CY8C5387
CY8C5388
CY8C5485
CY8C5486
CY8C5487
CY8C5488
CY8C5585
CY8C5586
CY8C5587
CY8C5588
EFM32G200F
EFM32G210F
EFM32G222F
EFM32G230F
EFM32G232F
EFM32G280F
EFM32G290F
EFM32G840F
EFM32G842F
EFM32G880F
EFM32G890F
EFM32GG230F
EFM32GG232F
EFM32GG280F
EFM32GG290F
EFM32GG295F
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
95
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
EFM32GG330F
EFM32GG332F
EFM32GG380F
EFM32GG390F
EFM32GG395F
EFM32GG840F
EFM32GG842F
EFM32GG880F
EFM32GG890F
EFM32GG895F
EFM32GG940F
EFM32GG942F
EFM32GG980F
EFM32GG990F
EFM32GG995F
EFM32TG108F
EFM32TG110F
EFM32TG210F
EFM32TG222F
EFM32TG225F
EFM32TG230F
EFM32TG232F
EFM32TG822F
EFM32TG825F
EFM32TG840F
EFM32TG842F
EFM32WG230F
EFM32WG232F
EFM32WG280F
EFM32WG290F
EFM32WG295F
EFM32WG330F
EFM32WG332F
EFM32WG380F
EFM32WG390F
EFM32WG395F
EFM32WG840F
EFM32WG842F
EFM32WG880F
EFM32WG890F
EFM32WG895F
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
96
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
EFM32WG940F
EFM32WG942F
EFM32WG980F
EFM32WG990F
EFM32WG995F
EM773
LM3S101
LM3S102
LM3S1110
LM3S1133
LM3S1138
LM3S1150
LM3S1162
LM3S1165
LM3S1332
LM3S1435
LM3S1439
LM3S1512
LM3S1538
LM3S1601
LM3S1607
LM3S1608
LM3S1620
LM3S1621
LM3S1625
LM3S1626
LM3S1627
LM3S1635
LM3S1637
LM3S1651
LM3S1751
LM3S1776
LM3S1811
LM3S1816
LM3S1850
LM3S1911
LM3S1918
LM3S1937
LM3S1958
LM3S1960
LM3S1968
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
97
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
LM3S1B21
LM3S1J11
LM3S1J16
LM3S1N11
LM3S1N16
LM3S1P51
LM3S1R21
LM3S1R26
LM3S1W16
LM3S1Z16
LM3S2110
LM3S2139
LM3S2276
LM3S2410
LM3S2412
LM3S2432
LM3S2533
LM3S2601
LM3S2608
LM3S2616
LM3S2620
LM3S2637
LM3S2651
LM3S2671
LM3S2678
LM3S2730
LM3S2739
LM3S2776
LM3S2793
LM3S2911
LM3S2918
LM3S2939
LM3S2948
LM3S2950
LM3S2965
LM3S2B93
LM3S300
LM3S301
LM3S308
LM3S310
LM3S315
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
98
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
LM3S316
LM3S317
LM3S328
LM3S3634
LM3S3651
LM3S3739
LM3S3748
LM3S3749
LM3S3759
LM3S3768
LM3S3826
LM3S3J26
LM3S3N26
LM3S3W26
LM3S3Z26
LM3S5632
LM3S5651
LM3S5652
LM3S5656
LM3S5662
LM3S5732
LM3S5737
LM3S5739
LM3S5747
LM3S5749
LM3S5752
LM3S5757
LM3S5762
LM3S5767
LM3S5768
LM3S5769
LM3S5791
LM3S5951
LM3S5956
LM3S5B91
LM3S5C31
LM3S5K31
LM3S5K36
LM3S5P31
LM3S5P36
LM3S5P51
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
99
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
LM3S5P56
LM3S5R31
LM3S5R36
LM3S5T36
LM3S5Y36
LM3S600
LM3S601
LM3S608
LM3S610
LM3S6100
LM3S611
LM3S6110
LM3S612
LM3S613
LM3S615
LM3S617
LM3S618
LM3S628
LM3S6420
LM3S6422
LM3S6432
LM3S6537
LM3S6610
LM3S6611
LM3S6618
LM3S6633
LM3S6637
LM3S6730
LM3S6753
LM3S6911
LM3S6918
LM3S6938
LM3S6950
LM3S6952
LM3S6965
LM3S800
LM3S801
LM3S808
LM3S811
LM3S812
LM3S815
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
100
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
LM3S817
LM3S818
LM3S828
LM3S8530
LM3S8538
LM3S8630
LM3S8730
LM3S8733
LM3S8738
LM3S8930
LM3S8933
LM3S8938
LM3S8962
LM3S8970
LM3S8971
LM3S9781
LM3S9790
LM3S9792
LM3S9997
LM3S9B81
LM3S9B90
LM3S9B92
LM3S9B95
LM3S9B96
LM3S9L97
LM4F110B2QR
LM4F110C4QR
LM4F110E5QR
LM4F110H5QR
LM4F111B2QR
LM4F111C4QR
LM4F111E5QR
LM4F111H5QR
LM4F112C4QC
LM4F112E5QC
LM4F112H5QC
LM4F112H5QD
LM4F120B2QR
LM4F120C4QR
LM4F120E5QR
LM4F120H5QR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
101
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
LM4F121B2QR
LM4F121C4QR
LM4F121E5QR
LM4F121H5QR
LM4F122C4QC
LM4F122E5QC
LM4F122H5QC
LM4F122H5QD
LM4F130C4QR
LM4F130E5QR
LM4F130H5QR
LM4F131C4QR
LM4F131E5QR
LM4F131H5QR
LM4F132C4QC
LM4F132E5QC
LM4F132H5QC
LM4F132H5QD
LM4F230E5QR
LM4F230H5QR
LM4F231E5QR
LM4F231H5QR
LM4F232E5QC
LM4F232H5QC
LM4F232H5QD
LPC1101LV
LPC1102
LPC1102LV
LPC1110
LPC1111
LPC1112
LPC1112LV
LPC1113
LPC1114
LPC1114LV
LPC1115
LPC11A02
LPC11A04
LPC11A11
LPC11A12
LPC11A13
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
102
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
LPC11A14
LPC11C12
LPC11C14
LPC11C22
LPC11C24
LPC11D14
LPC11E11
LPC11E12
LPC11E13
LPC11E14
LPC11E36
LPC11E37
LPC11U12
LPC11U13
LPC11U14
LPC11U23
LPC11U24
LPC1224
LPC1225
LPC1226
LPC1227
LPC1311
LPC1313
LPC1315
LPC1316
LPC1317
LPC1342
LPC1343
LPC1345
LPC1346
LPC1347
LPC1751
LPC1752
LPC1754
LPC1756
LPC1758
LPC1759
LPC1763
LPC1764
LPC1765
LPC1766
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
103
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
LPC1767
LPC1768
LPC1769
LPC1770
LPC1772
LPC1774
LPC1776
LPC1777
LPC1778
LPC1780
LPC1781
LPC1785
LPC1786
LPC1787
LPC1788
LPC1810
LPC1812
LPC1813
LPC1815
LPC1817
LPC1820
LPC1822
LPC1823
LPC1825
LPC1827
LPC1830
LPC1833
LPC1850
LPC1853
LPC1857
LPC4072FBD80
LPC4072FET80
LPC4074FBD144
LPC4074FBD80
LPC4076FBD144
LPC4076FET180
LPC4078FBD100
LPC4078FBD144
LPC4078FBD208
LPC4078FBD80
LPC4078FET180
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
104
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
LPC4078FET208
LPC4088FBD144
LPC4088FBD208
LPC4088FET180
LPC4088FET208
LPC4310FBD144
LPC4310FET100
LPC4320FBD100
LPC4320FBD144
LPC4320FET100
LPC4330FBD144
LPC4330FET100
LPC4330FET180
LPC4330FET256
LPC4333FBD144
LPC4333FET180
LPC4333FET256
LPC4337FBD144
LPC4337FET100
LPC4337FET180
LPC4337FET256
LPC4350FBD208
LPC4350FET180
LPC4350FET256
LPC4353FET180
LPC4353FET256
LPC4357FBD208
LPC4357FET256
LPC810M021FN8
LPC811M001FDH16
LPC812M101FD20
LPC812M101FDH16
LPC812M101FDH20
M0516LAN
M0516ZAN
M052LAN
M052ZAN
M054LAN
M054ZAN
M058LAN
M058ZAN
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
105
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
M1A3P1000
M1A3P1000L
M1A3P250
M1A3P400
M1A3P600
M1A3P600L
M1A3PE3000L
M1AFS1500
M1AFS250
M1AFS600
M1AGL1000
M1AGL250
M1AGL400
M1AGL600
M1AGLE3000
M2S005
M2S010
M2S025
M2S050
M2S080
M2S120
MAX32600
MAX32600P85A
MAX32600P85B
MB9AF102N
MB9AF102R
MB9AF104N
MB9AF104R
MB9AF105NA
MB9AF105RA
MB9AF111K
MB9AF111L
MB9AF111M
MB9AF111N
MB9AF112K
MB9AF112M
MB9AF112N
MB9AF114L
MB9AF114M
MB9AF114N
MB9AF115M
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
106
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MB9AF115N
MB9AF116M
MB9AF116N
MB9AF131L
MB9AF131M
MB9AF131N
MB9AF132K
MB9AF132L
MB9AF132M
MB9AF132N
MB9AF141L
MB9AF141M
MB9AF141N
MB9AF142L
MB9AF142M
MB9AF142N
MB9AF144L
MB9AF144M
MB9AF144N
MB9AF311K
MB9AF311M
MB9AF311N
MB9AF312K
MB9AF312L
MB9AF312M
MB9AF312N
MB9AF314L
MB9AF314M
MB9AF314N
MB9AF315M
MB9AF315N
MB9AF316M
MB9AF316N
MB9AF341L
MB9AF341M
MB9AF341N
MB9AF342L
MB9AF342M
MB9AF342N
MB9AF344L
MB9AF344M
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
107
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MB9AFA31L
MB9AFA31M
MB9AFA31N
MB9AFA32L
MB9AFA32M
MB9AFA32N
MB9AFA41L
MB9AFA41M
MB9AFA41N
MB9AFA42L
MB9AFA42M
MB9AFA42N
MB9AFA44L
MB9AFA44M
MB9AFA44N
MB9AFB41M
MB9AFB41N
MB9AFB42L
MB9AFB42M
MB9AFB42N
MB9AFB44L
MB9AFB44M
MB9AFB44N
MB9BF104N
MB9BF104R
MB9BF105N
MB9BF105R
MB9BF106N
MB9BF106R
MB9BF112N
MB9BF112R
MB9BF114N
MB9BF114R
MB9BF115N
MB9BF115R
MB9BF116R
MB9BF116S
MB9BF116T
MB9BF117S
MB9BF117T
MB9BF118S
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
108
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MB9BF118T
MB9BF164K
MB9BF164L
MB9BF165K
MB9BF165L
MB9BF166K
MB9BF166L
MB9BF166M
MB9BF166N
MB9BF166R
MB9BF167M
MB9BF167N
MB9BF167R
MB9BF168M
MB9BF168N
MB9BF168R
MB9BF216S
MB9BF216T
MB9BF217T
MB9BF218S
MB9BF218T
MB9BF304N
MB9BF304R
MB9BF305N
MB9BF305R
MB9BF306N
MB9BF306R
MB9BF312N
MB9BF312R
MB9BF314N
MB9BF314R
MB9BF315N
MB9BF315R
MB9BF316N
MB9BF316R
MB9BF316S
MB9BF316T
MB9BF317S
MB9BF317T
MB9BF318S
MB9BF318T
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
109
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MB9BF364K
MB9BF364L
MB9BF365K
MB9BF365L
MB9BF366L
MB9BF366M
MB9BF366N
MB9BF366R
MB9BF367M
MB9BF367N
MB9BF367R
MB9BF368M
MB9BF368N
MB9BF368R
MB9BF404N
MB9BF404R
MB9BF405N
MB9BF405R
MB9BF406N
MB9BF406R
MB9BF412N
MB9BF412R
MB9BF414R
MB9BF415N
MB9BF415R
MB9BF416N
MB9BF416R
MB9BF416S
MB9BF416T
MB9BF417S
MB9BF417T
MB9BF418S
MB9BF418T
MB9BF464K
MB9BF464L
MB9BF465K
MB9BF465L
MB9BF466K
MB9BF466L
MB9BF466M
MB9BF466N
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
110
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MB9BF466R
MB9BF467N
MB9BF467R
MB9BF468M
MB9BF468N
MB9BF468R
MB9BF504N
MB9BF504R
MB9BF505N
MB9BF505R
MB9BF506N
MB9BF506R
MB9BF512N
MB9BF512R
MB9BF514N
MB9BF514R
MB9BF515N
MB9BF515R
MB9BF516N
MB9BF516R
MB9BF516S
MB9BF516T
MB9BF517S
MB9BF517T
MB9BF518S
MB9BF518T
MB9BF564K
MB9BF564L
MB9BF565K
MB9BF565L
MB9BF566L
MB9BF566M
MB9BF566N
MB9BF566R
MB9BF567M
MB9BF567N
MB9BF567R
MB9BF568M
MB9BF568N
MB9BF568R
MB9BF616S
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
111
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MB9BF616T
MB9BF617S
MB9BF617T
MB9BF618T
MK10DN128VEX5
MK10DN128VFM5
MK10DN128VFT5
MK10DN128VLF5
MK10DN128VLH5
MK10DN128VMP5
MK10DN32VEX5
MK10DN32VFM5
MK10DN32VFT5
MK10DN32VLF5
MK10DN32VLH5
MK10DN32VMP5
MK10DN512VLK10
MK10DN512VLL10
MK10DN512VLQ10
MK10DN512VMB10
MK10DN512VMC10
MK10DN512VMD10
MK10DN64VEX5
MK10DN64VFM5
MK10DN64VFT5
MK10DN64VLF5
MK10DN64VLH5
MK10DN64VMP5
MK10DX128VEX5
MK10DX128VEX7
MK10DX128VFM5
MK10DX128VFT5
MK10DX128VLF5
MK10DX128VLH5
MK10DX128VLH7
MK10DX128VLK7
MK10DX128VLL7
MK10DX128VLQ10
MK10DX128VMC7
MK10DX128VMD10
MK10DX128VML7
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
112
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MK10DX128VMP5
MK10DX256VEX7
MK10DX256VLH7
MK10DX256VLK7
MK10DX256VLL7
MK10DX256VLQ10
MK10DX256VMC7
MK10DX256VMD10
MK10DX256VML7
MK10DX32VEX5
MK10DX32VFM5
MK10DX32VFT5
MK10DX32VLF5
MK10DX32VLH5
MK10DX32VMP5
MK10DX64VEX5
MK10DX64VEX7
MK10DX64VFM5
MK10DX64VFT5
MK10DX64VLF5
MK10DX64VLH5
MK10DX64VLH7
MK10DX64VLK7
MK10DX64VMC7
MK10DX64VMP5
MK10FN1M0VLQ12
MK10FN1M0VMD12
MK10FX512VLQ12
MK10FX512VMD12
MK11DN512VLK5
MK11DN512VMC5
MK11DX128VMC5
MK11DX256VLK5
MK11DX256VMC5
MK12DN512VLH5
MK12DN512VLK5
MK12DN512VMC5
MK12DX128VLF5
MK12DX128VLH5
MK12DX128VLK5
MK12DX128VMC5
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
113
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
MK12DX256VLF5
MK12DX256VLH5
MK12DX256VLK5
MK12DX256VMC5
MK14LN32VFM4
MK14LN32VFT4
MK14LN32VLF4
MK14LN32VLH4
MK14LN32VLK4
MK14LN64VFM4
MK14LN64VFT4
MK14LN64VLF4
MK14LN64VLH4
MK14LN64VLK4
MK15LN128VFM4
MK15LN128VFT4
MK15LN128VLF4
MK15LN128VLH4
MK15LN128VLK4
MK15LN32VFM4
MK15LN32VFT4
MK15LN32VLF4
MK15LN32VLK4
MK15LN64VFM4
MK15LN64VFT4
MK15LN64VLF4
MK15LN64VLH4
MK15LN64VLK4
MK20DN128VEX5
MK20DN128VFM5
MK20DN128VFT5
MK20DN128VLF5
MK20DN128VLH5
MK20DN128VMP5
MK20DN32VEX5
MK20DN32VFM5
MK20DN32VFT5
MK20DN32VLF5
MK20DN32VLH5
MK20DN32VMP5
MK20DN512VLK10
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
114
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MK20DN512VLL10
MK20DN512VLQ10
MK20DN512VMB10
MK20DN512VMC10
MK20DN512VMD10
MK20DN512ZCAB10
MK20DN64VEX5
MK20DN64VFM5
MK20DN64VFT5
MK20DN64VLF5
MK20DN64VLH5
MK20DN64VMP5
MK20DX128VEX5
MK20DX128VEX7
MK20DX128VFM5
MK20DX128VFT5
MK20DX128VLF5
MK20DX128VLH5
MK20DX128VLH7
MK20DX128VLK7
MK20DX128VLL7
MK20DX128VLQ10
MK20DX128VMC7
MK20DX128VMD10
MK20DX128VML7
MK20DX128VMP5
MK20DX256VEX7
MK20DX256VLH7
MK20DX256VLK10
MK20DX256VLK7
MK20DX256VLL10
MK20DX256VLL7
MK20DX256VLQ10
MK20DX256VMB10
MK20DX256VMC10
MK20DX256VMC7
MK20DX256VMD10
MK20DX256VML7
MK20DX32VEX5
MK20DX32VFM5
MK20DX32VFT5
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
115
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MK20DX32VLF5
MK20DX32VLH5
MK20DX32VMP5
MK20DX64VEX5
MK20DX64VEX7
MK20DX64VFM5
MK20DX64VFT5
MK20DX64VLF5
MK20DX64VLH5
MK20DX64VLH7
MK20DX64VLK7
MK20DX64VMC7
MK20DX64VMP5
MK20FN1M0VLQ12
MK20FN1M0VMD12
MK20FX512VLQ12
MK20FX512VMD12
MK21DN512VMC5
MK21DX128VLK5
MK21DX128VMC5
MK21DX256VLK5
MK21DX256VMC5
MK21FN1M0VLQ12
MK21FN1M0VMC10
MK21FN1M0VMC12
MK21FN1M0VMD10
MK21FN1M0VMD12
MK21FX512VLQ12
MK21FX512VMC10
MK21FX512VMC12
MK21FX512VMD10
MK21FX512VMD12
MK22DN512VLH5
MK22DN512VLK5
MK22DN512VMC5
MK22DX128VLF5
MK22DX128VLH5
MK22DX128VLK5
MK22DX128VMC5
MK22DX256VLF5
MK22DX256VLH5
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
116
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MK22DX256VLK5
MK22DX256VMC5
MK22FN1M0VLH10
MK22FN1M0VLH12
MK22FN1M0VLK10
MK22FN1M0VLK12
MK22FN1M0VLL10
MK22FN1M0VLL12
MK22FN1M0VLQ10
MK22FN1M0VMC10
MK22FN1M0VMC12
MK22FN1M0VMD12
MK22FX512VLH12
MK22FX512VLK12
MK22FX512VLL12
MK22FX512VMC12
MK22FX512VMD12
MK30DN512VLK10
MK30DN512VLL10
MK30DN512VLQ10
MK30DN512VMB10
MK30DN512VMC10
MK30DN512VMD10
MK30DX128VEX7
MK30DX128VLH7
MK30DX128VLK7
MK30DX128VLL7
MK30DX128VLQ10
MK30DX128VMC7
MK30DX128VMD10
MK30DX128VML7
MK30DX256VEX7
MK30DX256VLH7
MK30DX256VLK7
MK30DX256VLL7
MK30DX256VLQ10
MK30DX256VMC7
MK30DX256VMD10
MK30DX256VML7
MK30DX64VEX7
MK30DX64VLH7
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
117
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MK30DX64VLK7
MK30DX64VMC7
MK40DN512VLK10
MK40DN512VLL10
MK40DN512VLQ10
MK40DN512VMB10
MK40DN512VMC10
MK40DN512VMD10
MK40DX128VEX7
MK40DX128VLH7
MK40DX128VLK7
MK40DX128VLL7
MK40DX128VLQ10
MK40DX128VMC7
MK40DX128VMD10
MK40DX128VML7
MK40DX256VEX7
MK40DX256VLH7
MK40DX256VLK7
MK40DX256VLL7
MK40DX256VLQ10
MK40DX256VMC7
MK40DX256VMD10
MK40DX256VML7
MK40DX64VEX7
MK40DX64VLH7
MK40DX64VLK7
MK40DX64VMC7
MK50DN512CLL10
MK50DN512CLQ10
MK50DN512CMC10
MK50DN512CMD10
MK50DX128CEX7
MK50DX128CLH7
MK50DX128CLK7
MK50DX128CLL7
MK50DX128CMB7
MK50DX128CMC7
MK50DX256CLK10
MK50DX256CLK7
MK50DX256CLL10
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
118
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MK50DX256CLL7
MK50DX256CMC10
MK50DX256CMC7
MK50DX256CMD10
MK50DX256CML7
MK51DN256CLQ10
MK51DN256CMD10
MK51DN512CLL10
MK51DN512CLQ10
MK51DN512CMC10
MK51DN512CMD10
MK51DX128CEX7
MK51DX128CLH7
MK51DX128CLK7
MK51DX128CMC7
MK51DX256CLK10
MK51DX256CLK7
MK51DX256CLL10
MK51DX256CLL7
MK51DX256CMC10
MK51DX256CMC7
MK51DX256CML7
MK52DN512CLQ10
MK52DN512CMD10
MK53DN512CLQ10
MK53DN512CMD10
MK53DX256CLQ10
MK53DX256CMD10
MK60DN256VLL10
MK60DN256VLQ10
MK60DN256VMC10
MK60DN256VMD10
MK60DN512VLL10
MK60DN512VLQ10
MK60DN512VMC10
MK60DN512VMD10
MK60DN512ZAB10
MK60DN512ZCAB10
MK60DX256VLL10
MK60DX256VLQ10
MK60DX256VMC10
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
119
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
MK60DX256VMD10
MK60FN1M0VLQ12
MK60FN1M0VLQ15
MK60FN1M0VMD12
MK60FN1M0VMD15
MK60FX512VLQ12
MK60FX512VLQ15
MK60FX512VMD12
MK60FX512VMD15
MK61FN1M0CAA12
MK61FN1M0VMD12
MK61FN1M0VMD15
MK61FN1M0VMJ12
MK61FN1M0VMJ15
MK61FX512VMD12
MK61FX512VMJ12
MK61FX512VMJ15
MK70FN1M0VMJ12
MK70FN1M0VMJ15
MK70FX512VMJ12
MK70FX512VMJ15
MKE02Z16VLC2
MKE02Z16VLD2
MKE02Z16VLD4
MKE02Z32VLC2
MKE02Z32VLC4
MKE02Z32VLD2
MKE02Z32VLD4
MKE02Z32VLH2
MKE02Z32VLH4
MKE02Z32VQH2
MKE02Z32VQH4
MKE02Z64VLC2
MKE02Z64VLD2
MKE02Z64VLD4
MKE02Z64VLH2
MKE02Z64VLH4
MKE02Z64VQH2
MKE04Z128VLD4
MKE04Z128VLH4
MKE04Z128VLK4
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
120
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
MKE04Z128VQH4
MKE04Z64VLD4
MKE04Z64VLH4
MKE04Z64VLK4
MKE04Z64VQH4
MKE06Z128VLD4
MKE06Z128VLH4
MKE06Z128VLK4
MKE06Z128VQH4
MKE06Z64VLD4
MKE06Z64VLH4
MKE06Z64VLK4
MKE06Z64VQH4
MKL02Z16VFG4
MKL02Z16VFK4
MKL02Z16VFM4
MKL02Z32CAF4
MKL02Z32VFG4
MKL02Z32VFK4
MKL02Z32VFM4
MKL02Z8VFG4
MKL04Z16VFK4
MKL04Z16VFM4
MKL04Z16VLC4
MKL04Z16VLF4
MKL04Z32VFK4
MKL04Z32VFM4
MKL04Z32VLC4
MKL04Z32VLF4
MKL04Z8VFK4
MKL04Z8VFM4
MKL04Z8VLC4
MKL05Z16VFK4
MKL05Z16VFM4
MKL05Z16VLC4
MKL05Z16VLF4
MKL05Z32VFK4
MKL05Z32VFM4
MKL05Z32VLC4
MKL05Z32VLF4
MKL05Z8VFK4
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
121
Support
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
MKL05Z8VFM4
MKL05Z8VLC4
MKL14Z32VFM4
MKL14Z32VFT4
MKL14Z32VLH4
MKL14Z32VLK4
MKL14Z64VFM4
MKL14Z64VFT4
MKL14Z64VLH4
MKL14Z64VLK4
MKL15Z128VFM4
MKL15Z128VFT4
MKL15Z128VLH4
MKL15Z128VLK4
MKL15Z32VFM4
MKL15Z32VFT4
MKL15Z32VLH4
MKL15Z32VLK4
MKL15Z64VFM4
MKL15Z64VFT4
MKL15Z64VLH4
MKL15Z64VLK4
MKL16Z128VFM4
MKL16Z128VFT4
MKL16Z128VLH4
MKL16Z256VLH4
MKL16Z256VLK4
MKL16Z32VFM4
MKL16Z32VFT4
MKL16Z32VLH4
MKL16Z64VFM4
MKL16Z64VFT4
MKL16Z64VLH4
MKL24Z32VFM4
MKL24Z32VFT4
MKL24Z32VLH4
MKL24Z32VLK4
MKL24Z64VFM4
MKL24Z64VLH4
MKL24Z64VLK4
MKL25Z128VFM4
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
122
Support
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
MKL25Z128VFT4
MKL25Z128VLH4
MKL25Z32VFM4
MKL25Z32VFT4
MKL25Z32VLH4
MKL25Z32VLK4
MKL25Z64VFM4
MKL25Z64VFT4
MKL25Z64VLH4
MKL25Z64VLK4
MKL26Z128VFM4
MKL26Z128VFT4
MKL26Z128VLH4
MKL26Z128VLL4
MKL26Z128VMC4
MKL26Z256VLH4
MKL26Z256VLK4
MKL26Z256VLL4
MKL26Z256VMC4
MKL26Z32VFM4
MKL26Z32VFT4
MKL26Z32VLH4
MKL26Z64VFM4
MKL26Z64VFT4
MKL26Z64VLH4
MKL34Z64VLH4
MKL34Z64VLL4
MKL36Z128VLH4
MKL36Z128VLL4
MKL36Z128VMC4
MKL36Z256VLH4
MKL36Z256VLL4
MKL36Z256VMC4
MKL36Z256VMP4
MKL36Z64VLH4
MKL36Z64VLL4
MKL46Z128VLH4
MKL46Z128VLL4
MKL46Z128VMC4
MKL46Z256VLH4
MKL46Z256VLL4
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
123
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
MKL46Z256VMC4
MKL46Z256VMP4
MKM14Z128CHH5
MKM14Z64CHH5
MKM33Z128CLH5
MKM33Z128CLL5
MKM33Z64CLH5
MKM33Z64CLL5
MKM34Z128CLL5
MKV10Z16VFM7
MKV10Z16VLC7
MKV10Z16VLF7
MKV10Z32VFM7
MKV10Z32VLC7
MKV10Z32VLF7
MKV30F128VFM10
MKV30F128VLF10
MKV30F128VLH10
MKV30F64VFM10
MKV30F64VLF10
MKV30F64VLH10
MKV31F128VLH10
MKV31F128VLL10
MKV31F256VLH12
MKV31F256VLL12
MKV31F512VLH12
MKV31F512VLL12
MKW01Z128CHN
MKW21D256VHA5
MKW21D512VHA5
MKW22D512VHA5
MKW24D512VHA5
NUC100LC1BN
NUC100LD1BN
NUC100LD2BN
NUC100LD3AN
NUC100LE3AN
NUC100RC1BN
NUC100RD1BN
NUC100RD2BN
NUC100RD3AN
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
124
Support
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
NUC100RE3AN
NUC100VD2AN
NUC100VD3AN
NUC100VE3AN
NUC120LC1BN
NUC120LD1BN
NUC120LD2BN
NUC120LD3AN
NUC120LE3AN
NUC120RC1BN
NUC120RD1BN
NUC120RD2BN
NUC120RD3AN
NUC120RE3AN
NUC120VD2AN
NUC120VD3AN
NUC120VE3AN
NUC122LC1AN
NUC122LD2AN
NUC122RC1AN
NUC122RD2AN
NUC122ZC1AN
NUC122ZD2AN
NUC130LC1BN
NUC130LC1CN
NUC130LD2BN
NUC130LD2CN
NUC130LD3AN
NUC130LE3AN
NUC130LE3CN
NUC130RC1BN
NUC130RC1CN
NUC130RD2BN
NUC130RD2CN
NUC130RD3AN
NUC130RE3AN
NUC130RE3CN
NUC130VD2AN
NUC130VD3AN
NUC130VE3AN
NUC130VE3CN
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
125
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
NUC140LC1BN
NUC140LC1CN
NUC140LD2BN
NUC140LD2CN
NUC140LD3AN
NUC140LE3AN
NUC140LE3CN
NUC140RC1BN
NUC140RC1CN
NUC140RD2BN
NUC140RD2CN
NUC140RD3AN
NUC140RE3CN
NUC140VD2AN
NUC140VD3AN
NUC140VE3AN
NUC140VE3CN
OMAP4430
OMAP4460
OMAP4470
OMAP5430
OMAP5432
OMAPV1035
S3FM02G
S3FN41F
SC000
SC300
SKEAZ128MLH4
SKEAZ128MLK4
SKEAZ64MLH4
SKEAZ64MLK4
SKEAZN16MLC4
SKEAZN32MLC4
SKEAZN32MLH4
SKEAZN64MLC4
SKEAZN64MLH4
SKEAZN8MFK4
SKEAZN8MTG4
STM32F030C6
STM32F030C8
STM32F030F4
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
126
Support
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
STM32F030K6
STM32F030R8
STM32F031C4
STM32F031C6
STM32F031F4
STM32F031F6
STM32F031G4
STM32F031G6
STM32F031K4
STM32F031K6
STM32F042C4
STM32F042C6
STM32F042F4
STM32F042F6
STM32F042G4
STM32F042G6
STM32F042K4
STM32F042K6
STM32F042T6
STM32F050C4
STM32F050C6
STM32F050G6
STM32F050K4
STM32F050K6
STM32F051C4
STM32F051C6
STM32F051C8
STM32F051K4
STM32F051K6
STM32F051K8
STM32F051R4
STM32F051R6
STM32F071CB
STM32F071RB
STM32F071V8
STM32F071VB
STM32F072C8
STM32F072CB
STM32F072R8
STM32F072RB
STM32F072V8
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
127
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
STM32F072VB
STM32F100C4
STM32F100C6
STM32F100C8
STM32F100CB
STM32F100R4
STM32F100R6
STM32F100R8
STM32F100RB
STM32F100RC
STM32F100RD
STM32F100RE
STM32F100V8
STM32F100VB
STM32F100VC
STM32F100VD
STM32F100VE
STM32F100ZC
STM32F100ZD
STM32F100ZE
STM32F101C4
STM32F101C6
STM32F101C8
STM32F101CB
STM32F101R6
STM32F101R8
STM32F101RB
STM32F101RC
STM32F101RD
STM32F101RE
STM32F101RF
STM32F101RG
STM32F101T4
STM32F101T6
STM32F101T8
STM32F101TB
STM32F101V8
STM32F101VB
STM32F101VC
STM32F101VD
STM32F101VE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
128
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
STM32F101VF
STM32F101VG
STM32F101ZC
STM32F101ZD
STM32F101ZE
STM32F101ZF
STM32F101ZG
STM32F102C4
STM32F102C6
STM32F102C8
STM32F102CB
STM32F102R4
STM32F102R6
STM32F102R8
STM32F102RB
STM32F103C4
STM32F103C6
STM32F103C8
STM32F103CB
STM32F103R4
STM32F103R6
STM32F103R8
STM32F103RB
STM32F103RC
STM32F103RD
STM32F103RE
STM32F103RF
STM32F103RG
STM32F103T4
STM32F103T6
STM32F103T8
STM32F103TB
STM32F103V8
STM32F103VB
STM32F103VC
STM32F103VD
STM32F103VE
STM32F103VF
STM32F103VG
STM32F103ZC
STM32F103ZD
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
129
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
STM32F103ZE
STM32F103ZF
STM32F103ZG
STM32F105R8
STM32F105RB
STM32F105RC
STM32F105V8
STM32F105VB
STM32F105VC
STM32F107RB
STM32F107RC
STM32F107VB
STM32F107VC
STM32F205RB
STM32F205RC
STM32F205RE
STM32F205RF
STM32F205RG
STM32F205VB
STM32F205VC
STM32F205VE
STM32F205VF
STM32F205VG
STM32F205ZC
STM32F205ZE
STM32F205ZF
STM32F205ZG
STM32F207IC
STM32F207IE
STM32F207IF
STM32F207IG
STM32F207VC
STM32F207VE
STM32F207VF
STM32F207VG
STM32F207ZC
STM32F207ZE
STM32F207ZF
STM32F207ZG
STM32F215RE
STM32F215RG
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
130
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
STM32F215VE
STM32F215VG
STM32F215ZE
STM32F215ZG
STM32F217IE
STM32F217IG
STM32F217VE
STM32F217VG
STM32F217ZE
STM32F217ZG
STM32F302CB
STM32F302CC
STM32F302RB
STM32F302RC
STM32F302VB
STM32F302VC
STM32F303CB
STM32F303CC
STM32F303RB
STM32F303RC
STM32F303VB
STM32F303VC
STM32F313CC
STM32F313RC
STM32F313VC
STM32F372C8
STM32F372CB
STM32F372CC
STM32F372R8
STM32F372RB
STM32F372RC
STM32F372V8
STM32F372VB
STM32F372VC
STM32F373C8
STM32F373CB
STM32F373CC
STM32F373R8
STM32F373RB
STM32F373RC
STM32F373V8
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
131
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
STM32F373VB
STM32F373VC
STM32F383CC
STM32F383RC
STM32F383VC
STM32F401CB
STM32F401CC
STM32F401RB
STM32F401RC
STM32F401VB
STM32F401VC
STM32F405OE
STM32F405OG
STM32F405RG
STM32F405VG
STM32F405ZG
STM32F407IE
STM32F407IG
STM32F407VE
STM32F407VG
STM32F407ZE
STM32F415OG
STM32F415RG
STM32F415VG
STM32F415ZG
STM32F417IE
STM32F417IG
STM32F417VE
STM32F417VG
STM32F417ZE
STM32F417ZG
STM32F427IG
STM32F427II
STM32F427VG
STM32F427VI
STM32F427ZG
STM32F427ZI
STM32F429BG
STM32F429IG
STM32F429II
STM32F429NG
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
132
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
STM32F429NI
STM32F429VG
STM32F429VI
STM32F429ZG
STM32F429ZI
STM32F437IG
STM32F437II
STM32F437VG
STM32F437VI
STM32F437ZG
STM32F437ZI
STM32F439BG
STM32F439BI
STM32F439IG
STM32F439II
STM32F439NG
STM32F439NI
STM32F439VG
STM32F439VI
STM32F439ZG
STM32F439ZI
STM32L051C6
STM32L051C8
STM32L051K6
STM32L051K8
STM32L051R6
STM32L051R8
STM32L051T6
STM32L051T8
STM32L052C6
STM32L052C8
STM32L052K6
STM32L052K8
STM32L052R6
STM32L052R8
STM32L052T6
STM32L052T8
STM32L053C6
STM32L053C8
STM32L053R6
STM32L053R8
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
133
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
STM32L062K8
STM32L063C8
STM32L063R8
STM32L151C6
STM32L151C8
STM32L151CB
STM32L151QC
STM32L151QD
STM32L151R6
STM32L151RB
STM32L151RC
STM32L151RD
STM32L151V8
STM32L151VB
STM32L151VC
STM32L151VD
STM32L151ZC
STM32L151ZD
STM32L152C6
STM32L152C8
STM32L152CB
STM32L152QC
STM32L152QD
STM32L152R6
STM32L152R8
STM32L152RB
STM32L152RC
STM32L152RD
STM32L152V8
STM32L152VB
STM32L152VC
STM32L152VD
STM32L152ZC
STM32L152ZD
STM32L162QD
STM32L162RD
STM32L162VD
STM32L162ZD
STM32W108C8
STM32W108CB
STM32W108CC
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
134
Support
YES YES YES

YES YES YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
STM32W108CZ
STM32W108HB
TC233LP
TC234LP
TC260D
TC260DU
TC264D
TC264DA
TC264DE
TC264DU
TC265D
TC265DE
TC265DU
TC270T
TC270TP
TC270TU
TC275T
TC275TA
TC275TE
TC275TF
TC275TP
TC275TU
TC277T
TC277TA
TC277TE
TC277TF
TC277TP
TC277TU
TC290T
TC290TP
TC290TU
TC297T
TC297TA
TC297TE
TC297TF
TC297TP
TC297TU
TC298T
TC298TE
TC298TF
TC298TP
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
135
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
ICD
DEBUG
FIRE
ICE
CPU
TC298TU
TC299T
TC299TE
TC299TF
TC299TP
TC299TU
TC2D5T
TC2D5TE
TC2D7T
TC2D7TE
TM4C1230C3PM
TM4C1230D5PM
TM4C1230E6PM
TM4C1230H6PM
TM4C1231C3PM
TM4C1231D5PM
TM4C1231D5PZ
TM4C1231E6PM
TM4C1231E6PZ
TM4C1231H6PGE
TM4C1231H6PM
TM4C1231H6PZ
TM4C1232C3PM
TM4C1232D5PM
TM4C1232E6PM
TM4C1232H6PM
TM4C1233C3PM
TM4C1233D5PM
TM4C1233D5PZ
TM4C1233E6PM
TM4C1233E6PZ
TM4C1233H6PGE
TM4C1233H6PM
TM4C1233H6PZ
TM4C1236D5PM
TM4C1236E6PM
TM4C1236H6PM
TM4C1237D5PM
TM4C1237D5PZ
TM4C1237E6PM
TM4C1237E6PZ
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
136
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
TM4C1237H6PGE
TM4C1237H6PM
TM4C1237H6PZ
TM4C123AE6PM
TM4C123AH6PM
TM4C123BE6PM
TM4C123BE6PZ
TM4C123BH6PGE
TM4C123BH6PM
TM4C123BH6ZRB
TM4C123FE6PM
TM4C123FH6PM
TM4C123GE6PM
TM4C123GE6PZ
TM4C123GH6PGE
TM4C123GH6PM
TM4C123GH6PZ
TM4C123GH6ZRB
TM4C1290NCPDT
TM4C1290NCZAD
TM4C1292NCPDT
TM4C1292NCZAD
TM4C1294KCPDT
TM4C1294NCPDT
TM4C1294NCZAD
TM4C1297NCZAD
TM4C1299KCZAD
TM4C1299NCZAD
TM4C129CNCPDT
TM4C129CNCZAD
TM4C129DNCPDT
TM4C129DNCZAD
TM4C129EKCPDT
TM4C129ENCPDT
TM4C129ENCZAD
TM4C129LNCZAD
TM4C129XKCZAD
TM4C129XNCZAD
TMPM320C1DFG
TMPM330FDWFG
TMPM330FWFG
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
137
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
TMPM330FYFG
TMPM332FWUG
TMPM333FDFG
TMPM333FWFG
TMPM333FYFG
TMPM341FDXBG
TMPM342FYXBG
TMPM343F10XBG
TMPM343FDXBG
TMPM343FEXBG
TMPM360F20
TMPM361F10FG
TMPM361FDFG
TMPM361FYFG
TMPM362F10FG
TMPM363F10FG
TMPM365FYXBG
TMPM366FDFG
TMPM366FDXBG
TMPM366FWFG
TMPM366FWXBG
TMPM366FYFG
TMPM366FYXBG
TMPM367FDFG
TMPM367FDXBG
TMPM367FWFG
TMPM367FWXBG
TMPM367FYFG
TMPM367FYXBG
TMPM368FDFG
TMPM368FDXBG
TMPM369FDFG
TMPM369FDXBG
TMPM369FYFG
TMPM369FYXBG
TMPM36BFYFG
TMPM370FYDFG
TMPM370FYFG
TMPM372FWFG
TMPM372FWUG
TMPM373FWDUG
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
138
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
TRACE
ICD
DEBUG
FIRE
ICE
CPU
TMPM374FWUG
TMPM375FSDMG
TMPM376FDDFG
TMPM376FDFG
TMPM380FWDFG
TMPM380FWFG
TMPM380FYDFG
TMPM380FYFG
TMPM382FSFG
TMPM382FWFG
TMPM382FYFG
TMPM384FDFG
TMPM390FWFG
TMPM395FW
TMS470MF031
TMS470MF042
TMS470MF066
TMS470MSF541
TMS470MSF542
VF12xR
VF32xR
VF52xR
VF6xx
VF7xx
XMC1100-F0008
XMC1100-F0016
XMC1100-F0032
XMC1100-F0064
XMC1200-F0200
XMC1201-F0016
XMC1201-F0032
XMC1201-F0064
XMC1201-F0200
XMC1202-X0032
XMC1301-F0008
XMC1301-F0016
XMC1301-F0032
XMC1302-X0016
XMC1302-X0032
XMC4100
XMC4104
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
Cortex-M Debugger
139
Support
ICD
TRACE
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
POWER
INTEGRATOR
ICD
DEBUG
FIRE
ICE
CPU
XMC4200
XMC4400
XMC4402
XMC4500
XMC4502
XMC4504
XMC4700
YES
YES
YES
YES
YES
YES
YES
Compilers
Language
Compiler
C
C
C
C
C
CARM
ARMCC
ARMCC
REALVIEW-MDK
GCCARM
C
C
C
C
C
C
C
C
C++
C++
C++
C++
C++
C++
Company
ARM Germany GmbH

ARM Ltd.
ARM Ltd.
ARM Ltd.
Free Software
Foundation, Inc.
GCCARM
Free Software
Foundation, Inc.
GREENHILLS-C
Greenhills Software Inc.
ICCARM
IAR Systems AB
ICCV7-ARM
Imagecraft Creations
Inc.
HIGH-C
Synopsys, Inc
TI-C
Texas Instruments
GNU-C
Wind River Systems
D-CC
Wind River Systems
ARM-SDT-2.50
ARM Ltd.
REALVIEW-MDK
ARM Ltd.
GCCARM
Free Software
Foundation, Inc.
GNU
Free Software
Foundation, Inc.
GCCARM
Free Software
Foundation, Inc.
GREENHILLS-C++ Greenhills Software Inc.
Option
Comment
ELF/DWARF
AIF
ELF/DWARF
ELF/DWARF2
COFF/STABS
ELF/DWARF2
ELF/DWARF2
ELF/DWARF2
ELF/DWARF ARM7
ELF/DWARF
COFF
COFF
ELF
ELF/DWARF2
ELF/DWARF2
COFF/STABS
EXE/STABS
ELF/DWARF2
ELF/DWARF2
Cortex-M Debugger
140
Support
Language
Compiler
Company
Option
Comment
C++
C++
C/C++
C/C++
MSVC
HIGH-C++
XCODE
GCC
EXE/CV5
ELF/DWARF
Mach-O
ELF/DWARF
WindowsCE
C/C++
VX-ARM
Microsoft Corporation
Synopsys, Inc
Apple Inc.
HighTec EDV-Systeme
GmbH
TASKING
ELF/DWARF2
Realtime Operation System

Not supported yet.
3rd Party Tool Integrations

The following third parts debuggers can control TRACE32 via the TRACE32 API.
CPU
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW
ALL
CODE::BLOCKS
Host
Windows
Windows
Windows
Code Confidence Ltd
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
Windows
Windows
Windows
Windows
Windows
Windows
Windows
NATIONAL
INSTRUMENTS
Corporation
Open Source
Windows
Windows
Windows
Cortex-M Debugger
141
Support
CPU
Tool
Company
Host
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
GURUCE
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
GuruCE
Windows
ALL
ALL
ARM
Cortex-M Debugger
142
Support
Products
Product Information
OrderNo Code
Text
LA-7844
JTAG Debugger for Cortex-M (ICD)
JTAG-CORTEX_M
supports ARM Cortex-M

trace support ETM Cortex-M via ETB included
supports 5-pin standard JTAG, cJTAG and
Serial Wire Debug Port, (0.4 V - 5 V)
includes software for Windows, Linux and MacOSX
requires Power Debug Module
cJTAG and SWD require
Power Debug Interface USB 2.0/USB 3.0,
Power Debug Ethernet, PowerTrace, Power Debug II
or PowerDebug PRO
LA-7844A
JTAG Debugger License for Cortex-M Add.
JTAG-CORTEX_M-A

please add the base serial number of your debug
cable to your order
LA-7844X
JTAG Debugger Extension for Cortex-M
JTAG-CORTEX_M-X

requires a valid software guarantee or a valid
software maintenance key
cable to your order
LA-7970X
Trace License for ARM (Debug Cable)
TRACE-LICENSE-ARM
Supports for Embedded Trace Buffer (ETB)

cable to your order
LA-3717
Measuring Adapter JTAG 20
MES-AD-JTAG20
Adapter to measure JTAG signals by a logic analyzer

or to disconnect single JTAG lines from the target
LA-3862
ARM Conv. ARM-20, MIPI-34 to Mictor-38
CON-ARM/MIPI34-MIC
Converter to connect the ARM Debug Cable or

the CombiProbe to a Mictor connector on the
target. This is needed if you want to debug
without a Preprocessor and if there is only
a Mictor connector on the target.
The trace signals of the CombiProbe are
connected to the lowest four trace signals of
the Mictor (ETMv3 pinout, continuous mode).
But tracing is normally no use case due to
the bandwidth limitations of the CombiProbe.
Cortex-M Debugger
143
Products
Order Information
Order No.
Code
Text
LA-7844
LA-7844A
LA-7844X
LA-7970X
LA-3717
LA-3862
JTAG-CORTEX_M
JTAG-CORTEX_M-A
JTAG-CORTEX_M-X
TRACE-LICENSE-ARM
MES-AD-JTAG20
CON-ARM/MIPI34-MIC
JTAG Debugger for Cortex-M (ICD)

JTAG Debugger License for Cortex-M Add.
JTAG Debugger Extension for Cortex-M
Trace License for ARM (Debug Cable)
Measuring Adapter JTAG 20
ARM Conv. ARM-20, MIPI-34 to Mictor-38
Additional Options
LA-2101
AD-HS-20
LA-3722
CON-JTAG20-MICTOR
LA-3770
CONV-ARM20/MIPI34
LA-3788
DAISY-CHAINER-JTAG20
LA-7760A EJTAG-MIPS32-A
LA-3756A JTAG-ANDES-A
LA-3778A JTAG-APS-A
LA-3750A JTAG-ARC-A
LA-7747
JTAG-ARM-CON-14-20
LA-3726
JTAG-ARM-CON-20-20
LA-7748
JTAG-ARM-CON-20-TI14
LA-3780
JTAG-ARM-CON-20-TI20
LA-7744X JTAG-ARM10-X
LA-3743X JTAG-ARMV8-A-X
LA-7830A JTAG-C55X-A
LA-7838A JTAG-C6XXX-A
LA-3711A JTAG-CEVAX-A
LA-7843X JTAG-CORTEX-A/R-X
LA-3741A JTAG-HEXAGON-A
LA-7836A JTAG-MMDSP-A
LA-7837A JTAG-NIOS-II-A
LA-7817A JTAG-SH4-A-20
LA-7845A JTAG-STARCORE-20-A
LA-7774A JTAG-TEAK-JAM-20-A
LA-3774A JTAG-TEAKLITE-III-A
LA-7847A JTAG-TMS320C28X-A
LA-3747A JTAG-UBI32-A
LA-3749A JTAG-VSPA-A
LA-3760A JTAG-XTENSA-A
LA-7832A JTAG-ZSP400-A
Adapter Half-Size 20 pin

ARM Converter ARM-20 to Mictor-38
ARM Converter ARM-20 to MIPI-10/20/34
Daisy Chainer 4 JTAG 20
EJTAG Debugger License for MIPS32 Add.
JTAG Debugger License for AndeStar Add.
JTAG Debugger License for APS Add.
JTAG Debugger License for ARC Add.
ARM Converter ARM-20 to/from ARM-14
ARM Converter 2x ARM-20 to ARM-20
Converter ARM-20 to TI-14
Converter ARM-20 to TI-14 or TI-20-Compact
JTAG Debugger Extension for ARM10
JTAG Debugger Ext. Cortex-A (64-bit)
JTAG Debugger License for TMS320C55x Add.
JTAG Debugger License for TMS320C6xxx Add.
JTAG Debugger License for CEVA-X Additional
JTAG Debugger Extension Cortex-A/-R (32-bit)
JTAG Debugger License for Hexagon Add.
JTAG Debugger License for MMDSP
JTAG Debugger License for NIOS-II Add.
JTAG Debugger License for SH2/SH3/SH4 Add.
JTAG Debugger License for StarCore 20 Pin Add
JTAG Debug. for Teak/TeakLite JAM 20 Add.
JTAG Debugger for TeakLite III Add. (ICD)
JTAG Debugger License for TMS320C28X Add.
JTAG/SPI Debugger License for UBI32 Add.
JTAG Debugger License for VSPA Add.
JTAG Debugger License for Xtensa Add.
JTAG Debugger for ZSP400 DSP Core Additional
Cortex-M Debugger
144
Products
Order No.
Code
Text
LA-3712A
LA-7960X
LA-7756A
JTAG-ZSP500-A
MULTICORE-LICENSE
OCDS-TRICORE-A
JTAG Debugger for ZSP500 DSP Core Additional

License for Multicore Debugging
Debugger for TriCore Standard Additional
Cortex-M Debugger
145
Products

Debugger Cortexm

Hochgeladen von

Dokumentinformationen

Copyright

Verfügbare Formate

Dieses Dokument teilen

Dokument teilen oder einbetten

Freigabeoptionen

Stufen Sie dieses Dokument als nützlich ein?

Sind diese Inhalte unangemessen?

Copyright:

Verfügbare Formate

Debugger Cortexm

Hochgeladen von

Copyright:

Verfügbare Formate

Cortex-M Debugger

TRACE32 Online Help

ICD In-Circuit Debugger ................................................................................................................

Processor Architecture Manuals ..............................................................................................

Cortex-M Debugger ..............................................................................................................

Brief Overview of Documents for New Users .................................................................

Quick Start of the JTAG Debugger ..................................................................................

Communication between Debugger and Processor can not be established

Trace Extensions ...............................................................................................................

Cortex-M Specific Implementations ................................................................................

On-chip Breakpoints for Instructions

On-chip Breakpoints for Data

Example for Standard Breakpoints

Cortex-M specific Onchip Commands ............................................................................

SRAM privilege access

Special function register write access

Enable TSTART signal

Enable TSTOP signal

Base address of the trace buffer

Cortex-M specific SYStem Commands ...........................................................................

Define JTAG frequency

Inform debugger about core clock

Configure debugger according to target topology

<parameter> describing the Debugport

<parameter> describing the JTAG scan chain and signal behavior

<parameter> describing a system level TAP Multitap

<parameter> configuring a CoreSight Debug Access Port DAP

<parameter> describing debug and trace Components

<parameter> which are Deprecated

Select the used CPU

Run-time memory access (intrusive)

Define JTAG frequency

Tristate the JTAG port

Run-time memory access

Establish the communication with the target

Select AHB-AP HPROT bits.

ACE enable flag of the AXI-AP

Select AXI-AP CACHE bits.

Select AXI-AP HPROT bits.

Define byte order (endianess)

AHB-AP type of the Cortex-M

No DAP instruction register check

Rearrange DAP memory map

Options for debug port handling

Activate more log messages

Disable software reset

Define disassembler mode

Implicitly use run-time memory access

Allow the debugger to drive nSRST

Disable interrupts while single stepping

Disable interrupts while HLL single stepping

Debugging of an Intel SOC

Disable all interrupts

Go to 'Test-Logic Reset' when locked

Select memory-AP HPROT bits

Enable multiple address spaces support

No check of the running state

Enable overlay support

Mode to handle special power recovery

Halt the core after reset

Generic software reset

Target outputs TDO on rising edge

Select Cortex-M DAP

Use 32-bit access to set breakpoint