Fire c166

FIRE Emulator for C166 Family
TRACE32 Online Help

TRACE32 Directory
TRACE32 Index
TRACE32 Documents ......................................................................................................................
FIRE In-Circuit Emulator ...............................................................................................................
FIRE Target Guides ....................................................................................................................
FIRE Emulator for C166 Family ..............................................................................................
FIRE Emulator for C166 Family ...........................................................................................
Warning ..............................................................................................................................
Quick Start .........................................................................................................................
Configuration .....................................................................................................................
11
Emulation Module ST10R201
11
Adapter C165/C167/ST10
12
Adapter C161RI/PI
14
Adapter C161CI,CS,JI,JC,SI
15
Adapter F276
17
Adapter F252
19
Adapter XCORE
20
Troubleshooting ................................................................................................................
21
Hang-up Conditions
21
Dualport Errors
21
FAQ .....................................................................................................................................
22
Basics .................................................................................................................................
23
Overview
24
Trigger Module
25
Bondout Module
26
CPU Module
27
Emulation Modes
27
SYStem.CpuAccess
SYStem.MemAccess
SYStem.Mode
SYStem.TimeReq
CPU access modes
28
Dualport access
30
Emulation modes
31
Sets dualport update interval
31
General SYStem Settings and Restrictions ....................................................................

SYStem.CPU
SYStem.Option V33
1989-2016 Lauterbach GmbH
32
CPU type selection
33
3.3V power fail detection
33
SYStem.Option IMASKASM
Mask interrupts during assembler step
SYStem.Option IMASKHLL
34
Mask interrupts during HLL step
34
On-circuit emulation
34
On-circuit emulation reset
35
Peripheral reset
35
SYStem.Option ONCE
SYStem.Option ONCEReset
SYStem.RESetOut
SYStem.Option BusType
SYStem.Option WriteLimit
SYStem.Option ExtBus
SYStem.Option
SYStem.Option
Bus mode
36
Write strobe limitation
36
External bus
36
Start-up modes
37
Trace modes
38
SYStem.Option <disable>
Freeze modes
39
SYStem.Option <control>
Startup settings
40
XPER modes
41
SYStem.Option <subsystem>
SYStem.Option TestClock
Clock test
43
SYStem.Option MuxMode
Multiplexed mode
43
Segmentation
43
SYStem.Option CS
Chip selects
44
SYStem.Option Clock
PLL selects
44
ROM size
45
Exception Control .............................................................................................................
46
SYStem.Option SGT
SYStem.Option ROMSIZE
Schematics
46
Reset Line
46
NMI
46
eXception.state
Exception control
47
eXception.Activate
Force exception
47
eXception.Enable
Enable exception
48
eXception.Trigger
Trigger on exception
49
Stimulate exception
50
XPER Mapping and Shadowing .......................................................................................
51
eXception.Pulse
Shadow Memory
51
XBUS Mapping
51
Bondout Trace ...................................................................................................................

Analyzer Modes
52
52
Bondout Trigger and Break System ................................................................................
53
Bondout Breakpoints
53
Bondout Trigger System
54
Trigger on Data Writes
55
Trigger on Data Writes with Data Qualification
55
Selective Trace of Address Areas
55
Selective Trace of Address Areas and Data Qualification
55
Trigger on Execution of Program Line
55
Trace of Local Variables
55
Trigger of Local Variables with Data Qualification
56
Code Flag System .............................................................................................................
57
Code Coverage
57
Flag Mapping
57
C1 Analysis
58
Data Access Flags .............................................................................................................
60
Flag Operation
60
Flag Mapping
60
Bondout Based Dualport Systems ..................................................................................
61
Bondout Shadow Memory
61
Injected Access
61
On-chip Trigger System ....................................................................................................

TrOnchip
62
Trigger onchip
62
Special Functions ..............................................................................................................
63
Memory Classes ................................................................................................................
64
State Analyzer ....................................................................................................................
65
General 80166 Keywords for the Trigger Unit
65
Bondout CPU Keywords for the Trigger Unit
65
Keywords for the Display
66
Bondout Information Display
66
Port Analyzer .....................................................................................................................
67
Port Signals C161PI/C161RI
67
Port Signals C161SI/C161CI/C161JC/C161CS
67
Port Signals C161V/C161K/C161O
68
Port Signals C163
68
Port Signals C164CI
69
Port Signals C164CM/C164SM/C164SV
69
Port Signals C164CR
70
Port Signals C165
70
Port Signals C167/F16X/F26X
71
Port Signals ST10F25X
71
Port Signals ST10F276/ST10F286
72
Port Signals ST10F280/ST10F29X
72
Port Signals XCORE
73
Technical Data ...................................................................................................................

Mechanical Dimensions
75
75
C166
75
ST10
80
Adaptions
84
C166
84
ST10
86
Adapters
88
C166
88
ST10
89
Operation Voltage
94
C166
95
ST10
95
Operation Frequency
96
C166
96
ST10
96
Support ...............................................................................................................................
98
Probes
98
C166
98
ST10
99
Available Tools
101
C166
101
ST10
102
Compilers
103
Realtime Operation Systems
103
3rd Party Tool Integrations
104
Products .............................................................................................................................
Product Information
105
105
C166
105
ST10
106
Order Information
107
C166
107
ST10
107

Version 24-May-2016
F::Data.List
addr/line code
>{
>
>
>
754>
P:008C74>E008
756
P:008C76 E006
P:008C78 E11A
P:008C7A F046
F::PER
Ports
P0L
P0H
DP0L
DP0H
P1L
P1H
DP1L
00
50
00
00
A2
8C
00
label
mnemonic
comment
register int i, primz, k;

int anzahl;
anzahl = 0;
sieve:
mov
r8,#0x0
; anzahl,#0
for ( i = 0 ; i <= SIZE ; flags[ i++ ] = TRUE ) ;

mov
r6,#0x0
; i,#0
F::Register
R0
9088
R1
0
R2
3
R3
3
D7 low D6 low D5
R4
2
D7 low D6 high D5
R5
1
DR7 in
DR6 in
DR5
R6
9088
DR7 in
DR6 in
DR5
R7
0
D7 high D6 low D5
PSW
1
D7 high D6 low D5
SOV 0FA0C
DR7 in
DR6 in
DR5
R8
1
R9
0
R10
2
R11
0
R12
3
R13 614E
R14
0
R15
0
CP 0FC20
SUN 0FC00
DPP0
1
DPP1
0
DPP2
1
DPP3
3
SP 0FBFC
MDH
0
MDL
6
MDC
0
CSP
0
IP
8C74
For general informations about the In-Circuit Debugger refer to the FIRE Users Guide (fire_user.pdf). All
general commands are described in IDE Reference Guide (ide_ref.pdf) and General Reference
Guide.
Warning
NOTE:
Do not connect or remove probe from target while target power is ON.
Power up:
Switch on emulator first, then target
Power down: Switch off target first, then emulator
Warning
Quick Start
Before debugging can be started, the emulator must be configured by software:
Ready to run setup files for most standard compilers can be found on the software CD in the directory /
Demo/c166/Compiler. All setup files are designed to run the emulator stand alone without target hardware.
The following description should make the initial setup (to run the emulator together with the target
hardware) easier. It describes a typical setup with frequently used settings. It is recommended to use the
programming language PRACTICE to create a batch file, which includes all necessary setup commands.
PRACTICE files (*.cmm) can be created with the PRACTICE editor pedit (Command: PEDIT <file name>)
or with any other text editor.
A basic setup file includes the following parts:
1.
Set cpu-type and -mode
2.
Set system options
3.
Select dualport mode (optional)
4.
Set mapper (optional)
5.
Select frequency (optional)
6.
Activate the emulator
7.
Load application file (optional)
8.
Set breakpoints (optional)
9.
Start application
10.
Stop application (optional)
Quick Start
Here a typical example, how to setup the system:

1.
Set cpu-type and -mode options

The command SYStem.CPU is used to select one derivative within a cpu-family and to set its
operation mode.
SYStem.Down
SYStem.CPU C167CR
SYStem.Option BusType NOMUX16
SYStem.Option CS 5
SYStem.Option SGT 16M
SYStem.Option Clock 4.0
SYStem.Option V33 OFF
SYStem.Option CAN1 ON
2.
;
;
;
;
;
;
;
;
switch the system down

select derivative C167CR
set the operation mode NOMUX16
set the number of CS used
set segmentation
set PLL option
select operation voltage
one CAN used
Set system options

The system window controls the CPU specific setup. Please check this window very carefully and set
the appropriate options. Use the ? button in the main tool bar and click to the option check box
(Command: HELP.PICK) to get online help in a pop up window.
SYStem.Option XPerEN ON
SYStem.Option WDTdis ON
3.
; Set XPEN automatically

; Disable watchdog
Select dualport mode (optional)

Dualport allows access to emulation RAM, while emulation is running. This is necessary to display
variables, set breakpoints or display the flag listings while the emulation is running.
System.MemAccess selects how dualport access is done.
SYStem.MemAccess ARAM
;
;
;
;
SYStem.CpuAccess Denied
4.
Select type of dualport access

for the emulation memory
Deny real-time memory access to
all other memories
Set mapper
The mapper controls the memory access of the CPU, this means the use of internal or external
memory.
MAP.RESet
MAP.Ram 0x0--0x7fff
MAP.Intern 0x0--0x7fff
; reset mapper (all external)

; Allocate emulation RAM:
; Select emulation RAM as valid
Quick Start
5.
Select frequency (optional)

The CPU can be clocked by an internal (emulator) or external (target) clock source. If the internal
clock is used, the clock is provides by the VCO of the emulator. The setting of the internal clock is
done by the VCO command.
The current CPU frequency can be displayed in the counter window (Command: Count).
VCO.Fre 5.
6.
; input clock to the EXTAL pin of the cpu is

; set to 5 MHz (only necessary if internal
; clock is used)
Activate the emulator

When the emulator is activated a debug-monitor program is loaded into a hidden emulator memory.
Afterwards, a bondout reset-signal is inactivated and the monitor program starts. This program allows
access to user memory (data.dump, data.list) and cpu-registers, and gives control to start and stop
the emulation.
SYStem.Mode EmulExt
7.
; system works with external target clock
Load application file (optional)

The application can be loaded by various file formats. OMF format is often used to load code and
symbol information. For information about the load command for your compiler see Compiler.
Data.LOAD.Omf keilcl /Puzzled /LowerPATH
8.
; load application file
Set breakpoints (optional)

There are several ways to set breakpoints (Command: Break.Set). Breakpoints can be displayed
using the Break.List command.
Break.Set main /Program
Var.Break.Set flags /Write
Break.Set flags /Write /Data 0x1
9.
;
;
;
;
;
;
set program break on function

main
set write break on variable
flags
set write break with data
definition
Start application
Application can be started with giving a break address. For example go main starts the application
and stops at symbol main.
Go
; run application
Quick Start
10.
Stop application (optional)

Application can be breaked manually by using the BREAK command.
Break
; break application manually
It is recommended to check the following chapters for all questions regarding the correct setup:
Configuration
Troubleshooting
10
Quick Start
Configuration
Emulation Module ST10R201
CPU
Switch Settings
Normal
1 2 3 4 5 6 7 8
OFF
XCORE
1 2 3 4 5 6 7 8
OFF
11
Configuration
Adapter C165/C167/ST10
CPU
Switch Settings
C165
1 2 3 4 5 6 7 8
OFF
C167
1 2 3 4 5 6 7 8
OFF
C167CR
1 2 3 4 5 6 7 8
OFF
C167CS
1 2 3 4 5 6 7 8
OFF
C167SR
1 2 3 4 5 6 7 8
OFF
12
Configuration
R167
1 2 3 4 5 6 7 8
OFF
F167
1 2 3 4 5 6 7 8
OFF
F168
1 2 3 4 5 6 7 8
OFF
F169
1 2 3 4 5 6 7 8
OFF
F269
1 2 3 4 5 6 7 8
OFF
13
Configuration
Adapter C161RI/PI
CPU
Switch Settings
C161RI
1 2 3 4 5 6 7 8
OFF
C161PI
1 2 3 4 5 6 7 8
OFF
14
Configuration
Adapter C161CI,CS,JI,JC,SI
CPU
Switch Settings
C161CI
1 2 3 4 5 6 7 8
OFF
C161CS
1 2 3 4 5 6 7 8
OFF
C161JI
1 2 3 4 5 6 7 8
OFF
C161JS
1 2 3 4 5 6 7 8
OFF
C161SI
1 2 3 4 5 6 7 8
OFF
15
Configuration
C161JC32
1 2 3 4 5 6 7 8
OFF
C161JC16
1 2 3 4 5 6 7 8
OFF
Target Clock for

XTAL3
1 2 3 4 5 6 7 8
OFF
Internal 32 kHz Clock

for XTAL3
1 2 3 4 5 6 7 8
OFF
16
Configuration
Adapter F276
S100
CPU
Switch Settings S100
F27X
11 22 33 44 55 66 77 88
O
O FF FF
17
Configuration
S101
CPU
Switch Settings S101
F276
1 2 3 4 5 6 7 8
OFF
F275
1 2 3 4 5 6 7 8
OFF
F273
1 2 3 4 5 6 7 8
OFF
F272
1 2 3 4 5 6 7 8
OFF
F271
1 2 3 4 5 6 7 8
OFF
18
Configuration
Adapter F252
S100
F252
1 2 3 4 5 6 7 8
OFF
F251
1 2 3 4 5 6 7 8
OFF
19
Configuration
Adapter XCORE
CPU
Switch Settings
XCORE
1 2 3 4 5 6 7 8
OFF
20
Configuration
Troubleshooting
Hang-up Conditions
If you are not able to stop the emulation, there may be some typically reasons:
No READY Signal
This condition occurs, if no READY signal is generated by the target.
WATCHDOG
C167/ST10 CPUs have a watchdog system. Don't forget to disable

the Software Watchdog before starting emulation.
IDLE or PWRDWN
The emulator cant be stopped in idle or power down modes. Some

restrictions depend on bondout errors.
Dualport Errors
Dualport access is made either between bus cycles or by feeding NOP instructions (Bondout CPU). If no
bus cycle is generated (IDLE or SLEEP), an dualport error occurs.
The ROM emulation memory system (DATA, BREAK, FLAG) is always accessible.
21
Troubleshooting
FAQ
Debugging via
VPN
The debugger is accessed via internet/VPN and the performance is very

slow. What can be done to improve debug performance?
The main cause for bad debug performance via internet or VPN are low data
throughput and high latency. The ways to improve performance by the debugger
are limited:
in practice scripts, use "SCREEN.OFF" at the beginning of the script and

"SCREEN.ON" at the end. "SCREEN.OFF" will turn off screen updates.
Please note that if your program stops (e.g. on error) without executing
"SCREEN.OFF", some windows will not
be updated.
"SYStem.POLLING SLOW" will set a lower frequency for target state

checks (e.g. power, reset, jtag state). It will take longer for the debugger to
recognize that the core stopped on a breakpoint.
"SETUP.URATE 1.s" will set the default update frequency of Data.List/

Data.Dump/Variable windows to 1 second (the slowest possible setting).
prevent unneeded memory accesses using "MAP.UPDATEONCE

[address-range]" for RAM and "MAP.CONST [address--range]" for ROM/
FLASH. Address ranged with "MAP.UPDATEONCE" will read the specified
address range only once after the core stopped at a
breakpoint or manual break. "MAP.CONST" will read the specified address
range only once per SYStem.Mode command (e.g. SYStem.UP).
22
FAQ
Basics
The bondout module includes a separate 512K memory for ROM emulation up to 40/50 MHz. The ROM
emulation is supported by a BREAKPOINT memory and a FLAG memory. These memories are dualported
with no limitations.
The C167 processor has an internal XBUS to support different internal peripheral extensions, like CAN or
others. The CPU module has a socket for the original chip of the emulated XBUS derivative.
23
Basics
Overview
The C16x/ST10 specific part of TRACE32-FIRE consists of the following modules:
Trigger Module
Bondout Module
CPU Module
Shadow Memory
C1 Flag
Read Trace
Write Trace
Data Trace
IP Trace
Code Trace
Read Flag
Write Flag
Data Flag
IP Flag
Code Flag
Read Break
Write Break
Data Break
IP Break
Code Break
Trigger Module
Clock
Generator
Mapper
Trace Bus
Trigger System
ROM Bus
Bondout
FLASH
Emulation
Boot Loader
External Bus
XPER Bus
Ports
Monitor RAM
Bondout Module
XPER
Device
Target Adapter
Port
Analyzer
CPU Module
24
Basics
Trigger Module
Trigger Module
Bondout Module
CPU Module
The trigger module provides the follwing features:

Dequeueing System
All signals on the E3 bondout (Infineon) are synchronized. One trace

records is build by corresponding instruction addresses, read and write
operand address, operand data and opcode information.
Trace System
The trace system is build by an 128 bit and 64K deep trace storage. All
bondout signals are sampled by this unit. The trace works as a trace
extension to the trace memory within the FIRE emulation controller.
Break System/
Address Selectors
The break/address selector system consists of:
4 * 1 MByte ranges to set (Operand) Read Breakpoints plus 4 data

selectors
4 * 1 MByte ranges to set (Operand) Write Breakpoints plus 4 data

selectors
8 * 1 MByte ranges to set Instruction Address Breakpoints plus 8

data selectors
2 independent data selectors
Flag System
The flag system is build by
2 * 1 MByte ranges for Operand Read Flags
2 * 1 MByte ranges for Operand Write Flags
2 * 1 MByte ranges for Instruction Execution Flags
2 * 1 MByte ranges for Jump Taken Flags
Shadow Memory
1 MByte shadow memory that can be used for IRAM/XRAM or external

memory.
Trigger Unit
The trigger unit combines address selectors to set trigger points (Alpha,
Beta, Charly and Delta address selector).
Break Unit
The break unit combines breakpoints to directly stop the emulation (Read,
Write breakpoints).
25
Basics
Bondout Module
Trigger Module
Bondout Module
CPU Module
The bondout module is the family specific part of TRACE32-FIRE. Three different bondout modules are
available:
C167-E3
Supports all Infineon devices
ST10201
Supports all STMicroelectronics 5 V devices
ST10202
Supports all STMicroelectronics 3.3 V devices
The bondout modules includes the following components:

Bondout Chip
The bondout chip is either an E3 from Infineon or a ST1020x by

STMicroelectronics. The bondout chip has special trace busses for emulation
of the on-chip FLASH memory and for sampling the internal signals.
Clock Generator
The clock can be driven by the target or the emulator system. The 32 kHz
clock is always driven by the emulator.
Trigger System
Exception
Control
RSTIN and NMI lines can be enabled and stimulated by the emulator system
Exception Trigger
Triggering is possible on asynchronous events like RSTIN, the emulation is

stopped after the trigger event.
Monitor Memory
A hidden memory holds the emulation monitor. The user has no access to
this memory.
Bootloader
The boot loader is stored in a separate memory.
FLASH/ROM
Emulation
Memory
A 512 K memory for ROM/FLASH emulation is placed near to the bondout

chip for high-speed emulation.
Mapper
The mapper defines the mapping of the external emulation memory. Up to

16 MByte of memory can be supported. The FIRE166 emulator uses
asynchronous dualport emulation memory (ARAM).
26
Basics
CPU Module
Trigger Module
Bondout Module
CPU Module
The CPU module is the device specific part of the FIRE-166 emulator.
Target Connection
The target connection is done by 100mil socket rows. Clip-over, solder-on

ore socket adapters can be used.
XPER Socket
The emulation of CAN, IIC, XRAM or ASC1 modules is done by the

production device (standard chip) in XPER emulation mode. Some
adapters have sockets for the chips.
Port Analyzer MUX
All signal pins can be traced by the port analyzer. Buffers to all peripheral
signals are on the adapter board.
Emulation Modes
F::SYStem
system
Down
Up
RESet
Mode
RESet
AloneInt
AloneExt
EmulInt
EmulExt
CPU
C167CR
MemAccess
ARAM
GAP
ROM
Denied
CpuAccess
Enable
Denied
TimeReq
1.000ms
The emulations head can stay in 5 modes. The modes are selected by the SYStem.Up or the
SYStem.Mode command.
27
Basics
SYStem.CpuAccess
CPU access modes
Format:
SYStem.CpuAccess <option>
<option>:
Enable
Denied
Enable
If a dualport read/write access is requested to a non-mapped memory, a spot

point (emulation break and go) is used to access the memory.
Denied
Dualport access via spot point is not possible.
The emulator uses a two stage strategy to realize the best possible dualport access method:
If MemAccess is set to GAP, the emulation controller tries a bus arbitration access as dualport cycle. This
is possible if memory is mapped to internal and on read cycles to shadow memory. Shadow memory
means, that memory is mapped in the emulator (map.ram), but the area is mapped external (map.extern).
On access to external mapped memory and write access to shadow memory the dualport is executed as a
spot point if CpuAccess is enabled. Dualport on access to external mapped memory and write access to
shadow memory is disabled if CpuAccess is disabled.
If MemAccess is set to CPU, the emulation controller uses the injection interface of the CPU to realize the
dualport cycle. The advantage of this method is that all memories, independent on the mapping, can be
used. The CpuAccess switch is ignored if MemAccess is set to CPU.
If MemAccess is set to Denied and CpuAccess is enabled, the emulation controller uses a spot point to
realize the dualport cycle.
If MemAccess is set to Denied and CpuAccess is disabled, dualport access is not possible.
28
Basics
The following table shows how the dualport is realized depending on the used system setting:
Mem
Access
Cpu
Access
Read
Map
Int.
Write
Map
Int.
Read
Shadow
Write
Shadow
Read
Map
Ext.
Write
Map
Ext.
GAP
Enable
gap
gap
gap
spot
spot
spot
GAP
Denied
gap
gap
gap
CPU
Enable
cpu
cpu
cpu
cpu
cpu
cpu
CPU
Denied
cpu
cpu
cpu
cpu
cpu
cpu
Denied
Enable
spot
spot
spot
spot
spot
spot
Denied
Denied
gap: The bus arbitration interface of the CPU is used for dualport access. Application performance is
only slightly influenced.
cpu: The injection interface of the CPU is used for dualport access. Application performance is more
influenced than with GAP mode.
spot: The emulation is breaked, memory access is done via CPU, emulation is continued. Application
performance is most influenced with this method.
29
Basics
SYStem.MemAccess
Dualport access
Format:
SYStem.MemAccess <option>
<option>:
ARAM
GAP
ROM
CPU
MIXed
Denied
GAP
The CPU bus access is stopped by a dedicated bondout signal for performing a
dualport access.
ARAM
The memory access is made directly to the ARAM. The performance is not
influenced. Only memory areas, which are mapped to emulation memory, are
accessible.
ROM
The ROM area can be accessed at every time without any performance
reduction.
CPU
The injected mode access of the ST10 is used for IRAM (0xf000--0xffff) access.
(ST10 only)
MIXed
Combination of all dual port modes.

Realtime memory access to IRAM (0xf000--0xffff) via injection mode of the
CPU (ST10 only).
Realtime memory access to onchip ROM/FLASH via ROM access
Realtime memory access to external memory with access method
ARAM
Denied
Dualport access is not possible while the emulation is running.
Dualport allows access to emulation RAM and onchip ROM/FLASH, while emulation is running. This is
necessary to display variables, set breakpoints or display flag listings while the emulation is running.
Dualport access is only possible on the emulators internal RAM and not on target RAM.
30
Basics
SYStem.Mode
Emulation modes
Format:
SYStem.Mode <mode>
<mode>:
RESet
AloneInt
AloneExt
EmulInt
EmulExt
RESet
The probe is in Reset.
AloneInt
Probe is running with internal clock, no target access possible.
AloneExt
Probe is running with external clock, no target access possible.
EmulInt
Probe is running with internal clock, target access is possible.
EmulExt
Probe is running with external clock, target access is possible.
In active mode, the power of the target is sensed and by switching down the target the emulator changes to
RESET mode. The probe is not supplied by the target. When running without target, the target voltage is
simulated by an internal pull-up resistor. The command SYStem.Up in Stand-alone doesn't work correctly.
Use SYStem.Mode AloneInt to select the correct emulation mode.
SYStem.TimeReq
Sets dualport update interval
Format:
SYStem.TimeReq <time>
<time>:
Update time interval.
31
Basics
General SYStem Settings and Restrictions
F::SYStem
system
Down
Up
RESet
Mode
RESet
AloneInt
AloneExt
EmulInt
EmulExt
CPU
C167CR
MemAccess
ARAM
GAP
ROM
Denied
CpuAccess
Enable
Denied
TimeReq
1.000ms
Option
TraceInt
TraceExt
TraceRes
XVisible
Option
IMASKASM
IMASKHLL
TestClock
V33
Option
ResetMode
OWDDIS
PFLASH
XPerEN
WDTdis
Option
CAN1
CAN2
CAN3
XCAN1
XCAN2
XCAN3
CANOD1
CANOD2
CANOD3
XRAM
XFLASH
Option
DGPT
DGPT2
DADC
DSSC
DASC
DPWM
DCC1
DCC2
DCC6
DCAN1
DCAN2
Option
ResetExt
ONCE
ONCEReset
BOOTSTRAP
WRC
SCReset
ROMSIZE
0x8000
BusType
NOMUX8
CS
5
SGT
16M
CLOCK
0.5
FDGPT
FDADC
FDSSC
FDASC
FDPWM
FDCC1
FDCC2
32
SYStem.CPU
CPU type selection
Format:
SYStem.CPU <cpu >
<cpu>:
C161CS
C161CS
C161JC
C161JI
C161SI
C161RI
C161PI
C161K
C161V
C161O
C163
C164CI
C164CR
C165
C167
C167CR
C167CS
C167SR
R167
F167
F168
F169
F269
The CPU type is selected. The CPU should be selected before activating the emulator and before using the
first PER command. Selections which doesnt fit to the probe used are ignored. Be sure that the switches on
the probe have the correct setting.
SYStem.Option V33
Format:
3.3 V power fail detection
SYStem.Option V33 [ON | OFF]
The emulator has a detection logic to detect a target power fail. This option must be set to on, if a 3.3 V
target is used.
NOTE: The ST10R201 bondout chip is specified for 5 V only.
33
SYStem.Option IMASKASM
Format:
Mask interrupts during assembler step
SYStem.Option IMASKASM [ON | OFF]
If enabled, the interrupt mask bits of the cpu will be set during assembler single-step operations. The
interrupt routine is not executed during single-step operations. After single step the interrupt mask bits are
restored to the value before the step.
SYStem.Option IMASKHLL
Format:
Mask interrupts during HLL step
SYStem.Option IMASKHLL [ON | OFF]
If enabled, the interrupt mask bits of the cpu will be set during HLL single-step operations. The interrupt
routine is not executed during single-step operations. After single step the interrupt mask bits are restored to
the value before the step.
NOTE: By changing the status register through target software, this option can affect the flow of the
target program. Accesses to the interrupt-mask bits will see the wrong values.
SYStem.Option ONCE
Format:
On-circuit emulation
SYStem.Option ONCE [ON | OFF]
Set to ON when using the Clip-Over-Adapter with QFP-Packages. The CPU chip on the target board is set
to tristate on RESET of the target system (Push reset key on your target).
P0.1
Target
ONCEEmulator
10K
34
SYStem.Option ONCEReset
Format:
On-circuit emulation reset
SYStem.Option ONCEReset [ON | OFF]
Some new probes support target reset out of the probe for ONCE mode. The RSTIN input of the CPU must
be an open-drain type. Then the emulator can force an RSTIN signal on the target when an
SYSTEM.MODE or SYSTEM.UP command is executed.
RSTINTarget
Emulator
SYStem.RESetOut
Format:
Peripheral reset
SYStem.RESetOut
The SRST instruction is executed. The RSTOUT line is set to active.
35
Bus mode
Format:
SYStem.Option BusType <mode>
<mode>:
ROMEN
NOMUX8
MUX8
NOMUX16
MUX16
Selects the bus mode for the processor.

ROMEN
The emulator starts in ROM mode. The external bus is disabled after reset. This
operation is valid with the bondout probes only.
NOMUX8
Non-multiplexed 8 bit bus. Port 0L is data port, Port 1 and 4 are address ports.
MUX8
Multiplexed 8 bit bus. Port 0 is used for address and data.
NOMUX16
Non-multiplexed 16 bit bus. Port 0 is data bus, port 1 and 4 are address signals.
MUX16
Multiplexed 16 Bit bus. Port 0 is address and data bus. The upper address lines
(segments) are supported on port 4.
SYStem.Option WriteLimit
Format:
Write strobe limitation
SYStem.Option WriteLimit [ON | OFF]
The write strobe for the emulation RAM is limited. This option should be activated if chip selects with zero
tristate cycles are used.
SYStem.Option ExtBus
Format:
External bus
SYStem.Option ExtBus [ON | OFF]
This option must be activated if bustype ROMEN is selected and external memory is used.
36
SYStem.Option
Start-up modes
Format:
SYStem.Option <mode> [ON | OFF]
<mode>:
BOOTSTRAP
RESETEXT
RESETMODE
WRC
BOOTSTRAP
Bootstrap Mode for C167/ST10.
RESETEXT
The setup after RESET is defined by the target system. The internal setups
(BOOTSTRAP, etc.) are ignored. This mode is valid for the C167 probe only.
Usually the probe can use the reset vector from the target. However some
targets supply this vector on reset of the target only (which must not be the
same time as the reset of the emulator), or the pull-down resistors didnt work
very fine (the buffers on Port 0 of the emulator need some input current). In all
this situations the internal reset vectors should be used:
SYStem.Option ChipSelect
SYStem.Option Clock
SYStem.Option BootsTrap
SYStem.Option WRC
ResetMode
Defines the mode of the RSTIN line on ST10F202.

OFF is unidirectional
ON The RSTIN signal is bidirectional
WRC
Activates the WRL/WRH mode.
37
SYStem.Option
Trace modes
Format:
<mode>:
TraceExt
TraceInt
TraceRes
TRACEEXT
The external bus cycles are traced only.
TRACEINT
The internal bus cycles on the bondout bus are traced. The option can be used
together with the TRACEEXT option to force a mixed trace of internal (bondout)
operations together with external cycles.
TRACERES
The dummy cycles on reset state are trace additionally (Bondout probes only).
This option is only necessary, if the trace should work through reset operation.
The MIXED trace mode (TRACEINT + TRACEEXT) is the most powerful trace function, but delivers a lot of
information that can disturb operations especially for performance and code coverage tests.
38
SYStem.Option <disable>
Freeze modes
Format:
<mode>:
DGPT
DCC1
DCC2
DCC6
DADC
DSSC
DASC
DPWM
DGPT2
FDGPT
FDCC1
FDCC2
FDADC
FDSSC
FDASC
FDPWM
DADC
Disable Analog/Digital Converter (C167,C165) on emulation stop
DGPT
DISPT
Disable General Purpose Timer on emulation stop
DCC1
DCC2
DCC6
Disable CAPCOM1, CAPCOM2, CAPCOM6 on emulation stop (C165, C167)
DSSC
Disable Synchronous Serial Interface on emulation stop (C167,C165)
DASC
Disable Asynchronous Serial Interface on emulation stop (C167,C165)
DPWM
Disable Pulse Width Modulator on emulation stop (C167,C165)
DCAN1
DCAN2
Disable CAN1, CAN2 (CAN Controller) on emulation stop
DGPT2
Disable General Purpose Timer 2 on emulation stop
FDADC
Disable Analog/Digital Converter always
FDGPT
FDISPT
Disable General Purpose Timer always
FDCC1
FDCC2
Disable CAPCOM1, CAPCOM2 always
39
FDSSC
Disable Synchronous Serial Interface always (C167,C165)
FDASC
Disable Asynchronous Serial Interface always (C167,C165)
FDPWM
Disable Pulse Width Modulator always(C167,C165)
FDGPT2
Disable General Purpose Timer 2 always
SYStem.Option <control>
Startup settings
Format:
<mode>:
XPerEN
XVisible
WDTdis
OWDDIS
SCReset
PFLASH
XPerEN
Activates the XPEN bit in the SYSCON register.
XVISIBLE
Activates the XVISIBLE bit in the SYSCON register.
WDTdis
Disables the WDT (WatchDogTimer) while activating the emulator.
OWDDIS
Oscillator Watchdog Disable.
SCReset
Single Chip Reset.
PFLASH
Enable Flash Programming Emulation.
40
SYStem.Option <subsystem>
XPER modes
Format:
<mode>:
CAN1
CAN2
CAN3
XCAN1
XCAN2
XCAN3
CANOD1
CANOD2
CANOD3
XRAM
XFLASH
CAN1
CAN2
CAN3
The CAN Unit is used.
XCAN1
XCAN2
XCAN3
The CAN Unit is used on the XPER chip.
CANOD1
CANOD2
CANOD3
The CAN Unit is used in OpenDrain mode.
XRAM
The XRAM is used on the XPER chip.
XFLASH
The XFLASH is used on the XPER chip.
CANEX1
CAN interrupt 1 (ST10F276/F280/F286 only).

OFF:EX0IN is on P.208
ON: EX0IN is on CAN1_RxD
CANEX2
CAN interrupt2 (ST10F276/F280/F286 only).

ON: EX1IN is on CAN2_RxD
RTCAEX
RTC Alarm Interrupt (ST10F276/F286 only).

ON: EX3IN is on RTC_AlarmIT
RTCSEX
RTC SecIT Interrupt (ST10F276/F286 only).

ON: EX2IN is on RTC_SecIT
41
RTC32K
RTC Clock (ST10F276/F286 only).

OFF: Main Onchip Oscillator
ON 32 kHz
CLKOUT
CLOCKOUT Function (ST10F276/F286 only).

OFF: P.315 port function
ON: CLOCKOUT function
J1850
The J1850 Unit is used on the XPER chip (C161JI/JC only).

OFF: J1850 Unit is not used
P447: Port 4.4 and P4.7 are used for the J1850 periphery
P467: Port 4.6 and P4.7 are used for the J1850 periphery
P754: not supported now
P776: not supported now
42
SYStem.Option TestClock
Clock test
Format:
SYStem.Option TestClock [ON | OFF]
TestClock
The internal clock (ECLK or XTAL2) is checked by the emulator. If

POWERDOWN modes are used, the TESTCLOCK option should be switched
off.
The clock test circuit is always active, if the emulation is stopped.
SYStem.Option MuxMode
Multiplexed mode
Format:
SYStem.Option MuxMode [ON | OFF]
MuxMode
This option defines the timing of the emulation of the external bus. If activated,
the data bus is enabled always half a clock after the falling edge of the ALE
signal. The max. frequency for zero wait state is reduced to 35 MHz.
SYStem.Option SGT
Segmentation
Format:
SYStem.Option SGT <size>
<size>:
OFF
256K
1M
16M
The segmentation must be setup for all non-bondout probes. However it is recommended on the C167
bondout probe for correct address mirroring. The setup defines the reset vector in stand-alone mode.
43
SYStem.Option CS
Chip selects
Format:
SYStem.Option CS <size>
<size>:
0
2
3
5
The reset vector for the chip selects is defined for all C167 probes.
SYStem.Option Clock
PLL selects
Format:
SYStem.Option CLOCK <factor>
<factor>:
0.5
1.0
1.5
2.0
2.5
3.0
4.0
5.0
The reset vector for the PLL multiplier is defined for all C167 probes.
44
SYStem.Option ROMSIZE
Format:
ROM size
SYStem.Option ROMSIZE <value>
The size of the internal ROM can be changed for future derivatives. The default value is 8000H (32K) for
C167. The maximum value is 0x80000.
The ROM is mapped from 0 to 7FFFH and then from 18000H.
0H
ROM/FLASH
8000H
18000H
XRAM
XPER
IRAM
ROM/FLASH
90000H
45
Exception Control
Schematics
Reset Line
Vcc
X.Enable
10K
RSTIN(Target)
RSTIN(CPU)
X.Activate
or
X.Pulse
NMI
VDD
10K
NMI- Target
>=1
X.Enable-
&
NMI- Cpu
X.Pulse-
46
Exception Control
eXception.state
Exception control
Format:
F::x
exception
OFF
ON
RESet
eXception.state
Activate
OFF
RSTIN
NMI
Enable
OFF
ON
RSTIN
NMI
Trigger
OFF
ON
RSTIN
RSTOUT
NMI
TRAP
PEC
BUSIDLE
CPUIDLE
ClockFail
Pulse
eXception.Activate
Pulse
OFF
RSTIN
NMI
Pulse
Single
Width
1.000us
PERiod
OFF
ON
0.000
Force exception
Format:
eXception.Activate RSTIN [ON | OFF]
Format:
eXception.Activate NMI [ON | OFF]
Format:
eXception.Activate OFF
RSTIN
Activates the RSTIN line.
NMI
Activates the NMI line.
OFF
No activation of any exception line.
47
Exception Control
eXception.Enable
Enable exception
Format:
eXception.Enabke RSTIN [ON | OFF]
Format:
eXception.Enable NMI [ON | OFF]
Format:
eXception.Enable OFF
Format:
eXception.Enable ON
RSTIN
Enables the RSTIN line.
NMI
Enables the NMI line.
ON
Enables all exception line.
OFF
Disables all exception lines.
48
Exception Control
eXception.Trigger
Trigger on exception
Format:
eXception.Trigger RSTIN [ON | OFF]
Format:
eXception.Trigger RSTOUT [ON | OFF]
Format:
eXception.Trigger NMI [ON | OFF]
Format:
eXception.Trigger TRAP [ON | OFF]
Format:
eXception.Trigger PEC [ON | OFF]
Format:
eXception.Trigger BUSIDLE [ON | OFF]
Format:
eXception.Trigger CPUIDLE [ON | OFF]
Format:
eXception.Trigger ClockFail [ON | OFF]
Format:
eXception.Trigger Pulse [ON | OFF]
Format:
eXception.Trigger OFF
Format:
eXception.Trigger ON
RSTIN
Trigger on RSTIN line.
RSTOUT
Trigger on RSTOUT line.
NMI
Trigger on NMI line.
TRAP
Trigger on TRAP execution.
PEC
Trigger on PEC transfers.
BUSIDLE
Trigger on BUSIDLE.
CPUIDLE
Trigger on CPUIDLE.
ClockFail
Trigger on Clock fail.
Pulse
Trigger on Pulse line.
49
Exception Control
ON
Trigger on all exception lines.
OFF
No trigger on any exception lines.
eXception.Pulse
Stimulate exception
Format:
eXception.Pulse RSTIN [ON | OFF]
Format:
eXception.Pulse NMI [ON | OFF]
Format:
eXception.Pulse OFF
RSTIN
Trigger on RSTIN line.
NMI
Trigger on NMI line.
OFF
No trigger on any exception line.
50
Exception Control
XPER Mapping and Shadowing
Shadow Memory
Format:
MAP.RAM <range>
The XRAM area can be supported by the emulator. When mapping external memory to this areas, the
memory can be used as shadow memory.
MAP.RAM 0xc000--0xdfff
; activate shadow memory
Dump E:0xc000
; show shadow memory
XBUS Mapping
Format:
MAP.XBus <range>
Format:
MAP.NoXBus <range>
If no XPER device is activated in this range, the XRAM can be supported by the standard emulation memory
(ARAM) of the Trace32-FIRE. The XPER chip selects must be activated, the external bus can stay in single
chip or external bus mode.
MAP.RAM 0xc000--0xdfff
; activate shadow memory
MAP.XBUS 0xc000--0xdfff
; activate for read and write access
Dump E:0xc000
; show shadow memory
51
XPER Mapping and Shadowing
Bondout Trace
The bondout bus delivers information on the instruction pointer, the opcode, the operand data (result or
operation) and the source and destination address. The bondout trace system makes filtering and
dequeueing of this busses to build qualified trace and trigger information. Valid trigger information is
highlighted in the trace.
OAR
Operand Read Address
OAW
Operand Write Address
IP
Instruction Pointer
OPC
Opcode (1st word)
OD
Operand Data (result of operation)
Every operation is shown in on trace frame. The IP address belongs to the source and destination address
and the operand data.
Analyzer Modes
The analyzer can work in 3 different modes:
TraceInt
All cycles inside the CPU are traced, the external bus cycles are not
traced.Address trigger points can be used by the ABX or BBX
breakpoints, or by the internal operand address breakpoints (OAW,
OAR). The bus oriented breakpoints like AlphaBreak cannot be used.
TraceExt
Only external bus cycles are traced. The internal breakpoints (OD, OAR,
etc.) can be used for emulation break, but not for analyzer control. All
external bus breakpoints like AlphaBreak can be used.
TraceInt + TraceExt
(Trace Mixed)
In this mode the internal CPU cycles as well as the external bus cycles
are traced. The standard address markers like AlphaBreak cannot be
used. All address qualification must be done by the special function like
ABX or BBX.
52
Bondout Trace
Bondout Trigger and Break System
Bondout Breakpoints
Format:
Break.Set <address> | <range> [/<mode> ]
<mode>:
Read
Write
Program
Data[.<size>] <data>
<size>:
auto
Byte
Word
<data>:
<value>
<range>
<mask>
The breakpoint system is based on the bondout bus. The breakpoint information is filtered out of the
program counter (instruction pointer), the operand read and write addresses and the resulting data of the
operation. Every breakpoint can be qualified by a data word, byte, range or pattern.
Break.Set flags /write
; set write breakpoint on address

; flags
Break.Set v.range(flags) /write
; set write breakpoint to full range

; of array flags
Break.Set flags /read
; set read breakpoint
Break.Set sieve /program
; set software breakpoint on function

; sieve
Break.Set sieve /p /hard
; set hardware breakpoint on function

; sieve
53
Bondout Trigger System
Format:
Break.Set <address> | <range> [/<mode> ]
<mode>:
Alpha
Beta
Charly
Delta
Read
Write
Program
Data[.<size>] <data>
<size>:
auto
Byte
Word
<data>:
<value>
<range>
<mask>
As all trace records are synchronized, and no prefetches are on the trace bus, triggering and selective
sampling is very easy with the FIRE emulator. By using the program address qualifier, triggering on local
variables is possible. Every qualifier is combined with a data qualifier.
Operand Read Address

OAR Qualifier
Alpha
Beta
Operand Write Addr.

OAW Qualifier
+
Charly
Instruction Address
IP Qualifier
Delta
Data
Data (Result)
Data Qualifier
Data
54
Trigger on Data Writes

addr ab v.range(flags) /write
; defines alphabreak with address of

; array flags
; stop emulator if alphabreak
trigger.program if ab
Trigger on Data Writes with Data Qualification

addr ab v.range(flags) /write /data.byte
0x1
;
;
;
;
trigger.trace if ab
defines alphabreak with

address of array flags
and data value 0x01
stop analyzer if alphabreak
Selective Trace of Address Areas

addr ab v.range(flags) /readwrite
sample if ab
;
;
;
;
defines alphabreak with address of

array flags
trace only access to range of
alphabreak
Selective Trace of Address Areas and Data Qualification

addr ab v.range(flags) /write /data 0x1
sample if ab
;
;
;
;
;

address of array flags
with data qualification
trace only access to range
of alphabreak
Trigger on Execution of Program Line

addr ab sieve /program /hard

; function sieve
; stop analyzer if alphabreak
trigger.trace if ab
Trace of Local Variables

addr ab \\demo\20 /program /hard
sample if ab

; program line 20 in module demo
; sample data if alphabreak
55
Trigger of Local Variables with Data Qualification

addr ab \\demo\20 /program /hard /data 0x1
sample if ab
;
;
;
;
;

address of program line 20
in module demo and data
0x1
sample data if alphabreak
56
Code Flag System
Code Coverage
As prefetches are filtered by the bondout, the code coverage is 100 % valid. The trigger system has 2 areas
for code coverage and C1 analysis with 1 MByte each. There are no restrictions on memory used by the
program code. The code coverage works for external memory, ROM, XRAM and IRAM. There is no
distinguish between BOOT ROM, ROM and external memory.
Flag Mapping
Flag mapping is done by
Format:
MAP.CFlag <addressrange>
Format:
MAP.NoCFlag <addressrange>
MAP.CFlag 0--0xfffff
; supports the 1st MByte with code coverage

; memory
MAP.NoCFlag
; suspends code coverage
57
Code Flag System
C1 Analysis
For the C1 analysis one additional flag is implemented which stores the direction on conditional jumps.
Format:
MAP.CFlag <addressrange>
Format:
MAP.NoCFlag <addressrange>
MAP.CFlag 0--0xfffff
; supports the 1st MByte with code coverage

; memory
MAP.NoCFlag
; suspends code coverage
D.L /CFlag
; shows the code coverage information
D.L /CFlag OK
; shows the code coverage information and marks

; all executed parts of the code
F::d.l func11 /cf

coverage addr/line code
partial
partial
ok
ok
not taken
ok
not taken
ok
not taken
ok
not taken
ok
taken
never
never
never
never
never
label
mnemonic
452 int func11( x )

int x;
{
455
switch ( x )
P:008724 F048
func11:
mov
P:008726 2842
sub
P:008728 2D0E
jmpr
P:00872A 2841
sub
P:00872C 2D0F
jmpr
P:00872E 2841
sub
P:008730 2D10
jmpr
P:008732 2842
sub
P:008734 2D14
jmpr
P:008736 0845
add
P:008738 3D15
jmpr
456
{
457
case 1:
458
x = x+1;
P:00873A 0881
add
459
x = x*2;
r4,r8
r4,#0x2
cc_eq,0x8746
r4,#0x1
cc_eq,0x874C
r4,#0x1
cc_eq,0x8752
r4,#0x2
cc_eq,0x875E
r4,#0x5
cc_ne,0x8764
r8,#0x1
58
Code Flag System
F::d.l func11 /cflag ok

coverage addr/line code
partial
partial
ok
ok
not taken
ok
not taken
ok
not taken
ok
not taken
ok
taken
never
never
never
never
never
never
never
never
never
never
label
mnemonic
452 int func11( x )

int x;
{
455
switch ( x )
P:008724 F048
func11:
mov
P:008726 2842
sub
P:008728 2D0E
jmpr
P:00872A 2841
sub
P:00872C 2D0F
jmpr
P:00872E 2841
sub
P:008730 2D10
jmpr
P:008732 2842
sub
P:008734 2D14
jmpr
P:008736 0845
add
P:008738 3D15
jmpr
456
{
457
case 1:
458
x = x+1;
P:00873A 0881
add
459
x = x*2;
P:00873C 5C18
shl
460
return x*x;
P:00873E 1B88
mulu
P:008740 F2F40EFE
mov
P:008744 DB00
rets
r4,r8
r4,#0x2
cc_eq,0x8746
r4,#0x1
cc_eq,0x874C
r4,#0x1
cc_eq,0x8752
r4,#0x2
cc_eq,0x875E
r4,#0x5
cc_ne,0x8764
r8,#0x1
r8,#0x1
r8,r8
r4,mdl
59
Code Flag System
Data Access Flags
Flag Operation
The data flag system works on all accesses with short and long addresses, in all types of memory. The flag
system has 2 areas for read and write with 1 MByte each. Stack, register and bit operations are not covered
by the flag system
The flag system works with byte resolution
Flag Mapping
Data flag mapping is done by
Format:
MAP.Flag <addressrange>
MAP.ReadFlag <addressrange>
MAP.WriteFlag <addressrange>
Format:
MAP.NoFlag <addressrange>
MAP.NoReadFlag <addressrange>
MAP.NoWriteFlag <addressrange>
MAP.Flag 0--0xfffff
; supports the 1st MByte with read and write flag

; memory
MAP.NoFlag
; suspends flag mapping
60
Data Access Flags
Bondout Based Dualport Systems
Bondout Shadow Memory

The shadow memory works for all short and long addressing modes in the external memory, the XRAM and
IRAM.
Format:
MAP.Shadow <addressrange>
Format:
MAP.NoShadow <addressrange>
The shadow memory is displayed, when the emulation is running. The shadow memory has 1 block with
1MByte length.
Injected Access
The ST10 supports injected dualport access. A memory-memory transfer instruction is feeded to the
instruction queue. This type of dualport access can access internal and external memory, IRAM and XRAM,
as well as memory on the target system.
The injected access mode is used when CPU access is enabled (ST10 only).
NOTE: The ST10R201 cannot work is this mode (silicon bug)
61
Bondout Based Dualport Systems
On-chip Trigger System
TrOnchip
Trigger onchip
Format:
TrOnchip.RomWrite [ON | OFF]
Format:
TrOnchip.MonWrite [ON | OFF]
Format:
TrOnchip.DPRAM [ON | OFF]
RomWrite
Break if illegal write in ROM (ST10 only).
MonWrite
Break if illegal write in MONITOR RAM (ST10 only).
DPRAM
Break if illegal write in DPRAM (outside the range defined) (ST10 only).
62
On-chip Trigger System
Special Functions
DPP ( <offset> )
Returns the memory addressed by the short pointer argument. The lower 14 bits of the argument hold the
offset, the two upper bits the DPP selector.
63
Special Functions
Memory Classes
Memory Class
Description
D
P
Data
Program
X
R
L
B
External Area
ROM/Flash Area
Bootloader Area
Bit
C
E
A
Memory access by CPU

Emulation memory access
Absolute (physical) memory access
64
Memory Classes
State Analyzer
General 80166 Keywords for the Trigger Unit
Bondout CPU Keywords for the Trigger Unit

Input Event
Meaning
BYTE
Byte transfer
EXTREAD
Read access on external bus
EXTWRITE
Write access on external bus
INTCYCLE
Internal cycle
OPFETCH
Opfetch cycle
TRIGOUT0
TRIGOUT1
Word
Word transfer
For not CPU-specific keywords, see non-declarable input variables in ICE/FIRE Analyzer Trigger Unit
Programming Guide (analyzer_prog.pdf).
65
State Analyzer
Keywords for the Display

WR
BHE
NMI
RSTIN
RSTOUT
BUSIDLE
Write Bus Cycle

BHE line
NMI line
Reset Input
Reset Output
No external bus activity for 15 clock cycles
Bondout Specific Items
IEA
IEAY
OPC
OD
OAR
OARY
OAW
OAWY
Instruction Execution Address

Symbolic Instruction Execution Address
Op Code
Result Data
Operand Address Read
same symbolic
Operand Address Write
same symbolic
INSTRFD
IEXTFET
INSTR
IDLE
ROMDATA
CAN
HOLD
BYTBUS
JCLOAD
JCHIT
INJ
REINJ
EXTONLY
PEC
TRAP
Instruction Queue Fetch/Decode

Instruction External Fetch
Instruction Fetch Cycle
CPU kernel in IDLE state
ROM Operand Access
Cancel
Hold
Byte sized bus operation
Jump Cache Load
Jump Cache Hit
Instruction Queue Inject (TRAP,PEC,RESET)
Instruction Queue Reinject
External cycle, bondout information not valid
PEC transfer
TRAP execution
List.Bondout
List.NoDummy
Display internal bus information

Suppress dummy cycles
Bondout Information Display

The information from the bondout busses is displayed in the way like external operations. In mixed trace
mode bondout data display is omitted, when it matches an external cycle. Cycles which sample only internal
bondout information are marked as DUMMY cycles. Cycles which contain only external information have the
EXTONLY flag set. Internal bondout cycles get the timestamp and external line information of the closest
cycle if possible. This allows the display of timestamp and external lines even when the processor has no
external bus activities. Variable accesses can be displayed in HLL form even for register and stack variables
(Var command).
66
State Analyzer
Port Analyzer
Port Signals C161PI/C161RI

Name
Group
Description
ALE
MISC
Strobe ALE
EA-
MISC
Line EA-
NMI-
MISC
Line NMI-
RD-
MISC
Strobe RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobe WR-
P000 .. P015
P0
Port P000 .. P015
P100 .. P115
P1
Port P100 .. P115
P208 .. P215
P2
Port P208 .. P215
P300 .. P313
P3
Port P300 .. P313
P315
P3
Port P315
READY-
P3
Port READY-
P400 .. P406
P4
Port P400 .. P406
P500 .. P503
P5
Port P500 .. P503
P514 .. P515
P5
Port P514 .. P515
P600 .. P607
P6
Port P600 .. P607
XINTR0 .. XINTR7
XINTR
Signal XINTR0 .. XINTR7
Port Signals C161SI/C161CI/C161JC/C161CS

Name
Group
Description
ALE
MISC
Strobe ALE
EA-
MISC
Line EA-
NMI-
MISC
Line NMI-
RD-
MISC
Strobe RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobe WR-
P000 .. P015
P0
Port P000 .. P015
P100 .. P115
P1
Port P100 .. P115
P208 .. P215
P2
Port P208 .. P215
P300 .. P313
P3
Port P300 .. P313
P315
P3
Port P315
READY-
P3
Port READY-
P400 .. P407
P4
Port P400 .. P407
P500 .. P515
P5
Port P500 .. P515
P600 .. P607
P6
Port P600 .. P607
67
Port Analyzer
Name
Group
Description
P704 .. P707
P7
Port P704 .. P707
P900 .. P904
P9
Port P900 .. P904
XINTR0 .. XINTR7
XINTR
Port Signals C161V/C161K/C161O

Name
Group
Description
ALE
MISC
Strobe ALE
EA-
MISC
Signal EA-
NMI-
MISC
Signal NMI-
RD-
MISC
Strobe RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobe WR-
P000 .. P015
P0
Port P000 .. P015
P100 .. P115
P1
Port P100 .. P115
P208 .. P215
P2
Port P208 .. P215
P302 .. P313
P3
Port P302 .. P313
P400 .. P405
P4
Port P400 .. P405
P500 .. P503
P5
Port P500 .. P503
P514 .. P515
P5
Port P514 .. P515
P600 .. P603
P6
Port P600 .. P603
Group
Description
ALE
MISC
Strobe ALE
EA-
MISC
Signal EA-
NMI-
MISC
Signal NMI-
RD-
MISC
Strobe RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobe WR-
P000 .. P015
P0
Port P000 .. P015
P100 .. P115
P1
Port P100 .. P115
P208 .. P215
P2
Port P208 .. P215
P300 .. P313
P3
Port P300 .. P313
P315
P3
Port P315
READY-
P3
Port READY-
P400 .. P407
P4
Port P400 .. P407
Port Signals C163

Name
68
Port Analyzer
Name
Group
Description
P510 .. P515
P5
Port P510 .. P515
P600 .. P607
P6
Port P600 .. P607
XINTR0 .. XINTR7
XINTR
Name
Group
Description
ALE
MISC
Strobe ALE
EA-
MISC
Signal EA-
NMI-
MISC
Signal NMI-
RD-
MISC
Strobe RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobe WR-
P000 .. P015
P0
Port P000 .. P015
P100 .. P115
P1
Port P100 .. P115
P304
P3
Port P304
P306
P3
Port P306
P308 .. P313
P3
Port P308 .. P313
Port Signals C164CI
P315
P3
Port P315
P400 .. P407
P4
Port P400 .. P407
P500 .. P507
P5
Port P500 .. P507
P800 .. P803
P8
Port P800 .. P803
Port Signals C164CM/C164SM/C164SV

Name
Group
Description
ALE
MISC
Strobe ALE
EA-
MISC
Signal EA-
NMI-
MISC
Signal NMI-
RD-
MISC
Strobe RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobe WR-
P000 .. P015
P0
Port P000 .. P015
P100 .. P115
P1
Port P100 .. P115
P2000 .. P2001
P20
Port P2000 .. P2001
P2004 .. P2005
P20
Port P2004 .. P2005
P2008
P20
Port P2008
P2012
P20
Port P2012
P500 .. P507
P5
Port P500 .. P507
P800 .. P803
P8
Port P800 .. P803
69
Port Analyzer
Port Signals C164CR

Name
Group
Description
ALE
MISC
Strobe ALE
EA-
MISC
Signal EA-
NMI-
MISC
Signal NMI-
RD-
MISC
Strobe RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobe WR-
P000 .. P015
P0
Port P000 .. P015
P100 .. P115
P1
Port P100 .. P115
P300 .. P313
P3
Port P300 .. P313
P315
P3
Port P315
READY-
P3
Port READY-
P400 .. P407
P4
Port P400 .. P407
P500 .. P515
P5
Port P500 .. P515
P800 .. P807
P8
Port P800 .. P807
XINTR0 .. XINTR7
XINTR
Name
Group
Description
ALE
MISC
Strobe ALE
EA-
MISC
Line EA-
NMI-
MISC
Line NMI-
RD-
MISC
Strobe RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobe WR-
P000 .. P015
P0
Port P000 .. P015
P100 .. P115
P1
Port P100 .. P115
P208 .. P215
P2
Port P208 .. P215
P300 .. P315
P3
Port P300 .. P315
P400 .. P407
P4
Port P400 .. P407
P510 .. P515
P5
Port P510 .. P515
P600 .. P607
P6
Port P600 .. P607
XINTR0 .. XINTR7
XINTR
Port Signals C165
70
Port Analyzer
Port Signals C167/F16X/F26X

Name
Group
Description
ALE
MISC
Strobe ALE
EA-
MISC
Line EA-
NMI-
MISC
Line NMI-
RD-
MISC
Strobe RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobe WR-
P000 .. P015
P0
Port P000 .. P015
P100 .. P115
P1
Port P100 .. P115
P200 .. P215
P2
Port P200 .. P215
P300 .. P315
P3
Port P300 .. P315
P400 .. P407
P4
Port P400 .. P407
P500 .. P515
P5
Port P500 .. P515
P600 .. P607
P6
Port P600 .. P607
P700 .. P707
P7
Port P700 .. P707
P800 .. P807
P8
Port P800 .. P807
XINTR0 .. XINTR7
XINTR
Name
Group
Description
ALE
MISC
Strobe ALE
EA-
MISC
Line EA-
NMI-
MISC
Line NMI-
RD-
MISC
Strobe RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobe WR-
P000 .. P015
P0
Port P000 .. P015
P100 .. P115
P1
Port P100 .. P115
P202 .. P215
P2
Port P202 .. P215
P300 .. P302
P3
Port P300 .. P302
P306 .. P313
P3
Port P306 .. P313
P315
P3
Port P315
P400 .. P407
P4
Port P400 .. P407
P500 .. P509
P5
Port P500 .. P509
P700 .. P703
P7
Port P700 .. P703
XINTR0 .. XINTR3
XINTR
Port Signals ST10F25X
71
Port Analyzer
Port Signals ST10F276/ST10F286

Name
Group
Description
ALE
MISC
Strobes ALE
EA-
MISC
Signal EA-
NMI-
MISC
Signal NMI-
RD-
MISC
Strobes RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobes WR-
P000 .. P015
P0
Signal P000 .. P015
P100 .. P115
P1
Signal P100 .. P115
P200 .. P215
P2
Signal P200 .. P215
P300 .. P313
P3
Signal P300 .. P313
P315
P3
Signal P315
READY-
P3
Signal READY-
P400 .. P407
P4
Signal P400 .. P407
P500 .. P515
P5
Signal P500 .. P515
P600 .. P607
P6
Signal P600 .. P607
P700 .. P707
P7
Signal P700 .. P707
P800 .. P807
P8
Signal P800 .. P807
XINTR0 .. XINTR3
XINTR
Port Signals ST10F280/ST10F29X

Name
Group
ALE
MISC
Description
Strobes ALE
EA-
MISC
Signal EA-
NMI-
MISC
Signal NMI-
RD-
MISC
Strobes RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobes WR-
XADCINJ
MISC
Signal XADCINJ
P000 .. P015
P0
Port P000 .. P015
P100 .. P115
P1
Port P100 .. P115
XP1000 .. XP1015
P10
Port XP1000 .. XP1015
P200 .. P215
P2
Port P200 .. P215
P300 .. P313
P3
Port P300 .. P313
P315
P3
Port P315
READY-
P3
Port READY-
P400 .. P407
P4
Port P400 .. P407
P500 .. P515
P5
Port P500 .. P515
P600 .. P607
P6
Port P600 .. P607
P700 .. P707
P7
Port P700 .. P707
P800 .. P807
P8
Port P800 .. P807
72
Port Analyzer
Name
Group
Description
XINTR0 .. XINTR3
XINTR
XP900 .. XP915
XP9
Port XP900 .. XP915
XPWM0 .. XPWM3
XPWM
Signal XPWM0 .. XPWM3
Port Signals XCORE

Name
Group
Description
BSCIRX
BSC
Signal BSCIRX
BSCITX
BSC
Signal BSCITX
CAN1RX
CAN
Line CAN1RX
CAN1TX
CAN
Line CAN1TX
CAN2RX
CAN
Line CAN2RX
CAN2TX
CAN
Line CAN2TX
CAN3RX
CAN
Line CAN3RX
CAN3TX
CAN
Line CAN3TX
DIRQ-
DPRAM
Signal DIRQ-
MCS-
DPRAM
Signal MCS-
MDS-
DPRAM
Signal MDS-
MRW-
DPRAM
Signal MRW-
IRQA-
IRQ
Signal IRQA-
IRQBCE-
IRQ
Signal IRQBCE-
IRQDPR-
IRQ
Signal IRQDPR-
IRQJ-
IRQ
Signal IRQJ-
IRQSCI-
IRQ
Signal IRQSCI-
IRQSPI-
IRQ
Signal IRQSPI-
VPWI-
J850
Signal VPWI-
VPWO
J850
Signal VPWO
ALE
MISC
Strobe ALE
NMI-
MISC
Signal NMI-
RB-
MISC
Signal RB-
RD-
MISC
Strobe RD-
RSTIN-
MISC
Reset Line RSTIN-
RSTOUT-
MISC
Reset Line RSTOUT-
WR-
MISC
Strobe WR-
XRAMWR-
MISC
Signal XRAMWR-
P200 .. P209
P2
Port P200 .. P209
P300 .. P313
P3
Port P300 .. P313
P315
P3
Port P315
READY-
P3
Port READY-
P500 .. P515
P5
Port P500 .. P515
P600 .. P607
P6
Port P600 .. P607
P700 .. P703
P7
Port P700 .. P703
PAA0 .. PAA6
PA
Port PAA0 .. PAA6
PAB0 .. PAB6
PA
Port PAB0 .. PAB6
PB0 .. PB4
PB
Port PB0 .. PB4
PC0 .. PC7
PC
Port PC0 .. PC7
PD00 .. PD15
PD
Port PD00 .. PD15
73
Port Analyzer
Name
Group
Description
PE0 .. PE7
PE
Port PE0 .. PE7
MISO
SPI
Signal MISO
MOSI
SPI
Signal MOSI
SCK
SPI
Signal SCK
SS-
SPI
Signal SS-
XINTR0 .. XINTR7
XINTR
74
Port Analyzer
Technical Data
Mechanical Dimensions
C166
Dimension
LA-9610
M-ST10/C167
75
Technical Data
Dimension
LA-9611
M-C161CS
LA-9612
M-C161PI
76
Technical Data
Dimension
LA-9613
M-C164CI
LA-9614
M-C164CR
77
Technical Data
Dimension
LA-9616
M-C161V
LA-9617
M-C163
78
Technical Data
Dimension
LA-9581
M-C164CM
750
2150
4250
ET64-QF64
PIN1
FRONT VIEW
5000
TOP VIEW
ALL DIMENSIONS IN MILS
450
4225
6875
6500
79
Technical Data
ST10
Dimension
LA-9610
M-ST10/C167
LA-9617
M-C163
80
Technical Data
Dimension
LA-9618
M-ST10F280
4250
5000
FRONT VIEW
TOP VIEW
750
1838
PIN1 TCON-200
450
LA-9615
4225
6500
6875
M-ST10/XCORE
81
Technical Data
Dimension
LA-9582
M-ST10F276
100-QF06 PIN1
750
450
LA-9584
3650
3850
144-QF10 PIN1
1800
1650
4250
5000
FRONT VIEW
TOP VIEW
6500
6875
M-ST10F296
750
1900
PIN1 TCON 200
FRONT VIEW
4250
5000
TOP VIEW
450
4300
6500
6875
82
Technical Data
Dimension
LA-9585
M-ST10F252
4250
5000
FRONT VIEW
TOP VIEW
750
1900
PIN1 100QF49
450
3850
6500
6875
LA-9609
BGA233-AI-ST10F280
TOP VIEW
2100
1750
A1
50
4X100
SIDE VIEW
425
SAMTEC:TFM-125-32-S-D-LC
LA-9609
450
OOOOOOOOOOOOOOOOOOOO
AI-9603
ALL DIMENSIONS IN 1/1000 INCH
83
Technical Data
Adaptions
C166
CPU
Adaption
C161PI
C161RI
C165
ET100-QF06
C161PI
C163
C163-16F
C163-24D
C165
ET100-QF49
84
Technical Data
CPU
Adaption
C161CI
C161SI
C161XX
ET128-QF63
C167
C167C
C167CR
C167CS
C167CW
C167SR
ET144-QF10
85
Technical Data
CPU
Adaption
C161K
C161O
C161S
C161V
C164CI
C164CL
ET80-QF14
ST10
CPU
Adaption
ST10F163
ST10F251
ST10F251M
ST10F252
ST10F252M
ST10R163
ST10R165
ST10R251
ST10R252
ET100-QF49
86
Technical Data
CPU
Adaption
ST10F167
ST10F168
ST10F169
ST10F269
ST10F271
ST10F271B
ST10F271M
ST10F272
ST10F272B
ST10F272M
ST10F273
ST10F273M
ST10F275
ST10F276
ST10R167
ST10R271
ST10R272
ET144-QF10
ST10F269
ST10F271
ST10F271B
ST10F271M
ST10F272
ST10F272B
ST10F272M
ST10F273
ST10F273M
ST10F275
ST10F276
ST10R271
ST10R272
ET144-QF63
87
Technical Data
CPU
Adaption
ST10R172L
ST10R262
ST10R272L
ET100-QF49
Adapters
C166
Not necessary.
88
Technical Data
ST10
Socket CPU
Adapter
ET100-QF49
YA-1091 ET100-EYA-QF49
Emul. Adapter for YAMAICHI socket ET100-QF49
ST10F163
ST10F251
ST10F251M
ST10F252
ST10F252M
ST10R163
ST10R165
ST10R251
ST10R252
8
6
56
SIDE VIEW
66
18
14
TOP VIEW (all dimensions in mm)
89
Technical Data
Socket CPU
Adapter
ET144-QF10
ET-1090 ET144-SET-QF10
Surface Mountable Adapter for ET144-QF10
ST10F167
ST10F168
ST10F169
ST10F269
ST10F271
ST10F271B
ST10F271M
ST10F272
ST10F272B
ST10F272M
ST10F273
ST10F273M
ST10F275
ST10F276
ST10R167
ST10R271
ST10R272
21
SIDE VIEW
::
::
::
::
::
::
::
::
::::::::::::::
::
::
::
::
::
::
::
::
::::::::::::::
46
51
ET144-QF10
ST10F167
ST10F168
ST10F169
ST10F269
ST10F271
ST10F271B
ST10F271M
ST10F272
ST10F272B
ST10F272M
ST10F273
ST10F273M
ST10F275
ST10F276
ST10R167
ST10R271
ST10R272
8
6
69
SIDE VIEW
69
13
13
90
Technical Data
Socket CPU
Adapter
ET144-QF10
LA-1096 ET144-FP144
Adapter ET144 to Footprint AMP Sockets
ST10F167
ST10F168
ST10F169
ST10F269
ST10F271
ST10F271B
ST10F271M
ST10F272
ST10F272B
ST10F272M
ST10F273
ST10F273M
ST10F275
ST10F276
ST10R167
ST10R271
ST10R272
8
9
69
SIDE VIEW
TARGET
69
15
15
91
Technical Data
Socket CPU
Adapter
ET144-QF10
TO-1300 ET144-ETO-QF10
Emul. Adapter for T0 socket ET144-QF10
450
110
108
35
36
2500
74
109
143
1
107
100
TOP VIEW
73
100
450
144
2700
71
37
38
360
ST10F167
ST10F168
ST10F169
ST10F269
ST10F271
ST10F271B
ST10F271M
ST10F272
ST10F272B
ST10F272M
ST10F273
ST10F273M
ST10F275
ST10F276
ST10R167
ST10R271
ST10R272
2500
2700
ALL DIMENSIONS
IN 1/1000 INCH
775
4 X SAMTEC:
TSW-118-D-...
72
TET-SOCKET
580
TET-ADAPTER
TARGET
92
Technical Data
Socket CPU
Adapter
ET144-QF63
ST10F269
ST10F271
ST10F271B
ST10F271M
ST10F272
ST10F272B
ST10F272M
ST10F273
ST10F273M
ST10F275
ST10F276
ST10R271
ST10R272
8
6
69
SIDE VIEW
69
17
18
93
Technical Data
Socket CPU
Adapter
ET100-QF49
ST10R172L
ST10R262
ST10R272L
8
6
56
SIDE VIEW
66
18
14
Operation Voltage
This list contains information on probes available for other voltage ranges. Probes not noted here supply an
operation voltage range of 4.5 5.5 V.
94
Technical Data
C166
CPU
Module
Adapter
Voltage Range
C161CI
C161K
C161O
C161PI
C161RI
C161S
C161SI
C161V
C161XX
C163
C163-16F
C163-24D
C164CI
C164CL
C164CM
C164SM
C164SV
C165
C167
C167C
C167CR
C167CS
C167CW
C167SR
LA-9611
LA-9616
LA-9616
LA-9612
LA-9612
LA-9616
LA-9611
LA-9616
LA-9611
LA-9617
LA-9617
LA-9617
LA-9613
LA-9613
LA-9581
LA-9581
LA-9581
LA-9610
LA-9610
LA-9610
LA-9610
LA-9610
LA-9610
LA-9610
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
3.0 .. 5.5 V
CPU
Module
Adapter
Voltage Range
ST10R172L
ST10R262
ST10R272L
LA-9610
LA-9610
LA-9610
3.0 .. 3.6 V
3.0 .. 3.6 V
3.0 .. 3.6 V
ST10
95
Technical Data
Operation Frequency
C166
Module
CPU
F-W010
F-W110
S-W010
S-W110
CHIP
LA-9611
LA-9616
LA-9616
LA-9612
LA-9612
LA-9616
LA-9611
LA-9616
LA-9611
LA-9617
LA-9617
LA-9617
LA-9613
LA-9613
LA-9581
LA-9581
LA-9581
LA-9610
LA-9610
LA-9610
LA-9610
LA-9610
LA-9610
LA-9610
C161CI
C161K
C161O
C161PI
C161RI
C161S
C161SI
C161V
C161XX
C163
C163-16F
C163-24D
C164CI
C164CL
C164CM
C164SM
C164SV
C165
C167
C167C
C167CR
C167CS
C167CW
C167SR
20.0+
16.0+
16.0+
25.0+
16.0+
25.0+
20.0+
16.0+
20.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
40.0
25.0+
25.0+
20.0+
16.0+
16.0+
25.0+
16.0+
25.0+
20.0+
16.0+
20.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
40.0+
25.0+
25.0+
20.0+
16.0+
16.0+
25.0+
16.0+
25.0+
20.0+
16.0+
20.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
31.6
25.0+
25.0+
20.0+
16.0+
16.0+
25.0+
16.0+
25.0+
20.0+
16.0+
20.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
25.0+
40.0+
25.0+
25.0+
20.0
16.0
16.0
25.0
16.0
25.0
20.0
16.0
20.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
25.0
40.0
25.0
25.0
Module
CPU
F-W010
F-W110
S-W010
S-W110
CHIP
LA-9617
LA-9610
LA-9610
LA-9610
LA-9585
ST10F163
ST10F167
ST10F168
ST10F169
ST10F251
40.0
40.0
40.0
40.0
40.0
50.0+
50.0+
50.0+
50.0+
48.0+
28.6
28.6
28.6
28.6
28.6
50.0+
50.0+
50.0+
50.0+
48.0+
50.0
50.0
50.0
50.0
48.0
TRACE HEAD
RAM
ST10
TRACE HEAD
RAM
96
Technical Data
Module
CPU
F-W010
F-W110
S-W010
S-W110
CHIP
LA-9585
LA-9585
LA-9585
LA-9610
LA-9582
LA-9582
LA-9582
LA-9582
LA-9582
LA-9582
LA-9582
LA-9582
LA-9582
LA-9582
LA-9618
LA-9584
LA-9584
LA-9617
LA-9610
LA-9610
LA-9585
LA-9585
LA-9582
LA-9582
LA-9615
LA-9610
LA-9610
LA-9610
ST10F251M
ST10F252
ST10F252M
ST10F269
ST10F271
ST10F271B
ST10F271M
ST10F272
ST10F272B
ST10F272M
ST10F273
ST10F273M
ST10F275
ST10F276
ST10F280
ST10F293
ST10F296
ST10R163
ST10R165
ST10R167
ST10R251
ST10R252
ST10R271
ST10R272
XCORE
ST10R172L
ST10R262
ST10R272L
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
40.0
25.0+
40.0
40.0
40.0
48.0+
48.0+
48.0+
50.0+
50.0+
50.0+
50.0+
50.0+
50.0+
50.0+
50.0+
50.0+
50.0+
50.0+
40.0+
50.0+
50.0+
50.0+
50.0+
50.0+
48.0+
48.0+
50.0+
50.0+
25.0+
50.0+
50.0+
80.0
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
28.6
25.0+
28.6
28.6
28.6
48.0+
48.0+
48.0+
50.0+
50.0+
50.0+
50.0+
50.0+
50.0+
50.0+
50.0+
50.0+
50.0+
50.0+
40.0+
50.0+
50.0+
50.0+
50.0+
50.0+
48.0+
48.0+
50.0+
50.0+
25.0+
50.0+
50.0+
57.1
48.0
48.0
48.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
50.0
40.0
50.0
50.0
50.0
50.0
50.0
48.0
48.0
50.0
50.0
25.0
50.0
50.0
80.0
TRACE HEAD
RAM
97
Technical Data
Support
Probes
C166
LA-9604
LA-9611
C161CI
ET128-QF63 3.0..5.5V
C161K
ET80-QF14
3.0..5.5V
C161O
ET80-QF14
3.0..5.5V
C161PI
C161PI
ET100-QF06 3.0..5.5V
ET100-QF49 3.0..5.5V
C161RI
ET100-QF06 3.0..5.5V
LA-9616
C161S
ET80-QF14
LA-9611
C161SI
ET128-QF63 3.0..5.5V
LA-9616
C161V
ET80-QF14
LA-9611
C161XX
ET128-QF63 3.0..5.5V
C163
ET100-QF49 3.0..5.5V
C163-16F
ET100-QF49 3.0..5.5V
C163-24D
ET100-QF49 3.0..5.5V
LA-9616
LA-9612
LA-9617
3.0..5.5V
3.0..5.5V
C164CI
ET80-QF14
3.0..5.5V
C164CL
ET80-QF14
3.0..5.5V
C164CM
ET64-QF64
3.0..5.5V
C164SM
ET64-QF64
3.0..5.5V
C164SV
ET64-QF64
3.0..5.5V
LA-9613
LA-9581
LA-9610
C165
C165
ET100-QF06 3.0..5.5V
ET100-QF49 3.0..5.5V
C167
ET144-QF10 3.0..5.5V
C167C
ET144-QF10 3.0..5.5V
C167CR
ET144-QF10 3.0..5.5V
C167CS
ET144-QF10 3.0..5.5V
C167CW
ET144-QF10 3.0..5.5V
C167SR
ET144-QF10 3.0..5.5V
98
Support
ST10
LA-9600
LA-9617
LA-9610
ST10F163
ET100-QF49
ST10F167
ET144-QF10
ST10F168
ET144-QF10
ST10F169
ET144-QF10
ST10F251
ET100-QF49
ST10F251M
ET100-QF49
ST10F252
ET100-QF49
ST10F252M
ET100-QF49
ST10F269
ST10F269
ET144-QF10
ET144-QF63
ST10F271
ST10F271
ET144-QF10
ET144-QF63
ST10F271B
ST10F271B
ET144-QF10
ET144-QF63
ST10F271M
ST10F271M
ET144-QF10
ET144-QF63
ST10F272
ST10F272
ET144-QF10
ET144-QF63
ST10F272B
ST10F272B
ET144-QF10
ET144-QF63
ST10F272M
ST10F272M
ET144-QF10
ET144-QF63
ST10F273
ST10F273
ET144-QF10
ET144-QF63
ST10F273M
ST10F273M
ET144-QF10
ET144-QF63
ST10F275
ST10F275
ET144-QF10
ET144-QF63
ST10F276
ST10F276
ET144-QF10
ET144-QF63
ST10F280
LAF280
ST10F293
LAF280
ST10F296
LAF280
ST10R163
ET100-QF49
LA-9585
LA-9610
LA-9582
LA-9618
LA-9584
LA-9617
99
Support
LA-9600
ST10R165
ET100-QF49
ST10R167
ET144-QF10
ST10R251
ET100-QF49
ST10R252
ET100-QF49
ST10R271
ST10R271
ET144-QF10
ET144-QF63
ST10R272
ST10R272
ET144-QF10
ET144-QF63
XCORE
LAXCORE
LA-9610
LA-9585
LA-9582
LA-9615
LA-9601
LA-9610
ST10R172L
ET100-QF49 3.0..3.6V
ST10R262
ET100-QF49 3.0..3.6V
ST10R272L
ET100-QF49 3.0..3.6V
100
Support
Available Tools
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
ICD
MONITOR
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
DEBUG
ICE
C161CI
C161K
C161O
C161PI
C161RI
C161S
C161SI
C161V
C161XX
C163
C163-16F
C163-24D
C164CI
C164CL
C164CM
C164SM
C164SV
C165
C167
C167C
C167CR
C167CS
C167CW
C167SR
FIRE
CPU
C166
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
101
Support
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
INSTRUCTION
SIMULATOR
POWER
INTEGRATOR
ICD
TRACE
YES YES
YES YES
YES YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES YES
YES YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
ICD
MONITOR
ICE
ST10F163
ST10F167
ST10F168
ST10F169
ST10F251
ST10F251M
ST10F252
ST10F252M
ST10F269
ST10F271
ST10F271B
ST10F271M
ST10F272
ST10F272B
ST10F272M
ST10F273
ST10F273M
ST10F275
ST10F276
ST10F280
ST10F293
ST10F296
ST10R163
ST10R165
ST10R167
ST10R172L
ST10R251
ST10R252
ST10R262
ST10R271
ST10R272
ST10R272L
XCORE
ICD
DEBUG
CPU
FIRE
ST10
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
YES
102
Support
Compilers
Language
Compiler
Company
Option
C
C
C
C166
XC16X/ST10
GNU-GCC166
EOMF-166
ELF/DWARF
DBX
C
C++
C166
GNU-CPP166
C++
CP166
ARM Germany GmbH

Cosmic Software
HighTec EDV-Systeme
GmbH
TASKING
HighTec EDV-Systeme
GmbH
TASKING
Comment
IEEE
DBX
IEEE
Realtime Operation Systems

Name
Company
Comment
ARTX-166
CMX-RTX
Elektrobit tresos
Erika
Nucleus PLUS
osCAN
OSE Basic
OSE Epsilon
OSEK
ProOSEK
PXROS
RTX166/-tiny
RTXC 3.2
RTXC Quadros
Rubus OS
SDT-Cmicro
uC/OS-II
ARM Germany GmbH

CMX Systems Inc.
Elektrobit Automotive GmbH
Evidence
Mentor Graphics Corporation
Vector
Enea OSE Systems
Enea OSE Systems
Elektrobit Automotive GmbH
HighTec EDV-Systeme GmbH
ARM Germany GmbH
Quadros Systems Inc.
Quadros Systems Inc.
Articus Systems AB
IBM Corp.
Micrium Inc.
via ORTI
via ORTI
via ORTI
(OS166)
(OS166), 3.x
via ORTI
via ORTI
2.0 to 2.92
103
Support
3rd Party Tool Integrations

CPU
Tool
Company
ALL
ALL
ALL
ADENEO
X-TOOLS / X32
CODEWRIGHT
ALL
CODE CONFIDENCE
TOOLS
CODE CONFIDENCE
TOOLS
EASYCODE
ECLIPSE
RHAPSODY IN MICROC
RHAPSODY IN C++
CHRONVIEW
LDRA TOOL SUITE
UML DEBUGGER
Adeneo Embedded
blue river software GmbH
Borland Software
Corporation
Code Confidence Ltd
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
C166
ATTOL TOOLS
VISUAL BASIC
INTERFACE
LABVIEW
CODE::BLOCKS
C++TEST
RAPITIME
DA-C
TRACEANALYZER
SIMULINK
TA INSPECTOR
UNDODB
VECTORCAST UNIT
TESTING
VECTORCAST CODE
COVERAGE
WINDOWS CE PLATF.
BUILDER
SDT CMICRO
Host
Windows
Windows
Windows
Code Confidence Ltd
Linux
EASYCODE GmbH
Eclipse Foundation, Inc
IBM Corp.
IBM Corp.
Inchron GmbH
LDRA Technology, Inc.
LieberLieber Software
GmbH
MicroMax Inc.
Microsoft Corporation
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Windows
NATIONAL
INSTRUMENTS
Corporation
Open Source
Parasoft
Rapita Systems Ltd.
RistanCASE
Symtavision GmbH
The MathWorks Inc.
Timing Architects GmbH
Undo Software
Vector Software
Windows
Windows
Windows
Windows
Windows
Windows
Windows
Linux
Windows
Vector Software
Windows
Windows
Windows
IBM Corp.
Windows
104
Support
Products
Product Information
C166
OrderNo Code
Text
LA-9604
FIRE-166
Bondout Module for C166 Family,

512K Flash Emulation,
33 MHz operation with E3 bondout
requires FIRE-ARAM
requires Trigger Module for
ST10/C161..C167 (LA-9602)
LA-9602
Trigger Module for ST10 / C161..C167
FIRE-166-TRIGG-64K
128 Trace Channels, Bondout Trigger System,

Bondout Flag System, Shadow RAM, 64K Trace
LA-9630
Trigger Module for ST10/C16x 512K Trace
FIRE-166-TRIGG-512K

LA-9610
Module for ST10/C167
M-ST10/C167
Module for TQFP100 and PQFP144

supports ST10x163, ST10R165, ST10x167, ST10x168,
ST10xx69, C163, C165, C167xx,
ST10R172L, ST10R262, ST10272L
Connectors for ET100-QF06 and ET-144
LA-9611
Module for C161CI/SI/JI/CS
M-C161CS
Module for TQFP128,

supports C161CI, SI, JI, CS, JC
LA-9612
Module for C161RI/PI
M-C161PI
Module for ET100-QF49,

supports C161PI, RI
LA-6618
CPU Adapter C161SI/CI/CS
CPU_C161
CPU adapter for LA-6613,

without CPU
LA-9613
Module for C164CI
M-C164CI

supports C164CI, C164CL
LA-9614
Module for C164CR
M-C164CR

supports C164CR
LA-9616
Module for C161S/V/K/O
M-C161V
Module for ET80-QF14, ET80-QF18,

supports C161S, C161V, C161K and C161O
LA-9617
Module for C163
M-C163

supports C163, 3.3 and 5 V
LA-9581
Module for C164CM
M-C164CM

supports C164CM, C164SM, C164SV
105
Products
ST10
OrderNo Code
Text
LA-9600
FIRE Emulator for ST10-201
FIRE-ST10-201
Bondout Module for ST10,

512K Flash Emulation, 5 Volt,
50 MHz Operation with ST201 Bondout
requires FIRE-ARAM
requires Trigger Module for
ST10/C161..C167 (LA-9602)
LA-9602
FIRE-166-TRIGG-64K

LA-9630
FIRE-166-TRIGG-512K

LA-9610
M-ST10/C167
Module for TQFP100 and PQFP144

supports ST10x163, ST10R165, ST10x167, ST10x168,
ST10xx69, C163, C165, C167xx,
ST10R172L, ST10R262, ST10272L
Connectors for ET100-QF06 and ET-144
LA-9617
Module for C163
M-C163

supports C163, 3.3 and 5 V
LA-9615
Module for ST10/XCORE
M-ST10/XCORE
Module for XCORE, adaption by TCON-240
LA-9582
Module for ST10F276
M-ST10F276
Module for TQFP144 and PQFP144,

supports ST10F271, ST10F272, ST10F273, ST10F275
and ST10F276
Connectors for ET-144
LA-9618
Module for ST10F280
M-ST10F280
Module for ST10F280, adaption by TCON-200
LA-9619
CPU adapter for ST10F280
CPU-ST10F280
Adapter board for ST10F280,

adaption by TCON-200
LA-9609
Emulation adapter for AI socket for ST10F280
BGA233-AI-ST10F280
Adapter for ST10F280 and ST10F296 to BGA233-Socket

Advanced Interconnect socket part number AI-9603 :
MGS-233-636GG
Testadapter for usage of CPU in BGA233 (LA-9608)
LA-9608
CPU Test Adapter for BGA233 ST10F280/F296
BGA233-CPU-ADAPTER
Adapter board for ST10F280 and ST10F296,

allows the use of the original CPU
adaption by TCON-200, BGA socket for ST10F280
and ST10F296
AI-9598
AI male to male adapter for BGA233
BGA233-AI-MALE-MALE
Advanced Interconnect male to male adapter

BGA233 for ST10F280
(17 x 17 rows)
AI-9603
Advanced Interconnect Socket for ST10F280
BGA233-AI-SOCKET
Advanced Interconnect socket

BGA233 for ST10F280 and ST10F296
(17 x 17 rows)
106
Products
Order Information
C166
Order No.
Code
Text
LA-9604
LA-9602
LA-9630
LA-9610
LA-9611
LA-9612
LA-6618
LA-9613
LA-9614
LA-9616
LA-9617
LA-9581
FIRE-166
FIRE-166-TRIGG-64K
FIRE-166-TRIGG-512K
M-ST10/C167
M-C161CS
M-C161PI
CPU_C161
M-C164CI
M-C164CR
M-C161V
M-C163
M-C164CM

Module for C161CI/SI/JI/CS
Module for C161RI/PI
CPU Adapter C161SI/CI/CS
Module for C164CI
Module for C164CR
Module for C161S/V/K/O
Module for C163
Module for C164CM
Additional Options
LA-7512
MON-166
ROM Monitor for C166/ST10 on ESI
ST10
Order No.
Code
Text
LA-9600
LA-9602
LA-9630
LA-9610
LA-9617
LA-9615
LA-9582
LA-9618
LA-9619
LA-9609
LA-9608
AI-9598
AI-9603
FIRE-ST10-201
FIRE-166-TRIGG-64K
FIRE-166-TRIGG-512K
M-ST10/C167
M-C163
M-ST10/XCORE
M-ST10F276
M-ST10F280
CPU-ST10F280
BGA233-AI-ST10F280
BGA233-CPU-ADAPTER
BGA233-AI-MALE-MALE
BGA233-AI-SOCKET
FIRE Emulator for ST10-201

Module for C163
Module for ST10/XCORE
Module for ST10F276
Module for ST10F280
CPU adapter for ST10F280
Emulation adapter for AI socket for ST10F280
CPU Test Adapter for BGA233 ST10F280/F296
AI male to male adapter for BGA233
Advanced Interconnect Socket for ST10F280
107
Products
Order No.
Code
Additional Options
LA-9585
M-ST10F252
LA-9584
M-ST10F296
LA-7512
MON-166
Text
Module for ST10F252
Module for ST10F296
ROM Monitor for C166/ST10 on ESI
108
Products

Fire c166

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FIRE Emulator for C166 Family

TRACE32 Online Help

FIRE In-Circuit Emulator ...............................................................................................................

FIRE Target Guides ....................................................................................................................

FIRE Emulator for C166 Family ..............................................................................................

FIRE Emulator for C166 Family ...........................................................................................

Quick Start .........................................................................................................................

Emulation Module ST10R201

CPU access modes

Sets dualport update interval

General SYStem Settings and Restrictions ....................................................................

FIRE Emulator for C166 Family

CPU type selection

3.3V power fail detection

Mask interrupts during assembler step

Mask interrupts during HLL step

On-circuit emulation reset

Write strobe limitation

Exception Control .............................................................................................................

XPER Mapping and Shadowing .......................................................................................

Bondout Trace ...................................................................................................................

Bondout Trigger and Break System ................................................................................

Bondout Trigger System

Trigger on Data Writes

Trigger on Data Writes with Data Qualification

Selective Trace of Address Areas

Selective Trace of Address Areas and Data Qualification

Trigger on Execution of Program Line

Trace of Local Variables

FIRE Emulator for C166 Family

Trigger of Local Variables with Data Qualification

Code Flag System .............................................................................................................

Data Access Flags .............................................................................................................

Bondout Based Dualport Systems ..................................................................................

Bondout Shadow Memory

On-chip Trigger System ....................................................................................................

Special Functions ..............................................................................................................

Memory Classes ................................................................................................................

State Analyzer ....................................................................................................................

General 80166 Keywords for the Trigger Unit

Bondout CPU Keywords for the Trigger Unit

Keywords for the Display

Bondout Information Display

Port Analyzer .....................................................................................................................

Port Signals C161PI/C161RI

Port Signals C161SI/C161CI/C161JC/C161CS

Port Signals C161V/C161K/C161O

Port Signals C163

Port Signals C164CI

Port Signals C164CM/C164SM/C164SV

Port Signals C164CR

Port Signals C165

Port Signals C167/F16X/F26X

Port Signals ST10F25X

Port Signals ST10F276/ST10F286

Port Signals ST10F280/ST10F29X

Port Signals XCORE

Technical Data ...................................................................................................................

FIRE Emulator for C166 Family

Realtime Operation Systems

3rd Party Tool Integrations

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FIRE Emulator for C166 Family