FORMATS FOR SUBMISSION OF PROJECTS ONLY FOR

CHARACTERIZATION UNDER THE INDIAN NANOELECTRONICS

USERS PROGRAM (INUP) AT IIT BOMBAY
(The proposals exceeding 2 pages are liable to be rejected without review.)
1. Project Title: Optimization and Analysis of 6T SRAM using CNFET at 32nm
Regim
2. Investigator(s)
Principal Investigator

Co-Principal Investigator

Title and Name

Satish M Turkane

Avinash S Pawar

Designation

Research Scholar

M.E. Student

Department

Electronic and
Telecommunication

Electronic and
Telecommunication

Organization

PREC Loni

PREC Loni

Academic/Industry Academic

Academic

Government/private Private

Private

Indian/Foreign Indian

Indian

Address

Loni, Rahata Taluk,

Ahmednagar, Maharashtra
413736

Loni, Rahata Taluk,

Ahmednagar, Maharashtra
413736

Telephone

8888787878

7030193213

Telefax

(02422) 273204

(02422) 273204

e-mail
satish_turkane@yahoo.co.in Pawar.avinash0007@gmail.com
3. Project abstract (maximum 500 words)
As
the
technology
is
moving
towardsnano-scale
regime,CNFET is having high stability, high performance and low power
dissipation. This makes CNFET a promising device for designing of
memory arrays.We have optimized a design of 6T SRAM cell based on

32nm CNFET technology and compare edit with MOSFET at same

regime. SRAM cell designed by CNFET shows improvement in the SNM
for read and write operation. We had examined the read and write
operation and obtained the results showing improved performance by
using different transistor ratio of small in size. As per the property of
CNFET having cell ratio of 2 and pull up ratio of 0.4, there had been
improvement in stability, performance and sensitivity on process
variation. High SNM is achieved with low nanotube diameter for the
SRAM cell. All the simulation is done on HSPICE simulation software
using 32nm CNFET Stanford model. Devices and circuits development
of low power circuits based on its unique tunneling properties and
chirality can further be explored.
4. Process flow/Sample history
Please provide the complete process flow indicating the steps with the relevant
specifications, that the sample has already gone through and process you want to do
at IIT Bombay. Mention the lab in which the completed process steps were carried
out. This information is required to verify the feasibility of the steps proposed to be
done at IIT Bombay from a contamination point of view and is central to the success
of your experiment. Please submit the form for Outside sample history &
process request_INUP.docx
5. For outside samples, contamination clearance is mandatory. Refer
to Anti Contamination Policy.V4.16.12.14-1.pdf

6. In case of a new chemical (chemical not listed on CEN website

http://www.cen.iitb.ac.in/cen/safety/newChemical.php) to be used
in proposed project please get the new chemical clearance. Kindly
send an email to inup@iitb.ac.in

7. Research infrastructure required

a. List those required from IIT Bombay Nanoelectronics Centre.
(Details of R&D infrastructure available at the Centre of Excellence in Nanoelectronics,
IIT Bombay may be found on www.inup.iitb.ac.in)
8. Funding for your project
Please indicate if any funding is available for your project and if part of the expenses
for usage of IITBNF facilities can be borne from such a project. Indicate the amount in

Indian Rupees. If the funding is not available, please submit the declaration by parent
organization.

9. Travel (in a table)

This refers to the travel expenses from your organization to IIT Bombay and back for
doing experiments. Indicate whether funding (part or complete) for such travel is
available to you. If only part funding is available, please indicate the amount.

10.

Any other relevant information