VLSI

DESIGN
A. Albert Raj
T. Latha

VLSI DESIGN
A. ALBERT RAJ

T. LATHA

Assistant Professor

Assistant Professor

Department of Electronics and Instrumentation Engineering

Noorul Islam College of Engineering
Kanyakumari

New Delhi-110001
2008

VLSI DESIGN
A. Albert Raj and T. Latha
2008 by PHI Learning Private Limited, New Delhi. All rights reserved. No part of this book may be
reproduced in any form, by mimeograph or any other means, without permission in writing from the
publisher.
ISBN-978-81-203-3431-1
The export rights of this book are vested solely with the publisher.
Published by Asoke K. Ghosh, PHI Learning Private Limited, M-97, Connaught Circus,
New Delhi-110001 and Printed by Mudrak, 30-A, Patparganj, Delhi-110091.

Contents
Preface

xiii

1. INTRODUCTION

1 4

1.1 Evolution of VLSI Device Technology 1

1.2 Metal Oxide Semiconductor (MOS) and VLSI Technology
Summary
4

2. BASIC MOS STRUCTURE

2.1
2.2
2.3

2.6

15

21

Interconnect
22
Circuit Elements
25

BiCMOS Technology
2.7.1
2.7.2

11

The p-well CMOS Process

15
The n-well CMOS Process
16
The Twin-Well Process
19
Silicon-On-Insulator Process
19

CMOS Process Enhancements

2.6.1
2.6.2

2.7

10

Complementary CMOS Switch

NMOS Fabrication 12
Basic CMOS Technology
2.5.1
2.5.2
2.5.3
2.5.4

Enhancement Mode Transistor Action

7
Depletion Mode Transistor Action
10

MOS Transistor Switches

2.3.1

2.4
2.5

533

Introduction 5
Basic MOS Transistor Operation
2.2.1
2.2.2

29

BiCMOS Fabrication in an n-well Process

32
Some Aspects of Bipolar and CMOS Devices
32

Summary
32
Review Questions 33
Short Answer Questions

33
iii

iv

Contents

3. MOS DEVICE CHARACTERISTICS

3.1
3.2

Introduction 34
Static Behaviour of the MOS Transistor
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5

3.3

3.7
3.8

43

Threshold Variations
46
SourceDrain Resistance
47
Variation in I-V Characteristics
Subthreshold Conduction
49
CMOS Latchup
50

46

48

NMOS Inverter 50
Determination of Pull-up to Pull-down Ratio (Zp.u/Zp.d) for an
NMOS Inverter Driven by Another NMOS Inverter 52
Pull-up to Pull-down Ratio for an NMOS Inverter Driven Through One
or More Pass Transistors 54
Device Models for Simulation 56
3.8.1
3.8.2
3.8.3
3.8.4

MOS Models
56
DC MOSFET Model
56
High Frequency MOSFET Model
SPICE Models
60

Summary
62
Review Questions 62
Short Answer Questions

57

62

4. CMOS INVERTER DESIGN

4.1
4.2
4.3

Symmetric CMOS Inverter

76
Noise Margins of CMOS Inverter
77
Temperature Dependence of VTC of CMOS Inverter
Supply Voltage Scaling in CMOS Inverters
78
Power and Area Considerations
79

Switching Characteristics of CMOS Inverter

4.4.1

4.5
4.6

6389

Introduction 63
CMOS InverterDC Characteristics 65
Design Parameters of CMOS Inverter 75
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5

4.4

42

MOS Structure Capacitances 43

Channel Capacitance
44
Junction Capacitance
45
Capacitive Device Model
46

The Actual MOS TransistorSecondary Effects

3.4.1
3.4.2
3.4.3
3.4.4
3.4.5

3.5
3.6

35

The Threshold Voltage

35
CurrentVoltage Relations
39
A Model for Manual Analysis
42
MOS Transistor Transconductance gm and Output Conductance gds
MOS Transistor Figure of Merit, w0
43

Dynamic Behaviour of MOS Transistor

3.3.1
3.3.2
3.3.3
3.3.4

3.4

3462

Estimation of CMOS Inverter Delay

CMOSGate Transistor Sizing

Stage Ratio 86

85

81

80

78

Contents

4.7

Power Dissipation
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5

86

88

5. MOS CIRCUIT DESIGN PROCESSES

Stick Layout Using NMOS Design

Stick Layout Using CMOS Design

Design Rules and Layout

5.5.1
5.5.2
5.5.3

5.6

90115

Introduction 90
Why Design Rules 90
MOS Layers 91
Stick Diagrams 91
5.4.1
5.4.2

5.5

94
95

96

Lambda (l) Based Design Rules

97
Double Metal MOS Process Rules
101
CMOS Lambda-based Design Rules
102

Elements of Physical Design

5.6.1
5.6.2

109

Basic Concepts
110
Design Hierarchies
111

Summary
114
Review Questions 114
Short Answer Questions

114

6. SPECIAL CIRCUIT LAYOUTS

6.1
6.2
6.3
6.4
6.5
6.6
6.7

Static Dissipation
87
Dynamic Dissipation
87
Short-circuit Dissipation
87
Total Power Dissipation
87
Power Economy
88

Summary
88
Review Questions 88
Short Answer Questions
5.1
5.2
5.3
5.4

Introduction 116
Tally Circuits 117
NANDNAND, NORNOR, and AOI Logic
Exclusive-OR Structures 122
Barrel Shifter 127
Transmission Gates 130
Latches and Flip-flops 131
6.7.1
6.7.2

116136
119

CMOS Static Latches

132
CMOS Dynamic Latches
132

6.8 Fan-in and Fan-out of CMOS Logic Design

Summary
136
Review Questions 136
Short Answer Questions 136

134

vi

Contents

7. SUPER BUFFERS, BiCMOS AND STEERING LOGIC

7.1
7.2
7.3

Introduction 137
RC Delay Lines 138
Super Buffers 139
7.3.1
7.3.2
7.3.3
7.3.4

7.4
7.5
7.6
7.7

137157

NMOS Super Super Buffer

141
NMOS Tristate Super Buffers and Pad-Drivers
CMOS Super Buffers
143
BiCMOS Gates
144

142

Dynamic Ratioless Inverters 146

Large Capacitive Loads
147
Pass-Transistor Logic 148
General Function Blocks 152
7.7.1
7.7.2

NMOS Function Blocks

CMOS Function Blocks

Summary
156
Review Questions 156
Short Answer Questions

153
155

156

8. CMOS COMBINATIONAL LOGIC CIRCUITS

8.1
8.2

Introduction 158
Static CMOS Design
8.2.1
8.2.2
8.2.3

8.3

159

Complementary CMOS
159
Ratioed Logic
163
Pass-Transistor Logic
164

Dynamic CMOS Design

8.3.1
8.3.2
8.3.3
8.3.4

158178

166

Dynamic Logic: Basic Principles

166
Speed and Power Dissipation of Dynamic Logic
Signal Integrity Issues in Dynamic Design
168
Cascading Dynamic Gates
171

8.4 Complex Logic Gates in CMOS

Summary
177
Review Questions 177
Short Answer Questions 178

167

172

9. CMOS SEQUENTIAL LOGIC CIRCUITS

9.1
9.2
9.3
9.4

9.4.1
9.4.2
9.4.3
9.4.4

9.5

179197

Introduction 179
Timing Metrics for Sequential Circuits 180
Classification of Memory Elements 181
Static Latches and Registers 183
Bistability Principle
183
Multiplexer-Based Latches
183
MasterSlave Edge-Triggered Register
Low Voltage Static Latches
187

Dynamic Latches and Registers

9.5.1
9.5.2
9.5.3

185

187

Dynamic Transmission-Gate Edge-Triggered Registers

189
C2MOSA Clock Skew Insensitive Approach
True Single-Phase Clocked Register (TSPCR)
190

188

Contents

9.6

Alternative Register Styles

9.6.1
9.6.2

9.7

192

193

The Schmitt Trigger

193
Monostable Sequential Circuits
Astable Circuits
195

Summary
196
Review Questions 196
Short Answer Questions

vii

192

Pulse Registers
192
Sense Amplifier-Based Registers

Non-bistable Sequential Circuits

9.7.1
9.7.2
9.7.3

194

197

10. DESIGN OF ARITHMETIC BUILDING BLOCKS

198225

10.1 Introduction 198

10.2 Datapaths 199
10.3 The Adder
200
10.3.1 The Binary Adder: Definitions
200
10.3.2 The Full-Adder: Circuit Design Considerations
202
10.3.3 The Binary Adder: Logic Design Considerations
207

10.4 The Multiplier

10.4.1
10.4.2
10.4.3
10.4.4

217

Multiplier: Definitions
218
Partial-Product Generation
219
Partial-Product Accumulation
220
Final Addition
223

Summary
224
Review Questions 224
Short Answer Questions

225

11. PROGRAMMABLE LOGIC DEVICES

226258

11.1 Introduction 226

11.2 NMOS PLAs
227
11.2.1 NMOS PLA Layouts

227

11.3 Other Programmable Logic Devices

232

11.3.1 Field Programmable Logic Array (FPLA)

11.3.2 Programmable Array Logic (PAL)
233
11.3.3 Dynamic Logic Arrays (DLAs)
233

232

11.4 The Finite-State Machine as a PLA Structure 235

11.5 Complex Programmable Logic Devices (CPLDs) 237
11.5.1 CPLD Packaging and Programming

239

11.6 Field Programmable Gate Arrays (FPGAs)

11.6.1
11.6.2
11.6.3
11.6.4

242

FPGA Packaging and Programming

243
The XILINX Programmable Gate Array
250
Implementation in FPGAs
256
Design Flow
256

Summary
257
Review Questions 258
Short Answer Questions

258

viii

Contents

12. CMOS CHIP DESIGN

259 284

12.1 Introduction 259

12.2 Design Strategies 260
12.2.1
12.2.2
12.2.3
12.2.4
12.2.5

Structured Design Strategies

Hierarchy
261
Regularity
261
Modularity
261
Locality
261

12.3 CMOS Chip Design Options

12.3.1
12.3.2
12.3.3
12.3.4

260

262

Application Specific Integrated Circuits (ASICs)

Types of ASICs
262
Economics of ASICs
272
CMOS Chip Design with Programmable Logic

Summary
283
Review Questions 283
Short Answer Questions

285307

13.1 Introduction 285

13.2 Global Routing 285
Goals and Objectives
285
Measurement of Interconnect Delay
286
Global Routing Methods
289
Global Routing Between Blocks
289
Global Routing Inside Flexible Blocks
291
Timing-Driven Methods
293
Back-Annotation
294

13.3 Detailed Routing

13.3.1
13.3.2
13.3.3
13.3.4
13.3.5
13.3.6
13.3.7
13.3.8
13.3.9
13.4.1
13.4.2

294

Goals and Objectives

298
Measurement of Channel Density
298
Algorithms
299
Left-Edge Algorithm
299
Constraints and Routing Graphs
299
Area-Routing Algorithms
302
Multilevel Routing
303
Timing-driven Detailed Routing
303
Final Routing Steps
304

13.4 Special Routing

304

Clock Routing
Power Routing

Summary
306
Review Questions 306
Short Answer Questions

277

284

13. ROUTING PROCEDURES

13.2.1
13.2.2
13.2.3
13.2.4
13.2.5
13.2.6
13.2.7

262

304
305

306

Contents

14. CMOS TESTING

ix

308351

14.1 Introduction 308

14.2 Need for Testing 308
14.2.1
14.2.2
14.2.3

Functionality Tests
309
Manufacturing Tests
309
Test Process
310

14.3 General Concepts of Testing

14.3.1
14.3.2

Reliability
311
Reliability Modelling

310
312

14.4 Manufacturing Test Principles

14.4.1
14.4.2
14.4.3
14.4.4
14.4.5
14.4.6
14.4.7
14.4.8
14.4.9
14.4.10

14.5 Design Strategies for Test

14.5.1
14.5.2
14.5.3
14.5.4
14.5.5

314

Fault Models
314
Gate Level Testing
317
Observability
321
Controllability
321
Fault Coverage
321
Automatic Test Pattern Generation (ATPG)
Fault Grading and Fault Simulation
326
Delay Fault Testing
327
Statistical Fault Analysis
328
Fault Sampling
329

330

Design for Testability

330
Ad hoc Testing
330
Scan-Based Test Techniques
Self-Test Techniques
339
IDDQ Testing
342

14.6 Chip-Level Test Techniques

14.6.1
14.6.2
14.6.3

Regular Logic Arrays

Memories
343
Random Logic
344
Boundary Scan

333

343

343

14.7 System-Level Test Techniques

14.7.1

344

344

14.8 Layout Design for Improved Testability

Summary
350
Review Questions 350
Short Answer Questions 350

15. VERILOG HDL

Verilog by Example

350

352365

15.1 Introduction 352

15.2 Basic Concepts 352
15.3 Structural Gate-Level Modelling
15.3.1

322

354

15.4 Switch-Level Modelling 359

15.5 Design Hierarchies 363
Summary
365
Review Questions 365
Short Answer Questions 365

354

Vlsi Design

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ALBERT, LATHA, T.

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