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Conditional Instructions
Instructions in a processor can be divided in to two categories
Unconditional instructions
Conditional instructions
Unconditional instructions
Arithmetic and logic instructions ADD, SUB, MPY, OR, AND etc.
Unconditional control instructions branch, call and return.
Syntax B loop , CALL sine, RET
Conditional instructions
These instructions are executed based on certain logical conditions
How the logical conditions are defined in processors?
Based on the content of accumulator
EQ (equal to 0)
NEQ (not equal to 0)
GT (greater than 0)
LT (less than 0)
GEQ (greater than or equal to 0) LEQ (less than or equal to 0)
Based on the flags
OV (over flow)
NOV (no over flow)
C (carry)
NC (no carry)
TC (test control true)
NTC (test control false)
Based on hardware pin
BIO (BIO signal low)
NBIO (BIO signal high)
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Interrupts
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What is an interrupt?
Interrupt is a signal (to be of any form) which is used to establish data transfer
between CPU and other devices.
What are the different types of interrupts?
Interrupts
External
Interrupts
Hardware
Interrupts
Internal
Interrupts
Software
Interrupts
NonMaskable
Nonmaskable
maskable
Maskable
Hardware
Interrupts
Nonmaskable
Maskable
Software
Interrupts
Nonmaskable
Maskable
1. All external
Interrupts are
hardware initiated
2. Internal interrupts
are initiated by both
hardware and
software
3. Only external
interrupts are Nonmaskable
4. All Internal
interrupts are
maskable
Interrupts cont
Interrupts in DSPs
External- Hardware initiated Non-maskable interrupts RS and NMI
RS Reset (hardware reset) - Program execution stops, all registers initialized to original value
NMI Non-maskable interrupt Program execution stops, register contents are not affected
External- Hardware initiated maskable interrupts INT0, INT1,INT2, INT3
INT0 External user interrupt 0
INT 1 External user interrupt 1
INT 2 External user interrupt 2
INT 3 External user interrupt 3
Internal- Hardware initiated maskable interrupts
All on-chip peripherals have interrupts
TINT Timer interrupt
XINT Serial port transmit interrupt
RINT Serial port receive interrupt
HINT Host port interface interrupt
Internal- software initiated maskable interrupts
INTR, TRAP
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Interrupts cont
The occurrence of the interrupt to the processor will set 1 the corresponding
bit in IFR until the CPU recognize the interrupt
The format of IFR is same as IMR
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Priority of interrupts
Interrupt location and priority table (`C541)
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Interrupt Programming
What is interrupt Programming?
Writing the interrupt service routing (ISR) for each and every interrupt and
storing them in the interrupt service routine address (ISRA) generated by the
processor.
How the interrupt service routine address is generated?
The interrupt-vector address is generated by concatenating the interrupt
vector pointer (IPTR) field of the PMST with the interrupt-vector number
(031) shifted by 2.
Example: Let IPTR = 01, the interrupt number for INT0 is 16 (10h)
The ISRA generated for INT0 is concatenating IPTR (01h) with (10h)
left shifted by two.
we get ISRA as 00C0h
The number of address locations allotted for each interrupt is four
By changing the IPTR, ISRA generated can be made access any block of
Program memory
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ISRA generated by the processor has only four PM locations for each interrupt.
ISR needs more than four memory locations.
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Interrupt Processing/Operation
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Once an interrupt has been passed to the CPU, the CPU operates in the
following manner
Maskable Interrupts:
1. The corresponding bit in the IFR is set 1, this gives the information to CPU
that interrupt has occurred.
2. Check for the conditions INTM = 0 and the corresponding bit in IMR =1, the
acknowledgment conditions are tested.
3. If the conditions are true, the CPU acknowledges the interrupt, generating
an IACK signal; otherwise, it ignores the interrupt and continues with the
main program.
4. When the interrupt has been acknowledged, its flag bit in the IFR is cleared
to 0 The INTM bit is set 1 (to block other maskable interrupts).
5. ISRA is generated by the CPU with IPTR value and interrupt number
6. The PC is saved on the stack by PUSH operation and ISRA is loaded in PC
7. The CPU branches to and executes the interrupt service routine (ISR).
8. The ISR is concluded by a return instruction, which pops the return address
off the stack.
10. The CPU continues with the main program till next time IFR is set.
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Non-maskable Interrupts:
1. The CPU immediately acknowledges the interrupt, generating an IACK
signal.
2. If the interrupt was requested by RS, NMI, or the INTR instruction, the the
INTM bit is set to 1 to block maskable hardware interrupts.
3. If the INTR instruction has requested one of the maskable interrupts, the
corresponding flag bit is cleared to 0.
4. The PC is saved on the stack.
7.
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Interrupt latency
Interrupt latency is defined as the number of clock cycle delay from the clock
cycle the interrupt occurred to the interrupts service routine get executed.
What is minimum latency?
For a 4 level pipelined system the minimum latency is 8 clock cycles
3 cycles to execute instructions in the pipeline before executing a
software vector.
1 cycle for the interrupt to be recognized by the CPU
4 cycles to execute the interrupt instruction and flush the pipeline
The minimum latency depends on the number of pipeline stages and the
number of clock cycle required for the CPU to recognize.
What is maximum latency?
The maximum interrupt latency depends on the type of instructions in the
pipeline.
Instructions such as repeat, branch, call which are in the pipeline are to be
completely executed before recognizing the interrupt.
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In power down mode the processor enters a dormant state and dissipates less
power than in the normal mode while maintaining the CPU contents
How to invoke power down mode?
The power-down mode can be invoked by executing the IDLE 1, IDLE 2 or
IDLE 3 instructions.
By driving the HOLD signal low with the HM status bit set to 1.
IDLE1
The IDLE1 mode halts all CPU activities except the system clock.
The system clock is applied to the peripherals, the peripheral circuits
continue to operate.
The peripherals such as serial ports , timers etc can take the CPU out of its
power-down state.
IDLE2
The IDLE2 mode halts the on-chip peripherals as well as the CPU.
Power is significantly reduced because the device is completely stopped.
Since, the on-chip peripherals are stopped, they cannot be used to wake
up from IDLE2.
To terminate IDLE2, activate any of the external interrupt pins (RS, NMI, and
INTx) with a 10-ns minimum pulse.
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Pipeline operation
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Operations performed
Hardware used
Fetch
Decode
Read
Execute
All processing
blocks & DB(W)
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No. of clock
cycle
Fetch
Decode
Read
Execute
LD #10h,DP
LD
LD #10h,DP
1000h
LD
LD #10h,DP
SUB 20h, B
Dummy
LD
LD #10h,DP
NOP
SUB 20h, B
Dummy
LD
ADD *AR2+,A
NOP
SUB 20h, B
Dummy
NOP
ADD *AR2+,A
NOP
SUB 20h, B
ST A, *AR2+
NOP
ADD *AR2+,A
NOP
LDM AR0,A
ST A, *AR2+
NOP
ADD *AR2+,A
LDM AR0,A
ST A, *AR2+
NOP
LDM AR0,A
ST A, *AR2+
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12
LDM AR0,A
Change in
phase
Operations performed
Program
prefetch
Program
fetch
Decode
Decode
Read
Access
Read
Execute
Fetch
Execute
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Pipeline conflicts
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Operation performed
3
Clk
cycle
Pre
fetch
PAB=a1
PAB=a2
PB=B
PAB=a3
PB=b1
IR = B
PAB=a4
PB=i3
IR = b1
Dummy
PAB=b1
PB=i4
Dummy
Dummy
Dummy
PB=j1
Dummy
Dummy
Dummy
IR = j1
Dummy
Dummy
b1
dummy
dummy
dummy
dummy
dummy
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7
8
9
10
Fetch
Decode
Access
Read
Execute
j1
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8
9
10
Clk
cycle
Pre
fetch
PAB=a1
PAB=a2
PB=B
PAB=a3
PB=b1
IR = B
PAB=a4
PB=i3
IR = b1
Dummy
PAB=b1
PB=i4
IR = i3
Dummy
Dummy
PB=j1
IR = i4
i3
Dummy
IR = j1
i4
i3
b1
dummy
i4
i3
dummy
i4
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7
8
9
10
Fetch
Decode
Access
Read
Execute
j1
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On-chip memory
Write followed by dual operand access due to DARAM
If a dual-access memory block is mapped in both program and data
spaces, an instruction fetch will conflict with a data operand read
access if they are performed on the same memory block.
Off-chip memory
One set of external address and data buses, a bus conflict occurs
between instruction fetch (F), operand read (R), and execute (E) write
phases if program, data or both memory are external.
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End of Part-4