Overview of various processors

Block diagram of Pentium IV microprocessor

Block diagram of 8051 microcontroller

Block diagram of TMS320C50 Digital Signal Processor

Block diagram of Multi-core Processor

TMS320DM6441 Processor architecture

Intel Core 2 Duo Processor architecture

Architecture of ADSP Processors

ADSP 216X DSP MICROCOMPUTER FEATURES

Key Features
16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory
25 MIPS, 40 ns Maximum Instruction Rate (5 V)
Enhanced Harvard Architecture
Three-Bus Performance: Instruction Bus and Dual Data Buses
Independent Computation Units:
ALU, Multiplier/Accumulator and Shifter
Single-Cycle Instruction Execution and Multifunction Instructions
On-Chip Program Memory ROM and Data Memory RAM
Integrated I/O Peripherals: Serial Ports, Timer
Separate On-Chip Buses for Program and Data Memory
Program Memory Stores Both Instructions and Data
(Three-Bus Performance)
Dual Data Address Generators with Modulo and Bit-Reverse Addressing
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
Double-Buffered Serial Ports with Companding Hardware,
Automatic Data Buffering and Multichannel Operation
Three Edge- or Level-Sensitive Interrupts
Low Power IDLE Instruction

ADSP 216X FUNCTIONAL BLOCK DIAGRAM

Basic System Configuration

Architecture of MOTOROLA Processors

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DSP56300 FAMILY BASED DSP

Key Features

24-bit fixed point core

One Million Instructions Per Second (MIPS) per MHz of operating speed
Highly parallel instruction set
Data Arithmetic Logic Unit (Data ALU)
Address Generation Unit (AGU)
Program Control Unit (PCU)
Fully pipelined 24 X 24-bit parallel Multiplier-Accumulator (MAC) unit
Bit Field Unit, comprising a 56-bit parallel barrel shifter (fast shift and
normalization; bit stream generation and parsing)
Conditional ALU instructions
24-bit or 16-bit arithmetic support under software control
Four 24-bit input general purpose registers: X1, X0, Y1, and Y0
Six Data ALU registers (A2, A1, A0, B2, B1, and B0) that are concatenated into
two general purpose 56-bit accumulators and accumulator shifters (A and B)
Two data bus shifter/limiter circuits
On-chip instruction cache controller
External memory interface (Port A)
Triple Timer
Phase Locked Loop (PLL)
Six-channel Direct Memory Access (DMA) controller

BLOCK DIAGRAM OF DSP56300 FAMILY BASED DSP

DSP56303 Block Diagram

DATA ALU BLOCK OF DSP56303

ADDRESS GENERATION UNIT (AGU)

Tool Flow
Starter Kit (Flow-1)

Assembly File

.asm
Executable Files

Assembler &
Linker

Executable Files

Debugger

Starter Kit
Target DSP

.dsk

.dsk

(Flow-2) for CCS

Assembly or C Files
.asm ,.C and .mat

Executable Files
.out

Assembler
.obj
Linker

Executable Files

Debugger

Starter Kit
Target DSP

.out

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