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First A. Author, Second B. Author, Jr., and Third C. Author, Member, IEEE

A highly reliable and efficient differential type

Buck-Boost DC-AC converters.
Abstract With Buck Boost inverter we can achieve output voltage with peak value greater or smaller than the dc input
voltage in a single stage. The conventional structure of Buck Boost inverter uses current bidirectional IGBT. IGBT has
features like long tail current, fixed voltage drops and thats why its switching losses are relatively higher. In this
paper, we have proposed switching cells structure in Buck Boost inverter instead of using current bidirectional IGBT.
In switching cell structure, mosfets and external diodes with very fast reverse recovery characteristics are used, while
the body diodes will have no chance of conducting current. As a result, switching and conduction losses will be
reduced and diode performance will be improved. This new structure will have an additional advantage of having no
shoot through problem so we can eliminate dead time or in other words reliability is increased. In order to further
increase the efficiency, a modified switching scheme is also proposed. In conventional switching strategy, all the
power switches operate in high frequency all the time and suffer from high voltage/current stresses which results in
high switching and conduction losses. While in the proposed switching scheme for modified inverter power mosfets of
each leg of differential buck boost inverter will operate in high frequency for only half cycle which will result in
improved efficiency.
(Note that the organization of the body of the paper is at the authors discretion; the only required sections are Introduction,
Methods and Procedures, Results, Conclusion, and References. Acknowledgements and Appendices are encouraged but optional.)

Index Terms Bidirectional IGBT, Buck Boost inverter, switching cell, switching/conduction losses. For a list of suggested keywords,
send a blank e-mail to keywords@ieee.org or visit http://www.ieee.org/organizations/pubs/ani_prod/keywrd98.txt\

Note: There should no nonstandard abbreviations, acknowledgments of support, references or footnotes in in the abstract.

I.

INTRODUCTION1

Or dc-ac power conversion there exists two

well-known converters: the voltage-source inverter
(VSI)
and
the
current
source
inverter(CSI).[1],[2],[3],[4]. We can achieve only buck
function from VSI, while only boost function from
current source inverter. However, in some applications
e.g. in the photovoltaic power conditioning system, the
1 This paragraph of the first footnote will contain the date on which you
submitted your paper for review. It will also contain support information,
including sponsor and financial support acknowledgment. For example,
This work was supported in part by the U.S. Department of Commerce
under Grant BS123456.
The next few paragraphs should contain the authors current affiliations,
including current address and e-mail. For example, F. A. Author is with the
National Institute of Standards and Technology, Boulder, CO 80305 USA
(e-mail: author@ boulder.nist.gov).
S. B. Author, Jr., was with Rice University, Houston, TX 77005 USA.
He is now with the Department of Physics, Colorado State University, Fort
Collins, CO 80523 USA (e-mail: author@lamar.colostate.edu).
T. C. Author is with the Electrical Engineering Department, University
of Colorado, Boulder, CO 80309 USA, on leave from the National Research
Institute for Metals, Tsukuba, Japan (e-mail: author@nrim.go.jp).

voltage of photo voltaic cells varies in wide range, so

such an inverter system is needed which can perform
both buck and boost function.
The conventional voltage source inverter (VSI) which
is shown in Fig.1, is seemingly the most valuable
power converter topology. It is used in variety of
industrial and commercial applications in which
uninterruptible power supply (UPS) and ac motor
drives are most significant. Full bridge inverter is
commonly used as Buck inverter. However, using buck
inverter, we can achieve output voltage whose
instantaneous average output value is always less than
the input dc voltage.

S2

advantage, which is that output voltages of the two

individual buckboost converters are not required to be
greater than the direct input voltage. Which also results
in lower voltage stress across filter capacitors. The
structure of this buck boost inverter is composed of
two current bidirectional dc-dc buck boost converters
and the load is connected differentially across the two
converters as shown in Fig.4.

S4

V0

Vin

R
S1

S3

v0

Fig. 1. The conventional voltage source inverter or buck inverter

In order to cope with this complication there are two

possible solutions. The first one is to make an addition
of a line-frequency step-up transformer in the
full-bridge inverter [5], as shown in Fig. 2. But this
structure results in increased volume, cost and weight
and the power density is also reduced greatly with
noise pollution.
Another possible solution is to use a two-stage cascade
structure, as depicted in Fig. 3. In which dc-dc boost
converter is used between dc source and inverter [6].
But in this structure the combined efficiency losses
contribute unnecessarily to low efficiency levels. The
cascaded two stage structure has also greater system
size, weight and cost.
Transformer

Renewable
energy
source.

AC load
or grid

DC/AC

S2

C1 v1

S1

L1

Vin

S3

+
-

S4

L2

v2 C2

Fig.4. The Buck Boost inverter.

Each converter generates a sinusoidal output voltage

with same dc offset. The modulation of each converter
is 180 degrees out of phase with respect to each other.
Since the load is connected differentially, dc offsets are
cancelled out and pure sinusoidal output voltage is
achieved.Fig.5. shows the output voltage of each
converter and the voltage across the load.
Converter 1
0

VDC

-v
Converter 2
0

Fig.2. Inverter with a transformer.

VDC

-v
Voltage across the load
v
0

Boost DC-DC

-v

converter

Fig.5. Basic waveforms to attain dc-ac boost conversion.

Q1
L1
Vin

Q3

L2 vo

C1
Q2

Q5

Q4

C2

Q6

Fig.3. Inverter with cascade structure.

Alternative design was proposed in [5], [7], [8], [9].

known as Buck Boost DC-AC inverter, which could
generate an output voltage higher or lower than input
dc voltage. Other advantages were reduced number of
switches as compared to cascade two-stage inverter.
The buck-boost inverter when compared with boost
inverter [should be written] has a supplementary

In this paper, we proposed switching cell structure in

conventional buck boost inverter i.e. switching cells
structure is introduced in buck boost inverter and the
resulting buck boost inverter is given the name of Dual
Buck type buck-boost inverter. In comparison with the
conventional Buck Boost inverter the suggested
inverter has some noticeable improvements. First of
all, it wipes out shoot-through worries, which is a
prime failure of conventional Buck Boost inverter.
And the second one is that we have no need of dead
time between the complimentary switches. The third
one is that power MOSFETs are used instead of using
IGBTs which results in improved efficiency.

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However, for conventional PWM strategy the two buck

boost converters of modified structure need to operate
concurrently. Due to which switching losses are quite
higher. In order to mitigate the above shortcoming, in
this paper we have proposed a new PWM strategy, in
which for half cycle only the power switches of the 1st
buck/boost converter operate at higher frequencies and
for the next half cycle only the power switches of 2nd
buck/boost converter operate at higher frequencies. It
means that for each half cycle only two of the four
switches operate at higher frequencies. As a result,
switching losses will be significantly reduced and
hence efficiency will be improved. Detail analysis that
are equally approved with experimental results are
shown in subsequent sections.
II. COMMUTATION PROBLEM IN CONVENTIONAL
BUCK-BOOST INVERTER AND SWITCHING
CELL STRUCTURE

In conventional buck boost inverter when there is

overlap time between complementary switches, current
shoot through problem occurs. Overlap time occurs
either due to EMI noise or miss-triggering of the gate
signals. The current shoot through problem with
switching states is depicted in fig ().

S1

S2

v0
R
C0

S2

C1 v1

S1

L1

Vin

S3

+
-

S4

L2

v2 C2

This problem is resolved by switching cell structure as

depicted in Fig () []. Two types of switching cells are
presented in this paper commonly known as P-cell and
N-cell. Each cell consists of a power switch and a
diode in series while an inductor or current source is
connected to the common junction of power switch and
diode. Power switches used are commonly IGBTs or
mosfets, but mosfets are preferred for its better
performance. In P-cell the power switch is connected
to the positive terminal of voltage while current is
leaving away from the common junction point of diode
and power switch. While in the N-cell the power
switch is connected to the negative terminal and
current enters to the common junction point of diode
and power switch.

Overlap time
S4
S3

N-cell

P-cell

or

III. PROPOSED BUCK BOOST INVERTER

The circuit topology of the proposed Buck Boost
inverter is depicted in Fig. 6. Like traditional Buck
Boost inverter, the proposed structure also consists of
two parallel combinations of Buck Boost converters
and we get pure sinusoidal voltage by connecting the
load differentially across the two converters. But

unlike traditional buck boost inverter, switching cell

structure is proposed in each individual buck boost
converter as shown in Fig. 6. Each individual buck
boost converter is composed of P-cell and N-cell.
v0
R

S2
D1
C1 v1

L2

D2

D4

S1

S3

L1

Vin

+
-

S4

D3
v2

C2

Fig. 6. Proposed Buck Boost inverter.

In the proposed topology because of switching cell

structures power MOSFETs are used as active devices
while the conventional hard switching inverter is
designed using IGBTs. The reason behind this is that in
the conventional structure body diodes conduct current
and MOSFETs body diode has poor reverse recovery
features hence we cant use mosfet in conventional
structure. Here in the proposed topology the
arrangement is such that no current will pass through
the body diodes of active switches. Preference is given
to MOSFET over IGBT because its switching speed is
faster and switching losses are lower than IGBT. IGBT
has almost fixed voltage drop while the mosfet
experiences resistive conduction voltage drop. So in
the conditions where resistive conduction drop of
MOSFET is smaller than IGBT fixed voltage drop, we
can make full use of benefits of power MOSFETS as
active switch. Another catastrophic failure of
conventional structure is possible existence of current
shoot through problem, due to which finite dead time
was necessary for complimentary switches. While the
proposed structure has no shoot through problem
which makes the system more reliable. [10] Since the
proposed topology has no shoot through problem so
dead time between the complimentary switches can be
eliminated. Hence the problems related to dead time,
such as distortion of output waveforms and less energy
transfer, are eliminated. Body diodes of power mosfets
experience reverse recovery problem but that will not
create any trouble for us in this case because no current
flows through body diodes and hence we can cash the
benefits of external diodes (fast and low reverse
recovery problem) with both hands.

IV. MODULATION STRATEGY FOR THE PROPOSED

BUCK BOOST INVERTER

The schematics of proposed inverter is shown in Fig.6.

In this paper v1 and v2 , which are 180 out of phase
having same dc offsets and magnitude, represents
voltages across C1 and C2 . Vdc is offset or average
voltage while A represents magnitude of both
v1 and v2 . The duty ratio of switches S1 and S3 is
d1 & d2 . Vin Input DC voltage and V0 magnitude
of sinusoidal output voltage. In case of conventional
voltage source inverter, the voltage gain versus duty
ratio curve is straight line, so SPWM modulation
strategy is applicable. However, in the Boost and Buck
Boost converter the voltage gain curve is not a straight
line as depicted in Fig.7, from which we can easily
deduce that the proposed inverter output and input
voltage is not in linear relationship with duty cycle of
switch S1 . So, if we change the duty cycle in a
sinusoidal manner we cant realize a sinusoidal output
voltage. In the figure the voltage gains characteristics
of both the individual boost converters and the inverter
outputs are shown. Also, the inverter input to output
voltage gain for two different mean operating duty
cycle values (or offset values) are shown. Figure shows
that around the mean operating point the duty cycle and
the output voltage gain has linear relationship. In this
approximate linear region SPWM strategy can be used
however if high gain is required then modified SPWM
strategy should be used because of non-linearity.

Fig. 7. Voltage gain vs duty cycle curve for individual boost converters and
proposed inverter.

The basic waveforms for the proposed inverter under

revised modulation strategy is shown in Fig. 8.

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S 4 respectively. Because it requires less calculation of DSP

and that is why it is preferred.

vref 1 1 d1

carrier
0.5

V. AC GAIN OF THE PROPOSED BUCK BOOST INVERTER

0
S2
S1

Peak value of output voltage can be calculated from (2) and

(3) as:

vref 1

carrier

vref 2 1 d 2

carrier

V0 2V2 2VDC
Where V2 is maximum negative voltage that appears
across the capacitor of 2nd buck boost converter and is
calculated as
V D
V2 in .
1 D
D=maximum duty cycle of switch S3 or S1.
For minimum voltage stress across semiconductor
V
devices VDC 0 is chosen.
2
Vin D
V
Henc V0 2
2 0

1 D
2

0.5

0
S4
S3

VDC V sin t

v1
0

VDC

VDC V sin t
v2

(V ) : t ( s )

VDC V sin t

VDC
(V ) : t ( s )

VDC V sin t
V0 sin t

v0
0

(V ) : t ( s )

v0 v1 v2 2 A sin t
v2 VDC A sin t

(1)

d2 (Vin )
1 d2

(2)

v0 v1 v2 2 A sin t

OR v0 V0 sin t

In above equations VDC

where V0 2 A.

(3)

V
0 .
2

V
But the best case is VDC 0 because in this case the
2

voltage stress across the semiconductor devices will be

minimum. Hence for further calculations this value will be
considered.
From equations (1) -(3):
v0
v
0 sin t
2Vin 2Vin
d1
.
v0
v
0 sin t 1
2Vin 2Vin
1 d1

1
.
v0
v0

sin t 1
2Vin 2Vin

v0
v
0 sin t
2Vin 2Vin
d2
.
v0
v
0 sin t 1
2Vin 2Vin
1 d2

1
.
v0
v0

sin t 1
2Vin 2Vin

(4)

(5)

V0
D

Vin 1 D
Calculated ac gain is equally verified with simulation
results that are included in fig. (). The circuit
parameters along with its results are also summarized
in table[].
Ac gain=

INPUT VOLTAGE Vin

90V

Maximum duty of switch

S1 Dmax1

0.6

Maximum duty of switch S3

0.6

Switching frequency

20KHz
500uH

Capacitors C1 , C2

10uF

Dmax 3

Inductors L1 , L2 , L3 , L4

Load

AC gain
Maximum output voltage
(6)

(7)

The voltage reference which is derived in (4) and (6) can be

used to generate the gate signals for switch S1 and S3
respectively. While gate signals of S 2 is complement of S1
and gate signals of S 4 is complement of S3 . But in Fig.8.
we have used (5) and (7) to generate gate signals for S 2 and

V0 Ac gain Vin

50
1.5
135V

Similarly,

V
di2
in
dt
L1

(3)

di3 Vin

dt
L3

(4)

V
di4
in
dt
L4

(5)

In steady state during this mode

iin1 i1 i2 & iin2 i3 i4
i01 & i02 0

Since i01 & i02 0 in this mode hence output current

VI. MODAL ANALYSIS OF PROPOSED BUCK BOOST
INVERTER
The modal analysis is organized in such a way that 1st
we will consider the positive portion of sinusoidal
output voltage and then the negative portion. For the
positive portion d1 d3 which implies that v1 v2
and hence v0 v1 v2 will be positive, because both
v1 & v2 are negative voltages. The output voltage will
be zero whenever d1 d3 .

i0 will flow through both capacitors C1 and C2 . As

can be seen in figure (), that i0 flows into the positive
terminal of C1 hence C1 is charged and as current
flows away from positive terminal of C2 so it is
discharged during this portion.
v0

i0

S2

D1

i01

S1

D2

v1 C
1

L2
i2

L1
i1

S4

D3
iin1 iin2

Vin

+
-

i02

S3

D4
L3
i3

L4
i4

C2 v2

2) Mode 2: -

During this mode S1 is turned off while S2 is turned on.

While S3 remains in on state and S4 in off state as
shown in fig (). The body diodes of S1 and S4 are
reverse polarized by v1 Vin and v2 Vin

For positive portion of output voltage.

1) Mode 1: -

In this mode S1 and S3 are turned on while S2 and S4 are

off. The body diodes of S1 and S3 are reverse polarized
because S1 and S3 are on and ideally zero potential
difference appears across its body diodes. While the
body diodes of S2 and S4 are reverse polarized by
v1 Vin and v2 Vin respectively. Considering
that switches and diodes are ideal, voltage that appears
across L1 and L3 is Vin .
(1)
vL1 Vin
di1 Vin

dt
L1

(2)

respectively. While since S 2 and S3 are conducting

hence their body diodes will also be reverse polarized
because of zero potential difference across diodes
ideally. The inductors current ripple during this mode
will be as given below while assuming voltage small
ripple approximation;
di1
v
v di
1 , 2 1
dt
L1 dt L2
di3 Vin di4
V
in
,

L4
dt
L3 dt

In steady state during this mode

iin1 0 & iin2 i3 i4
i01 =i1 - i2 & i02 0

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v0

i0

v0

i0

S2

D1

i01

S1

D2

v1 C
1

L2
i2

i02

S3

+
-

Vin

L1
i1

S2

S4

D3
iin1 iin2

i01

D4
L3
i3

S1

D2

C2 v2

L4
i4

D1

v1 C
1

L2
i2

iin1 iin2

Vin

L1
i1

S4

D3

i02

S3

+
-

D4
L3
i3

C2 v2

L4
i4

6) Mode 6: 3) Mode 3: -

During this mode S1 and S3 are off while S 2 and S 4

are on as shown in fig (). Here again the body diodes of
mosfets will be reverse polarized. Diodes D2 and
D4 are forward biased to provide free wheeling path to
i1 and i3 respectively. While diodes D1 and D3 are
reverse biased. Assuming output voltage small ripple
approximation inductor current ripple will be
calculated as,
di1
di2 v1
v
1 ,

dt
dt L2
L1
di3
v
di
v
2 , 4 2
dt
L3 dt L4
Also, iin 0 & iin 0
1
2

S2

D2

v1 C
1

L2
i2

L1
i1

Vin

+
-

v1 C
1

S4

D3
iin1 iin2

S1

D2

D1

D1

i01

v0

S1

v0
R

i0

i01

di3
v
di
v
2 , 4 2
dt
L3 dt L4
i0

i01 i1 i2 & i02 i3 i4

S2

During this mode S3 and S 2 are in off state while

S1 and S4 are in the on state. This mode only appears
in negative portion of sinusoidal voltage. All the body
diodes will be reverse polarized. External fast recovery
diodes D1 and D3 will be forward biased by
freewheeling current. While assuming voltage small
ripple approximation the inductor current ripple will be
calculated as below.
V
di1 Vin di2
,
in

dt
L1 dt
L2

L2
i2

i02

S3

iin1 iin2

Vin

L1
i1

S4

D3

i02

S3

+
-

D4
L3
i3

C2 v2

L4
i4

D4
L3
i3

L4
i4

C2 v2

4) Mode 4: Here the operating mode is exactly similar to mode 2.

7) Mode 7: -

The operation is shown in Fig. (). Inductor current

ripple calculation will be same like mode 3. As can be
seen in the figure input current will be zero during this
portion. But in this mode direction of i0 will be
opposite that of mode 3.

For negative portion of output voltage

In this portion d3 d1 and as a result v2 v1
Which implies that v0 v1 v2 will be a negative

S2

The operation during this mode is shown in Fig. (). Its

analysis is similar like mode 1. The difference is that
output current is flowing in other direction for pure
resistive load. Capacitor C1 is discharging while C2
is charging.

D1

i01

value because both v1 and v2 are always negative.

5) Mode 5: -

v0

i0

S1

D2

v1 C
1

L2
i2

L1
i1

S4

D3
iin1 iin2

Vin

+
-

i02

S3

D4
L3
i3

L4
i4

C2 v2

8) Mode 8: -

This operating mode is exactly similar to mode 6.

ref1 1 d1

VII. FILTER CAPACITORS REARRANGEMENT FOR INPUT

carrier

CURRENT CONTINUITY

From modal analysis, it is obvious that during mode 3

and mode 7 input current of dc voltage source is zero.
Similarly, iin1 is zero during modes 2,3,4 & 7 while

S2

S1

iin2 is zero during modes 3,6,7 & 8. This implies that

input current, iin1 and iin2 are discontinuous. In the fig

ref 2 1 d 2

() we have rearranged the filter capacitors which

results in quasi continuous current. Due to this
arrangement, the voltage stress across filter capacitors
will increase.

S3

C1
v1

C2

D1

i01

S1

D2

L2
i2

S4

v0

i0

S2

carrier

L1
i1

iin1 iin2

Vin

S4
i02

S3

+
-

v1

v2

D3

v2

D4
L3

L4
i4

i3

The input current equations will be calculated as:

iin1 i1 i2 i0
iin2 i3 i4 i0
From equations, above i1 , i2 , i3 , i4 & i0 are either quasi
continuous or continuous hence iin and iin will also be
1

v0

quasi continuous.

VIII. MODULATION STRATEGY FOR REDUCED

SWITCHING LOSSES

In the modulation strategy discussed earlier all the four

power switches operate at high frequencies due to
which all the switches suffer from high voltage/current
stresses. As a result, high conduction and switching
losses take place. In this modulation strategy, the two
buck boost converters will operate one by one. In the
positive portion of output voltage one converter will
operate while in the negative portion of output voltage
another converter will operate. It means at a time only
two power switches will operate at higher frequencies
and the remaining two switches of the other converter
will operate at lower frequencies. As a result, both
switching and conduction losses are largely reduced.

In the positive portion of output voltage, S1 and S2 are

complementary signals and will operate at higher
frequencies. S3 will be in off state and S4 in on state
during this half cycle. Voltage across capacitor
C1 and C2 will be.
v1 0
(6)
0 t

v2 A sin(t )
In the negative portion of output voltage, S3 and S4
will operate at high frequencies. S1 will be in off state
and S2 in on state during this half cycle. Voltage
across capacitors C1 and C2 will be.
v1 A sin(t )
(7)
t 2

v2 0
From (6) and (7);
d1 0

A sin(t )

d 2 A sin(t ) V
in

A
sin

d1
A sin t Vin

d 0
2
From (8) and (9)

0 t (8)

t 2

(9)

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0 t

d1 0

A sin t

d1 A sin wt V
in

A sin(t )

d 2
A
sin(
wt ) Vin

d =0
2

(10)

0 t

(11)

t 2

S1

v1 C
1

S1

S3

S4

L2
i2

D1
S1

D2

v1 C
1

1) Mode 1: -

L2
i2

S1

D2

v1 C
1

L2
i2

L1
i1

Vin

2) Mode 2: The operation during this

period is a result of
complementary signals

+
-

iin1 iin2

Vin

L1
i1

i3

L3

C2 v2

L4
i4

v0

S2

D4
L4
i4

+
-

D4

S4

L3

S3

i3

i0

S3

S4

D3

off. The schematics is shown in fig. (). The input

voltage appears across L1 . Capacitor C1 will supply
load current io , which passes through S4 and D4 .

R
iin1 iin2

C2 v2

L4
i4

4) Mode 4: This operating mode is same as mode 2.

In the period the output voltage is negative
5) Mode 5: In this mode S1 and S4 are on while other switches are

v0
D3

L3

In this mode S3 and S2 are on while S1 and S4 are

off. The input voltage appears across L3 . Capacitor
C2 will supply load current io , which passes through
S2 and D2 .

D1

+
-

D4

v0

S2

Modified switching strategy for reduced switching losses.

S2

S3

i3

i0

t6 t7 t8 t9 t10 t11

i0

iin1 iin2

Vin

L1
i1

S4

D3

3) Mode 3: In this mode S2 and S4 are in on state. The operation is

Fig.

D1

shown in fig. (). Current i3 freewheels through D4

while i0 flows through D2 and S2 .

S2

S2

D2

IX. MODAL ANALYSIS FOR POSITIVE PORTION OF

OUTPUT VOLTAGE

t0 t1 t2 t3 t4 t5

v0

i0

t 2

D1
S1

D2

C2 v2

mode is shown in Fig. (). This

dead time between the two
S3 and S4 . In this mode

S1 ,S3 and S4 are in off state. Diodes D3 and D4 are

forward biased by freewheeling current i4 and i3
respectively. Since S1 is in off state and D1 is reverse
polarized i0 will pass through S2 and D2 .

v1 C
1

L2
i2

L1
i1

S4

D3
iin1 iin2

Vin

+
-

S3

D4
L3
i3

L4
i4

C2 v2

6) Mode 6: In this mode S1 , S2 and S3 are in off state while S4 is

on. The operation is shown in fig. (). In this mode

S1 and S2 are in off state simultaneously because of
dead time between complementary signals. D1 and D2
are forward biased by freewheeling current i2 and i1
respectively. Since S3 is in off state and D3 is reverse

[26] P.W. Sun, J.-S. Lai, H. Qian, W.S. Yu, C. Smith, J. Bates, B. Arnet, A.
Litvinov, and S. Leslie, Efficiency evaluation of a 55kW
soft-switching module based inverter for high temperature hybrid
electric vehicle drives application, in Proc. 25th IEEE Applied Power
Electron. Conf. and Expo., 2010, pp. 474--479.

polarized i0 will pass through S4 and D4 .

v0

i0

S2

D1
S1

D2

v1 C
1

L2
i2

iin1 iin2

Vin

L1
i1

S4

D3
S3

+
-

D4
L3
i3

C2 v2

L4
i4

7) Mode 7: In this mode S2 and S4 are in on state while the other

switches are in off state. The operation is shown in fig.

(). Current i1 freewheels through D2 while i0 passes
through D4 and S4 .
v0

i0

S2

D1
S1

D2

v1 C
1

L2
i2

L1
i1

S4

D3

iin1 iin2

Vin

+
-

S3

D4
L3
i3

L4
i4

C2 v2

8) Mode 8: This period is dead time and same as mode 6.

In
addition,
when
it
operates
at higher dc bus voltage of each cell, it loses the benefit of
employing
power
MOSFETs as the active switches for fast switching speed and
efficiency improvement because of the reverse recovery
issues
of the body diode [21]-[23] unless people employ
soft-switching techniques [24]-[26]. For example, when the
cell
dc bus voltage goes up to 300V to 600V, people can not
simply
adopt high voltage power MOSFETs (600V to 900V rated
voltage, such as CoolMOS or MDmesh series) to work at
hard-switched situation like traditional cascade H-bridge
inverter.
[21] S.-Y. Park, P.W. Sun, W. Yu and J.-S. Lai, Performance evaluation of
high voltage super junction MOSFETs for zero-voltage soft-switching
inverter applications, in Proc. 25th IEEE Applied Power Electron.
Conf. and Expo., 2010, pp. 387--391.
[23] C.M. Johnson, and V. Pickert, Three-phase soft-switching voltage
source converters for motor drives. II. Fundamental limitations and
critical assessment, IEE Proceedings on Electric Power Applications,
vol. 146, no. 2, pp. 155162, 1999
[24] P.W. Sun, J.-S. Lai, H. Qian, W.S. Yu, C. Smith, and J. Bates, High
efficiency three-phase soft-switching inverter for electric vehicle
drives, in Proc. IEEE Vehicle Power and Propulsion Conf., 2009, pp.
761--766.

However,
the
delayed
responses
of
gate
drive circuits and switching devices produce overlap time
and/or dead time among the switches. The overlap [see Fig.
2(a)] and dead time [see Fig. 2(b)] cause current spikes
(di/dt) and voltage spikes (dv/dt), respectively, often
damaging the semiconductor devices. Thus, overlap and
dead time among the switches severely impair the reliability
of traditional acac converters, which limits their practical
applications. Soft commutation strategies for smooth current
transition have been researched in [22] and [39] for the
purpose of providing safe commutation and to avoid the use
of lossy snubber circuits. All of these strategies use
voltage/current sensing modules to enable the switching
devices to conduct according to the polarity of the input
voltage/current. The sensing modules, however, increase the
cost and control complexity of the converter, and these
methods still cannot provide safe and reliable commutation
when the input voltage is highly distorted, especially around
the zero crossing point [13]. Similar to the method
using RC snubber circuits, these methods also cannot protect
the switching devices from high current spikes when
shoot-through caused by EMI noises misgating-on
occurs.Body (or antiparallel) diodes of standard
metaloxide semiconductor field-effect transistors
(MOSFETs) exhibit poor reverse recovery characteristics
[23], [24]; therefore, insulated gate bipolar junction
transistors
(IGBTs)
are
commonly
used
as
switching devices in the traditional hard switching acac
converters. Fig. 3 illustrates the effect of reverse recovery
problem
of the MOSFETs body diode in the traditional buck-type
acac
converter. Switches S3 and S4 are turned on for vin > 0 for the
safe commutation. To avoid current shoot-through, finite
dead
time between S1 and S2 is required and the output inductor
current freewheels through the body diode DB of S2 during the
dead time. When S1 is turned on after the dead time, DB flows
current in reverse direction for a short interval due to its
reverse
recovery as shown in Fig. 3(b). Due to this, the reverse
recovery current creates a short circuit of input voltage,
which
causes
large current spikes in the switches and diodes. [24].
[23] L. Saro, K. Dierberger, and R. Redl, High-voltage MOSFET behavior
in soft-switching converters: Analysis and reliability improvements, in
Proc. 20th IEEE Telecom. Energy Conf., 1998, pp. 3040.
[24] X. D. Huang, H. J. Yu, J.-S. Lai, A. R. Hefner, and D. W. Berning,
Characterization of paralleled super junction MOSFET devices under
hard and soft-switching conditions, in Proc. 32nd IEEE Power Electron.
Spec. Conf., 2001, vol. 4, pp. 21452150. [39] J. H. Kim, B. D. Min, B. H.
Kwon,
and
S.
C.
Won,
A
PWM
buckboost
ac

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) <
chopper solving the commutation problem, IEEE Trans. Ind. Electron.,
vol. 45, no. 5, pp. 832835, Oct. 1998. H. Shin, H. Cha, H. Kim, and D.
Yoo,
Novel
single-phase
PWM
AC
AC converters solving commutation problem using switching cell structure
and coupled inductor, IEEE Trans. Power Electron, vol. 30, no. 4,
pp. 21372147, Apr. 2015.

The traditional direct PWM acac converters are the simplest

converters, and they have been derived from the traditional
dc
dc converters by adaption of ac switches. The traditional
singlephase boost-type dcdc converter is shown in Fig. 1(a),
and
its counterpart traditional boost type acac converter is
shown
in Fig. 1(b). The switching devices of the converter shown in
Fig. 1(b) are connected in series, thereby causing
commutation
problem. The switches (S1, S4) and (S2, S3) are gated on/off
complementarily, and the converter can be operated properly
with ideal gate signals. However, the delayed responses of
gate
drive circuits and switching devices produce overlap time
and/or
dead time among the switches. The overlap [see Fig. 2(a)]
and
dead time [see Fig. 2(b)] cause current spikes (di/dt) and
voltage
spikes (dv/dt), respectively, often damaging the
semiconductor devices. Thus, overlap and dead time among
the
switches
severely impair the reliability of traditional acac converters,
which
limits
their
practical
applications.
A common approach to address the aforementioned problem
is to add bulky and lossy resistorcapacitor (RC) snubbers
and allow finite dead time in the gate signals. However, this
method decreases converter efficiency and achievable
voltage
gain [20], [21] and causes distortion of the output voltage
waveforms because energy is dissipated in the resistor of RC
snubber
circuits and is not transferred to output during the dead time.
Furthermore, the snubber approach cannot protect the
switching
devices from high current spikes when shoot-through caused
by
EMI
noises
misgating-on
occurs.
Soft commutation strategies for smooth current transition
have been researched in [22] and [39] for the purpose of
providing safe commutation and to avoid the use of lossy
snubber
circuits. All of these strategies use voltage/current sensing
modules to enable the switching devices to conduct
according
to
the polarity of the input voltage/current. The sensing
modules,

11

however, increase the cost and control complexity of the

converter, and these methods still cannot provide safe and
reliable
commutation when the input voltage is highly distorted,
especially around the zero crossing point [13]. Similar to the
method
using RC snubber circuits, these methods also cannot protect
the
switching devices from high current spikes when
shoot-through
caused
by
EMI
noises
misgating-on
occurs.
Body (or antiparallel) diodes of standard metaloxide
semiconductor field-effect transistors (MOSFETs) exhibit
poor
reverse recovery characteristics [23], [24]; therefore,
insulatedgate bipolar junction transistors (IGBTs) are
commonly
used
as
switching devices in the traditional hard switching acac
converters. Fig. 3 illustrates the effect of reverse recovery
problem
of the MOSFETs body diode in the traditional buck-type
acac
converter. Switches S3 and S4 are turned on for vin > 0 for the
safe commutation. To avoid current shoot-through, finite
dead
time between S1 and S2 is required and the output inductor
current freewheels through the body diode DB of S2 during the
dead time. When S1 is turned on after the dead time, DB flows
current in reverse direction for a short interval due to its
reverse
recovery as shown in Fig. 3(b). Due to this, the reverse
recovery current creates a short circuit of input voltage,
which
causes
large current spikes in the switches and diodes. [24]. The SC
structure shown in Fig. 4 can inherently overcome this
problem.
There are two types of SCs: P-type and N-type, as shown in
Fig. 4 [25], [26]. Both SCs consist of one switching device
such
as IGBT/MOSFET and one externally selected freewheeling
diode connected in series. In the P-type SC, the common
point
is connected to positive terminal of current source or
inductor,
and in the N-type SC, the common point is connected to
negative
terminal of current source or inductor [26]. Therefore,
designing
converters/inverters/rectifiers with the SC structure can
eliminate the current shoot-through problem. Many power
electronics
topologies, including multilevel dcac inverters [20], [21],
highefficiency dcac inverters [28][37], and acdc rectifier
[37]
are
implemented
with
the
SC
structure.

In [13], the SC structure is successfully employed in the tra

ditional single-phase acac converters for the first time. The
boost-type example is shown again in Fig. 1(c). As shown,
the
converter is implemented with the SC structure and coupled
inductors, and they have the following significant
advantages.
1) They do not require current/voltage sensing modules or
lossy snubber circuits for the safe commutation, and can
be operated properly even with highly inductive load and
distorted
input
voltage.
2) They can be operated with high switching frequency
without the reverse recovery problem associated with
MOSFET body diode and the switching devices are not
damaged even with dead time or overlap time during
operation.

B. Dead Time
The dead time in which all the switching devices are turned
off is shown in Fig. 11(a). The capacitors C1 and C2 bypass
the
inductors currents during the dead time. The bypass modes
for
positive and negative half cycle of input voltage are shown
in
Fig. 11(b) and (c), respectively

C. Overlap Time
In this interval, all the switching devices are turned on,
as shown in Fig. 12(a). The limiting inductors limit the
shoot-through current by providing a high impedance path
when
all the switches are turned on either by purpose or
mismatched
gate signals. Fig. 12(b) and (c) shows this mode for vin > 0
and
vin < 0, respectively.

D. Review Stage
Please check with your editor on whether to submit your
manuscript as hard copy or electronically for review. If hard
copy, submit photocopies such that only one column appears
per page. This will give your referees plenty of room to write
comments. Send the number of copies specified by your
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your editor prefers submissions on disk or as e-mail
attachments.
If you want to submit your file with one column
electronically, please do the following:
--First, click on the View menu and choose Print

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) <
Layout.
--Second, place your cursor in the first paragraph. Go to
the Format menu, choose Columns, choose one column
Layout, and choose apply to whole document from the
dropdown menu.
--Third, click and drag the right margin bar to just over 4
inches in width.
The graphics will stay in the second column, but you can
drag them to the first column. Make the graphic wider to push
out any text that may try to fill in next to the graphic.
E. Final Stage
When you submit your final version (after your paper has
been accepted), print it in two-column format, including
figures and tables. You must also send your final manuscript
on a disk, via e-mail, or through a Web manuscript
submission system as directed by the society contact. You
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Also, send a sheet of paper or PDF with complete contact
information for all authors. Include full mailing addresses,
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copy of the journal in which the paper appears. In addition,
designate one author as the corresponding author. This is
the author to whom proofs of the paper will be sent. Proofs
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Format and save your graphic images using a suitable
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the resolution settings. If you created your source files in one
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without converting to a PS, EPS, or TIFF file: Microsoft
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Import your source files in one of the following: Microsoft
Word, Microsoft PowerPoint, Microsoft Excel, or Portable
Document Format (PDF); you will be able to submit the
graphics without converting to a PS, EPS, or TIFF files.
Image quality is very important to how your graphics will
reproduce. Even though we can accept graphics in many
formats, we cannot improve your graphics if they are poor
quality when we receive them. If your graphic looks low in
quality on your printer or monitor, please keep in mind that
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If you are importing your graphics into this Word
template, please use the following steps:
Under the option EDIT select PASTE SPECIAL. A dialog
box will open, select paste picture, then click OK. Your
figure should now be in the Word Document.

13

If you are preparing images in TIFF, EPS, or PS format,

note the following. High-contrast line figures and tables
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Sizing of Graphics
Most charts graphs and tables are one column wide (3 1/2
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Size of Author Photographs
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How to create a PostScript File
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Print to a file using the PostScript printer driver. File names
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Web Color Graphics

TABLE I
UNITS FOR MAGNETIC PROPERTIES
Symbol

Fig. 1. Magnetization as a function of applied field. Note that Fig. is

abbreviated. There is a period after the figure number, followed by two spaces.
It is good practice to explain the significance of the figure in the caption.

IEEE accepts color graphics in the following formats:

EPS, PS, TIFF, Word, PowerPoint, Excel, and PDF. The
resolution of a RGB color TIFF file should be at least 400
dpi.
Your color graphic will be converted to grayscale if no
separate grayscale file is provided. If a graphic is to appear in
print as black and white, it should be saved and submitted as a
black and white file. If a graphic is to appear in print or on
IEEE Xplore in color, it should be submitted as RGB color.
Graphics Checker Tool
The IEEE Graphics Checker Tool enables users to check
graphic files. The tool will check journal article graphic files
against a set of rules for compliance with IEEE requirements.
These requirements are designed to ensure sufficient image
quality so they will look acceptable in print. After receiving a
graphic or a set of graphics, the tool will check the files
against a set of rules. A report will then be e-mailed listing
each graphic and whether it met or failed to meet the
requirements. If the file fails, a description of why and
instructions on how to correct the problem will be sent. The
IEEE Graphics Checker Tool is available at
http://graphicsqc.ieee.org/
For more Information, contact the IEEE Graphics H-E-L-P
Desk by e-mail at graphics@ieee.org. You will then receive
an e-mail response and sometimes a request for a sample
graphic for us to check.
H. Copyright Form
An IEEE copyright form should accompany your final
submission. You can get a .pdf, .html, or .doc version at
http://www.ieee.org/copyright. Authors are responsible for
obtaining any security clearances.

Conversion from Gaussian and

CGS EMU to SI a

Quantity

H
m

magnetic flux
magnetic flux density,
magnetic induction
magnetic field strength
magnetic moment

magnetization

4M

j
J

magnetization
specific magnetization
magnetic dipole
moment
magnetic polarization

susceptibility
mass susceptibility
permeability

r
w, W
N, D

relative permeability
energy density
demagnetizing factor

1 Mx 108 Wb = 108 Vs
1 G 104 T = 104 Wb/m2
1 Oe 103/(4) A/m
1 erg/G = 1 emu
103 Am2 = 103 J/T
1 erg/(Gcm3) = 1 emu/cm3
103 A/m
1 G 103/(4) A/m
1 erg/(Gg) = 1 emu/g 1 Am2/kg
1 erg/G = 1 emu
4 1010 Wbm
1 erg/(Gcm3) = 1 emu/cm3
4 104 T
1 4
1 cm3/g 4 103 m3/kg
1 4 107 H/m
= 4 107 Wb/(Am)
r
1 erg/cm3 101 J/m3
1 1/(4)

Vertical lines are optional in tables. Statements that serve as captions for
the entire table do not need footnote letters.
aGaussian units are the same as cgs emu for magnetostatics; Mx = maxwell,
G = gauss, Oe = oersted; Wb = weber, V = volt, s = second, T = tesla, m =
meter, A = ampere, J = joule, kg = kilogram, H = henry.

X. MATH
If you are using Word, use either the Microsoft Equation
Editor or the MathType add-on (http://www.mathtype.com)
for equations in your paper (Insert | Object | Create New |
Microsoft Equation or MathType Equation). Float over
text should not be selected.

XI. UNITS
Use either SI (MKS) or CGS as primary units. (SI units are
strongly encouraged.) English units may be used as
secondary units (in parentheses). This applies to papers in
data storage. For example, write 15 Gb/cm2 (100 Gb/in2).
An exception is when English units are used as identifiers in
trade, such as 3-in disk drive. Avoid combining SI and
CGS units, such as current in amperes and magnetic field in
oersteds. This often leads to confusion because equations do
not balance dimensionally. If you must use mixed units,
clearly state the units for each quantity in an equation.
The SI unit for magnetic field strength H is A/m. However,
if you wish to use units of T, either refer to magnetic flux
density B or magnetic field strength symbolized as 0H. Use
the center dot to separate compound units, e.g., Am2.

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) <
XII. HELPFUL HINTS
A. Figures and Tables
Because IEEE will do the final formatting of your paper,
you do not need to position figures and tables at the top and
bottom of each column. Large figures and tables may span
both columns. Place figure captions below the figures; place
table titles above the tables. If your figure has two parts,
include the labels (a) and (b) as part of the artwork.
Please verify that the figures and tables you mention in the
text actually exist. Please do not include captions as part of
the figures. Do not put captions in text boxes linked to
the figures. Do not put borders around the outside of
your figures. Use the abbreviation Fig. even at the
beginning of a sentence. Do not abbreviate Table. Tables
are numbered with Roman numerals.
Figure axis labels are often a source of confusion. Use
words rather than symbols. As an example, write the quantity
Magnetization, or Magnetization M, not just M. Put
units in parentheses. Do not label axes only with units. As in
Fig. 1, for example, write Magnetization (A/m) or
Magnetization (Am1), not just A/m. Do not label axes
with a ratio of quantities and units. For example, write
Temperature (K), not Temperature/K.
Multipliers can be especially confusing. Write
Magnetization (kA/m) or Magnetization (103 A/m). Do
not write Magnetization (A/m) 1000 because the reader
would not know whether the top axis label in Fig. 1 meant
16000 A/m or 0.016 A/m. Figure labels should be legible,
approximately 8 to 12 point type.
B. References
Number citations consecutively in square brackets [1]. The
sentence punctuation follows the brackets [2]. Multiple
references [2], [3] are each numbered with separate brackets
[1][3]. When citing a section in a book, please give the
relevant page numbers [2]. In sentences, refer simply to the
reference number, as in [3]. Do not use Ref. [3] or
reference [3] except at the beginning of a sentence:
Reference [3] shows ... . Please do not use automatic
endnotes in Word, rather, type the reference list at the end of
the paper using the References style.
Number footnotes separately in superscripts (Insert |
Footnote). 2 Place the actual footnote at the bottom of the
column in which it is cited; do not put footnotes in the
reference list (endnotes). Use letters for table footnotes (see
Table I).
Please note that the references at the end of this document
are in the preferred referencing style. Give all authors
names; do not use et al. unless there are six authors or
more. Use a space after authors initials. Papers that have not
been published should be cited as unpublished [4]. Papers

2 It is recommended that footnotes be avoided (except for the

unnumbered footnote with the receipt date on the first page). Instead, try to
integrate the footnote information into the text.

15

that have been accepted for publication, but not yet specified
for an issue should be cited as to be published [5]. Papers
that have been submitted for publication should be cited as
submitted for publication [6]. Please give affiliations and
addresses for private communications [7].
Capitalize only the first word in a paper title, except for
proper nouns and element symbols. For papers published in
translation journals, please give the English citation first,
followed by the original foreign-language citation [8].
C. Abbreviations and Acronyms
Define abbreviations and acronyms the first time they are
used in the text, even after they have already been defined in
the abstract. Abbreviations such as IEEE, SI, ac, and dc do
not have to be defined. Abbreviations that incorporate
periods should not have spaces: write C.N.R.S., not C. N.
R. S. Do not use abbreviations in the title unless they are
unavoidable (for example, IEEE in the title of this article).
D. Equations
Number equations consecutively with equation numbers in
parentheses flush with the right margin, as in (1). First use the
equation editor to create the equation. Then select the
Equation markup style. Press the tab key and write the
equation number in parentheses. To make your equations
more compact, you may use the solidus ( / ), the exp function,
or appropriate exponents. Use parentheses to avoid
ambiguities in denominators. Punctuate equations when they
are part of a sentence, as in
(1)
Be sure that the symbols in your equation have been
defined before the equation appears or immediately
following. Italicize symbols (T might refer to temperature,
but T is the unit tesla). Refer to (1), not Eq. (1) or
equation (1), except at the beginning of a sentence:
Equation (1) is ... .
E. Other Recommendations
Use one space after periods and colons. Hyphenate
complex modifiers: zero-field-cooled magnetization.
Avoid dangling participles, such as, Using (1), the potential
was calculated. [It is not clear who or what used (1).] Write
instead, The potential was calculated by using (1), or
Using (1), we calculated the potential.
Use a zero before decimal points: 0.25, not .25. Use
cm3, not cc. Indicate sample dimensions as 0.1 cm 0.2
cm, not 0.1 0.2 cm2. The abbreviation for seconds is
s, not sec. Do not mix complete spellings and
abbreviations of units: use Wb/m2 or webers per square
meter, not webers/m2. When expressing a range of values,
write 7 to 9 or 7-9, not 7~9.
A parenthetical statement at the end of a sentence is
punctuated outside of the closing parenthesis (like this). (A
parenthetical sentence is punctuated within the parentheses.)

In American English, periods and commas are within

quotation marks, like this period. Other punctuation is
outside! Avoid contractions; for example, write do not
instead of dont. The serial comma is preferred: A, B, and
C instead of A, B and C.
If you wish, you may write in the first person singular or
plural and use the active voice (I observed that ... or We
observed that ... instead of It was observed that ...).
Remember to check spelling. If your native language is not
English, please get a native English-speaking colleague to
carefully proofread your paper.
XIII. SOME COMMON MISTAKES
The word data is plural, not singular. The subscript for
the permeability of vacuum 0 is zero, not a lowercase letter
o. The term for residual magnetization is remanence; the
adjective is remanent; do not write remnance or
remnant. Use the word micrometer instead of micron.
A graph within a graph is an inset, not an insert. The
word alternatively is preferred to the word alternately
(unless you really mean something that alternates). Use the
word whereas instead of while (unless you are referring
to simultaneous events). Do not use the word essentially to
mean approximately or effectively. Do not use the word
issue as a euphemism for problem. When compositions
are not specified, separate chemical symbols by en-dashes;
for example, NiMn indicates the intermetallic compound
Ni0.5Mn0.5 whereas NiMn indicates an alloy of some
composition NixMn1-x.
Be aware of the different meanings of the homophones
affect (usually a verb) and effect (usually a noun),
complement and compliment, discreet and discrete,
principal (e.g., principal investigator) and principle
(e.g., principle of measurement). Do not confuse imply
and infer.
Prefixes such as non, sub, micro, multi, and
ultra are not independent words; they should be joined to
the words they modify, usually without a hyphen. There is no
period after the et in the Latin abbreviation et al. (it is
also italicized). The abbreviation i.e., means that is, and
the abbreviation e.g., means for example (these
abbreviations are not italicized).
An excellent style manual and source of information for
science writers is [9]. A general IEEE style guide and an
Information for Authors are both available at
http://www.ieee.org/web/publications/authors/transjnl/index.html

XIV. EDITORIAL POLICY

Submission of a manuscript is not required for
participation in a conference. Do not submit a reworked
version of a paper you have submitted or published
elsewhere. Do not publish preliminary data or results. The
submitting author is responsible for obtaining agreement of
all coauthors and any consent required from sponsors before

submitting a paper. IEEE T RANSACTIONS and JOURNALS

strongly discourage courtesy authorship. It is the obligation
of the authors to cite relevant prior work.
The Transactions and Journals Department does not
publish conference records or proceedings. The
TRANSACTIONS does publish papers related to conferences
that have been recommended for publication on the basis of
peer review. As a matter of convenience and service to the
technical community, these topical papers are collected and
published in one issue of the TRANSACTIONS.
At least two reviews are required for every paper
submitted. For conference-related papers, the decision to
accept or reject a paper is made by the conference editors and
publications committee; the recommendations of the referees
are advisory only. Undecipherable English is a valid reason
for rejection. Authors of rejected papers may revise and
resubmit them to the TRANSACTIONS as regular papers,
whereupon they will be reviewed by two new referees.

XV. PUBLICATION PRINCIPLES

The contents of IEEE TRANSACTIONS and JOURNALS are
peer-reviewed and archival. The TRANSACTIONS publishes
scholarly articles of archival value as well as tutorial
expositions and critical reviews of classical subjects and
topics of current interest.
Authors should consider the following points:
1) Technical papers submitted for publication must
advance the state of knowledge and must cite relevant
prior work.
2) The length of a submitted paper should be
commensurate with the importance, or appropriate to the
complexity, of the work. For example, an obvious
extension of previously published work might not be
appropriate for publication or might be adequately
treated in just a few pages.
3) Authors must convince both peer reviewers and the
editors of the scientific and technical merit of a paper;
the standards of proof are higher when extraordinary or
unexpected results are reported.
4) Because replication is required for scientific progress,
papers submitted for publication must provide sufficient
information to allow readers to perform similar
experiments or calculations and use the reported results.
Although not everything need be disclosed, a paper must
contain new, useable, and fully described information.
For example, a specimens chemical composition need
not be reported if the main purpose of a paper is to
introduce a new measurement technique. Authors should
expect to be challenged by reviewers if the results are not
supported by adequate data and critical details.
5) Papers that describe ongoing work or announce the latest
technical achievement, which are suitable for
presentation at a professional conference, may not be
appropriate for publication in a T RANSACTIONS or

> REPLACE THIS LINE WITH YOUR PAPER IDENTIFICATION NUMBER (DOUBLE-CLICK HERE TO EDIT) <

17

Congress, 1998. CIEP 98. VI IEEE International Year: 1998

Pages: 126 131.

JOURNAL.
[8]

XVI. CONCLUSION
Please include a brief summary of the possible clinical
implications of your work in the conclusion section.
Although a conclusion may review the main points of the
paper, do not replicate the abstract as the conclusion.
Consider elaborating on the translational importance of the
work or suggest applications and extensions.

A comparison between the buck, boost and buck-boost inverters.

J.Almazan; N. Vazquez; C. Hernandez; J. Alvarez; J. Arau Power
Electronics Congress, 2000. CIEP 2000. VII IEEE International Year:
2000 Pages: 341 - 346
[9] Analysis and experimental study of the buck, boost and buck-boost
inverters N. Vazquez; J. Almazan; J. Alvarez; C. Aguilar; J. Arau
Power Electronics Specialists Conference, 1999. PESC 99. 30th
Annual IEEE Year: 1999, Volume: 2 Pages: 801 - 806
[10] Z. Yao, L. Xiao, and Y. Yan, Dual-Buck Full-Bridge Inverter With
Hysteresis Current Control, IEEE Trans. Ind. Electron., vol. 56,
no.8, pp. 31533160, Aug. 2009.

APPENDIX
Appendixes,
if
acknowledgment.

needed,

appear

before

the

ACKNOWLEDGMENT
The preferred spelling of the word acknowledgment in
American English is without an e after the g. Use the
singular heading even if you have many
acknowledgments. Avoid expressions such as One of us
(S.B.A.) would like to thank ... . Instead, write F. A. Author
thanks ... . Sponsor and financial support
acknowledgments are placed in the unnumbered footnote
on the first page, not here.
REFERENCES

[1]

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 27,

NO. 2, FEBRUARY 2012 Fault-Tolerant Voltage Source Inverter for
Permanent Magnet Drives Rammohan Rao Errabelli and Peter
Mutschler, Member, IEEE.

[2]

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 26,

NO. 8, AUGUST 2011 Comparative Evaluation of Three-Phase
Current Source Inverters for Grid Interfacing of Distributed and
Renewable Energy Systems Benjamin Sahan, Member, IEEE, Samuel
V. Araujo , Student Member, IEEE, Christian Noding, and Peter
Zacharias, Member, IEEE

[3]

A Single-Stage Grid Connected Inverter Topology for Solar PV

Systems With Maximum Power Point Tracking Sachin Jain and Vivek
Agarwal, Senior Member, IEEE
Active Buck-Boost Inverter. yu tang, member iee, xianmei dong, and
yaohua he. Iee transactions on industrial electronics, vol..61. no. 9,
September 2014.

[4]

[5]

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 19,

NO. 5, SEPTEMBER 2004 1305 Topologies of Single-Phase
Inverters for Small Distributed Power Generators: An Overview
Yaosuo Xue, Student Member, IEEE, Liuchen Chang, Senior
Member, IEEE, Sren Bkhj Kjr, Member, IEEE, Josep Bordonau,
Member, IEEE, and Toshihisa Shimizu, Senior Member, IEEE.

[6]

Boost-Derived Hybrid Converter With Simultaneous DC and AC Ou

tputs Olive Ray; Santanu Mishra IEEE Transactions on Industry
Applications Year: 2014, Volume: 50, Issue: 2 Pages: 1082 - 1093
A buck-boost DC-AC converter: operation, analysis, and control R.
O. Caceres; W. M. Garcia; O. E. Camacho Power Electronics

[7]

First A. Author (M76SM81F87) and the other authors may include

biographies at the end of regular papers. Biographies are often not included
in conference-related papers. This author became a Member (M) of IEEE in
1976, a Senior Member (SM) in 1981, and a Fellow (F) in 1987. The first
paragraph may contain a place and/or date of birth (list place, then date).
Next, the authors educational background is listed. The degrees should be
listed with type of degree in what field, which institution, city, state, and
country, and year degree was earned. The authors major field of study
should be lower-cased.
The second paragraph uses the pronoun of the person (he or she) and not
the authors last name. It lists military and work experience, including
summer and fellowship jobs. Job titles are capitalized. The current job must
have a location; previous positions may be listed without one. Information
concerning previous publications may be included. Try not to list more than
three books or published articles. The format for listing publishers of a book
within the biography is: title of book (city, state: publisher name, year)
similar to a reference. Current and previous research interests end the
paragraph.
The third paragraph begins with the authors title and last name (e.g., Dr.
Smith, Prof. Jones, Mr. Kajor, Ms. Hunter). List any memberships in
professional societies other than the IEEE. Finally, list any awards and work
for IEEE committees and publications. If a photograph is provided, the
biography will be indented around it. The photograph is placed at the top
left of the biography. Personal hobbies will be deleted from the biography.