BARREL SHIFTER

entity Barrel_Shifter is
port(Q: inout bit_vector(7 downto 0):="10101101"; dir,CLK: in bit);
end Barrel_Shifter;
architecture arh_Barrel_Shifter of Barrel_Shifter is
begin
process(dir,CLK)
variable k: natural :=0;
begin
if(dir'event) then k:=0;end if;
if(CLK='1' and CLK'EVENT) then
if (dir='1' and k<3) then
Q<=Q sll 1;
Q(7)<='0';
k:=k+1;
end if;
if (dir='0' and k<3) then
Q<=Q srl 1;
Q(0)<='0';
k:=k+1;
end if;
end if;
end process;
end arh_Barrel_Shifter;

BUFFER
library

IEEE;

use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.std_logic_arith.all;
entity buf is
port(A: in std_logic_vector (7 downto 0);
S:in std_logic;
B: out std_logic_vector (7 downto 0));
end buf;
architecture arh_buf of buf is
begin
process(s,A)
variable B1: std_logic_vector (7 downto 0);
begin
if S='1' then B1:=A; end if;
B<=B1;
end process;
end arh_buf;
library
IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.std_logic_arith.all;
entity ms_buf is
end ms_buf;
architecture arh_ms_buf of ms_buf is
signal
A,B: std_logic_vector (7 downto 0):="00000000";
signal S: std_logic;
component buf
port(A: in std_logic_vector (7 downto 0);
S: in std_logic;
B: out std_logic_vector (7 downto 0));
end component;
begin
UST: buf port map (A,S,B);
process
begin
S<='1';
A<="00000000";
wait for 10 ns;
for i in 0 to 254 loop
A<=A+1;
wait for 10 ns;
end loop;
wait;
end process;
end arh_ms_buf;

COMPARATOR
entity comparator is
port (A,B,C,D : in bit;
Y: out bit);
end comparator;
architecture arh_comparator of comparator is
signal Y1,Y2: bit;
component poarta_si
port(A,B :in bit;
Y: out bit);
end component;
component poarta_coincidenta
port(A,B :in bit;
Y: out bit);
end component;
begin
C1: poarta_si port map(Y1,Y2,Y);
C2: poarta_coincidenta port map (A,C,Y1);
C3: poarta_coincidenta port map (B,D,Y2);
end arh_comparator;
entity poarta_si is
port(A,B :in bit;
Y: out bit);
end poarta_si;
architecture arh_poarta_si of poarta_si is
begin
Y<=A and B;
end arh_poarta_si;
entity poarta_coincidenta is
port(A,B :in bit;
Y: out bit);
end poarta_coincidenta;
architecture arh_poarta_coincidenta of poarta_coincidenta is
begin
Y<=not(A xor B);
end arh_poarta_coincidenta;

DMUX 1 8
entity dmux1_8 is
port (I: in bit;
sel : in bit_vector (2 downto 0);
Y: out bit_vector (7 downto 0));
end dmux1_8;
architecture arh_dmux of dmux1_8 is
begin
Y <=('0','0','0','0','0','0','0',I) when sel="000" else
('0','0','0','0','0','0',I,'0') when sel="001" else
('0','0','0','0','0',I,'0','0') when sel="010" else
('0','0','0','0',I,'0','0','0') when sel="011" else
('0','0','0',I,'0','0','0','0') when sel="100" else
('0','0',I,'0','0','0','0','0') when sel="101" else
('0',I,'0','0','0','0','0','0') when sel="110" else
(I,'0','0','0','0','0','0','0') when sel="111";
end arh_dmux;
entity modul_simulare_dmux is
end modul_simulare_dmux;
architecture arh_modul_dmux of modul_simulare_dmux is
component dmux1_8
port (I: in bit;
sel : in bit_vector (2 downto 0);
Y: out bit_vector (7 downto 0));
end component;
signal I:bit ;
signal sel : bit_vector (2 downto 0) :="000";
signal Y: bit_vector (7 downto 0) :="00000000";
begin
UST : dmux1_8 port map (I=>I,sel=>sel,Y=>Y);
STIM: process
begin
I <= '1';
wait for 40 ns;

Sel <= "000";

wait for 40 ns;
Sel <= "001";
wait for 40 ns;
Sel <= "010";
wait for 40 ns;
Sel <= "011";
wait for 40 ns;
Sel <= "100";
wait for 40 ns;
Sel <= "101";
wait for 40 ns;
Sel <= "110";
wait for 40 ns;
Sel <= "111";
wait for 40 ns;
wait;
end process STIM;
end arh_modul_dmux;

FIFO
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity fifo is
port ( clk : in std_logic;
enr : in std_logic;
enw : in std_logic;
dataout : out std_logic_vector(1 downto 0);
datain : in std_logic_vector (1 downto 0);
empty : out std_logic;
full : out std_logic
);
end fifo;
architecture Behavioral of fifo is
type memory_type is array (0 to 3) of std_logic_vector(1 downto 0);
signal memory : memory_type :=(others => (others => '0'));
signal readptr,writeptr : std_logic_vector(1 downto 0) :="00";
begin
process(clk)
begin
if(clk'event and clk='1' and enr ='1') then
dataout <= memory(conv_integer(readptr));
--error <= '0';

readptr <= readptr + '1';

end if;
if(clk'event and clk='1' and enw ='1') then
memory(conv_integer(writeptr)) <= datain;
writeptr <= writeptr + '1';
end if;
if(readptr = "11") then
readptr <= "00";
end if;
if(writeptr = "11") then
full <='1';
writeptr <= "00";
else
full <='0';
end if;
if(writeptr = "00") then
empty <='1';
else
empty <='0';
end if;
end process;
end Behavioral;

JK
entity JK is
port(J,K,S,R,CLK: in bit;
Q,nQ: out bit);
end JK;
architecture arh_JK of JK is
begin
process(J,K,S,R,CLK)
variable Q1: bit;
variable stare_anterioara: bit;
begin
if (CLK='1' and CLK'EVENT) then

if(J='0' and K='0') then Q1:=stare_anterioara;

elsif(J='0' and K='1') then Q1:='0';
elsif(J='1' and K='0') then Q1:='1';
else Q1:=not(stare_anterioara);
end if;
end if;
stare_anterioara:=Q1;
Q<=Q1;
nQ<=not(Q1);
end process;
end arh_JK;

MS JK
library
IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.std_logic_arith.all;
entity buf is
port(A: in std_logic_vector (7 downto 0);
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity ms_jk is
end ms_jk;
architecture arh_ms_jk of ms_jk is
component jk
port(J,K,S,R,CLK: in bit;
Q,nQ: out bit);
end component;
signal J,K,S,R,CLK: bit;
signal Q,nQ : bit;
shared variable
end_sim : boolean := false;
begin
UST: JK port map (J=>J,K=>K,S=>S,R=>R,CLK=>CLK,Q=>Q,nQ=>nQ);
process
begin
if not end_sim then
CLK <='0';

wait for 20 ns;

CLK<='1';
wait for 20 ns;
else wait;
end if;
end process;
process
begin
wait for 40 ns;
J<='0'; K<='0';
wait for 40 ns;
J<='1'; K<='0';
wait for 40 ns;
J<='0'; K<='1';
wait for 40 ns;
J<='1'; K<='1';
wait for 40 ns;
end_sim:= true;
wait;
end process;
end arh_ms_jk;

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity JK is
port(J,K,S,R,CLK: in bit;
Q,nQ: out bit);
end JK;

JK

architecture arh_JK of JK is
begin
process(J,K,S,R,CLK)
variable Q1: bit;
variable stare_anterioara: bit;
begin
if (CLK='1' and CLK'EVENT) then
if(J='0' and K='0') then Q1:=stare_anterioara;
elsif(J='0' and K='1') then Q1:='0';
elsif(J='1' and K='0') then Q1:='1';
else Q1:=not(stare_anterioara);
end if;
end if;

stare_anterioara:=Q1;
Q<=Q1;
nQ<=not(Q1);
end process;
end arh_JK;

MUX
entity mux is
generic (nr_intrari :natural :=15; nr_selectii : natural :=3);
port( A : in bit_vector (0 to nr_intrari);
sel: in bit_vector (0 to nr_selectii);
Y: out bit);
end mux;
architecture arh_mux of mux is
begin
process(sel)
begin
if sel="0000" then
if sel="0001" then
if sel="0010" then
if sel="0011" then
if sel="0100" then
if sel="0101" then
if sel="0110" then
if sel="0111" then
if sel="1000" then
if sel="1001" then
if sel="1010" then
if sel="1011" then
if sel="1100" then
if sel="1101" then
if sel="1110" then

Y<=A(0); end if;

Y<=A(1); end if;
Y<=A(2); end if;
Y<=A(3); end if;
Y<=A(4); end if;
Y<=A(5); end if;
Y<=A(6); end if;
Y<=A(7); end if;
Y<=A(8); end if;
Y<=A(9); end if;
Y<=A(10); end if;
Y<=A(11); end if;
Y<=A(12); end if;
Y<=A(13); end if;
Y<=A(14); end if;

if sel="1111" then Y<=A(15); end if;

end process;
end arh_mux;

NUMARATOR P10

library
IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.std_logic_arith.all;
entity numarator_p10 is
port(clk, dir,pl,rst: in std_logic;
nr_pl: in std_logic_vector (3 downto 0);
num: out std_logic_vector (3 downto 0));
end numarator_p10;
architecture arh_nr of numarator_p10 is
begin
process(clk)
variable count: std_logic_vector(3 downto 0):="0000";
begin
if clk='1' and clk'event then
if rst='1' then count :="0000";
elsif pl='1' then count:=nr_pl;
else
if dir='1' then
if count /="1001" then
count:=count+1;
else count:="0000"; end if;
else
if count /="0000" then
count:=count-1;
else count:="1001"; end if;
end if;
end if;
end if;
num<=count;
end process;
end arh_nr;

NUMARATOR
library
IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.std_logic_arith.all;
entity numarator is
port(clk, dir,pl,rst: in std_logic;
nr_pl: in std_logic_vector (7 downto 0);
num: out std_logic_vector(7 downto 0));
end numarator;
architecture arh_n of numarator is
begin
process(clk)
variable count: std_logic_vector(7 downto 0):="00000000";
begin
if clk='1' and clk'event then
if rst='1' then count :="00000000";
elsif pl='1' then count:=nr_pl;
else
if dir='1' then
count:=count+1;
else count:=count-1;
end if;
end if;
end if;
num<=count;
end process;
end arh_n;

library
IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.std_logic_arith.all;

entity numar is
port(clock : in std_logic;
rst: in std_logic;
Q: out std_logic_vector (7 downto 0));
end numar;
architecture arh_numar of numar is
signal ei1,eo1,ei2,eo2,ei3,eo3,ei4,eo4: bit;
signal Y0,Y1,Y2,Y3: std_logic_vector (0 to 1);
component numarator_p11
port(clk,rst: in std_logic;
enable :in bit :='1';
enable_out : out bit;
num: out std_logic_vector(0 to 1));
end component;

begin
C1: numarator_p11 port map
C2: numarator_p11 port map
C3: numarator_p11 port map
C4: numarator_p11 port map
Q(0)<=Y0(1); Q(1)<=Y0(0);
Q(2)<=Y1(1); Q(3)<=Y1(0);
Q(4)<=Y2(1); Q(5)<=Y2(0);
Q(6)<=Y3(1); Q(7)<=Y3(0);
end arh_numar;

(
(
(
(

clock,rst,'1',eo1,Y0);
clock,rst,eo1,eo2,Y1);
clock,rst,eo2,eo3,Y2);
clock,rst,eo3,eo4,Y3);

library
IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.std_logic_arith.all;
entity numarator_p11 is
port(clk,rst: in std_logic;
enable :in bit :='1';
enable_out : out bit;
num: out std_logic_vector(1 downto 0));
end numarator_p11;
architecture arh_numarator_p11 of numarator_p11 is
begin
process(clk)
variable count: std_logic_vector(1 downto 0):="00";
variable enable1: bit;
begin

enable1:=enable;
if enable='1' then
if clk='1' and clk'event then
if rst='1' then count :="00";
else
count:=count+1;
end if;
end if;
if count="11" then enable1:='1';
else enable1:='0';
end if;
num<=count;
enable_out<=enable1;
end process;

end if;

end arh_numarator_p11;

library
IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.std_logic_arith.all;
entity num2 is
port (pl,rst,clk : in std_logic;
nr_pl: in std_logic_vector (1 downto 0);
B: out std_logic_vector (1 downto 0));
end entity;
architecture arh_num2 of num2 is
begin
process (clk)
variable A1: std_logic_vector(1 downto 0):="00";
begin
if clk='1' and clk'event then
if rst='1' then B<="00";
elsif pl='1' then B<=nr_pl;
else
A1:=A1+1;
B<=A1;
end if;
end if;
end process;
end arh_num2;

library
IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.std_logic_arith.all;
entity ms_num2 is
end ms_num2;
architecture arh_ms_num2 of ms_num2 is
signal pl,rst :std_logic;
signal clk :std_logic;
signal nr_pl, B : std_logic_vector (1 downto 0) :="00";
shared variable end_sim : boolean := false;
component num2
port (pl,rst,clk : in std_logic;
nr_pl: in std_logic_vector (1 downto 0);
B: out std_logic_vector (1 downto 0));
end component;
begin
UST: num2 port map (pl,rst,clk,nr_pl,B);
process
begin
if not(end_sim) then
clk<='0';
wait for 10 ns;
clk<='1';
wait for 10 ns;
else wait;
end if;
end process;
process
begin
if not(end_sim) then
B<="00";
wait for 20 ns;
B<="01";
wait for 20 ns;
B<="10";
wait for 20 ns;
B<="11";
wait for 20 ns;
end_sim:=true;
end if;
end process;
end arh_ms_num2;

library
IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pseudo is
port (clk : in bit;
Q_0, Q_1,Q_2 : out std_logic);
end pseudo;
architecture arh_pseudo of pseudo is
signal nQ0, nQ1,nQ2 : std_logic:='0' ;
signal Q0,Q1,Q2: std_logic:='1' ;
signal Y : std_logic ;
signal Y1: std_logic;
component sau_exclusiv
port (A,B :in std_logic;
C: out std_logic);
end component;
component bist_RS
port (S,R :in std_logic;
clk: in bit;
Q,nQ : out std_logic);
end component;
begin
C1:
C2:
C3:
C4:

sau_exclusiv port map(Q2,Q0,Y);

bist_RS port map (Y,Y1,clk,Q0,nQ0);
bist_RS port map (Q0,nQ0,clk,Q1,nQ1);
bist_RS port map (Q1,nQ1,clk,Q2,nQ2);

Q_0<=Q0;
Q_1<=Q1;
Q_2<=Q2;
Y1<=not(Y);

end arh_pseudo;

library
IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity bist_RS is
port (S,R :in std_logic;
clk: in bit;
Q,nQ : out std_logic);
end bist_RS;
architecture arh_bist_RS of bist_RS is
signal Q_ant: std_logic;
begin
process (R,S,CLK)
variable Q1: std_logic:='1';
variable nQ1: std_logic:='0';
begin
if clk='1' and clk'event then
if S='0' and R='0' then Q1:=Q_ant; nQ1:=not (Q_ant);
elsif S='0' and R='1' then
Q1:='0'; nQ1:= '1';
elsif S='1' and R='0' then
Q1:='1'; nQ1:= '0';
elsif S='1' and R='1' then Q1:='X'; nQ1:= 'X';
end if;
Q_ant<=Q1;
Q<=Q1;
nQ<=nQ1;
end if;
end process;
end arh_bist_RS;
library
IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity sau_exclusiv is
port (A,B :in std_logic;
C: out std_logic);
end sau_exclusiv;
architecture arh_sau_ex of sau_exclusiv is
begin
C<=A xor B;
end arh_sau_ex;

entity reclama is
port(intrerupator :in bit;
af1,af2:in bit;
stins:out bit);
end reclama;
architecture arh_reclama of reclama is
begin
process
begin
if intrerupator= '1' then
stins<='0'; wait for 40 ns;
if af1='1' then
report "test_psn";
elsif af2='1' then
report "rezultat_psn";
elsif intrerupator= '0' then
stins<='1';
wait for 60 ns;
end if;
end process;
end arh_reclama;

end if;

library
IEEE;
use IEEE.std_logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use IEEE.std_logic_arith.all;
entity num2 is
port (pl,rst,clk : in std_logic;
nr_pl: in std_logic_vector (1 downto 0);
B: out std_logic_vector (1 downto 0));
end entity;

architecture arh_num2 of num2 is

begin
process (clk)
variable A1: std_logic_vector(1 downto 0):="00";
begin
if clk='1' and clk'event then
if rst='1' then B<="00";
elsif pl='1' then B<=nr_pl;
else
A1:=A1+1;
B<=A1;
end if;
end if;
end process;
end arh_num2;
entity registruu_de_deplasare is
port(Sel, CLK: in bit;
Q:inout bit_vector(7 downto 0):="10010001");
end entity registruu_de_deplasare;
architecture arh3 of registruu_de_deplasare is
begin
process (CLK,Sel)
variable Q1: bit_vector(7 downto 0);
begin
Q1:=Q;
if (CLK'event) and (CLK='1') then
if Sel='1' then Q1:=Q1 sll 1; Q1(0) :='0';
else Q1:=Q1 srl 1; Q1(7) :='0';end if;
Q<=Q1;
end if;
end process;
end;
entity MSS_registru is
end MSS_registru;
architecture arh_MS_registru of MSS_registru is
signal Sel, CLK: bit;
signal Q: bit_vector(7 downto 0);
shared variable END_SIM: BOOLEAN := false;
component registruu_de_deplasare
port(Sel, CLK: in bit;
Q:inout bit_vector(7 downto 0));
end component;
begin
UST: registruu_de_deplasare port map(Sel, CLK, Q);
GENERARE_TACT: process

begin
if not(END_SIM) then
CLK<='1';
wait for 10 ns;
CLK<='0';
wait for 10 ns;
else wait;
end if;
end process GENERARE_TACT;
MS: process
begin
sel<='1';
wait for 80ns;
sel<='0';
wait for 80ns;
END_SIM:=true;
wait;
end process MS;
end arh_MS_registru;

library
IEEE;
use IEEE.std_logic_1164.all;
entity registru_universal is
port ( A: in bit_vector (3 downto 0);
sel: in bit_vector(1 downto 0);
clk :in bit;
Q: out bit_vector (3 downto 0));
end registru_universal;
architecture arh_registru of registru_universal is

begin
process(A,sel,clk)
variable A1,Q1 : bit_vector (3 downto 0):="0000";
begin
A1:=A;
if clk='1' and clk'event then
if sel="01" then
Q1:=Q1 srl 1; Q1(3):='0';
elsif sel="10" then
Q1:=Q1 sll 1; Q1(0):='0';
elsif sel="11" then
Q1(0):=A1(0);
Q1(1):=A1(1);
Q1(2):=A1(2);
Q1(3):=A1(3);
end if;
end if;
Q<=Q1;
end process;
end arh_registru;

entity ROM is
port(I: in natural;
Y: out bit_vector(0 to 15));
end ROM;
architecture arh_ROM of ROM is
begin
process(I)
type ROM is array(0 to 15) of bit_vector(0 to 15);
variable X:ROM;
begin
X(0) :="1000000000000000";
X(1) :="0100000000000000";
X(2) :="0010000000000000";
X(3) :="0001000000000000";
X(4) :="0000100000000000";

X(5) :="0000010000000000";
X(6) :="0000001000000000";
X(7) :="0000000100000000";
X(8) :="0000000010000000";
X(9) :="0000000001000000";
X(10):="0000000000100000";
X(11):="0000000000010000";
X(12):="0000000000001000";
X(13):="0000000000000100";
X(14):="0000000000000010";
X(15):="0000000000000001";
Y<=X(I);
end process;
end arh_ROM;

entity ms_scazator is
end ms_scazator;
architecture arh_ms_scazator of ms_scazator is
signal A,B,borrow_in, borrow_out, Y :bit;
component scazator
port (A,B, borrow_in: in bit;
borrow_out,Y: out bit);
end component;

begin
UST : scazator port map
(A=>A,B=>B,borrow_in=>borrow_in,borrow_out=>borrow_out,Y=>Y);
process
begin
borrow_in<='1';
A<='0'; B<='0';
wait for 20 ns;
A<='0'; B<='1';
wait for 20 ns;
A<='1'; B<='0';
wait for 20 ns;
A<='1'; B<='1';
wait for 20 ns;

borrow_in<='0';
A<='0'; B<='0';
wait for 20 ns;
A<='0'; B<='1';
wait for 20 ns;
A<='1'; B<='0';
wait for 20 ns;
A<='1'; B<='1';
wait for 20 ns;
wait;
end process;
end arh_ms_scazator;
entity scazator is
port (A,B, borrow_in: in bit;
borrow_out,Y: out bit);
end scazator;
architecture arh_scazator of scazator is
begin
process (A,B,borrow_in)
variable borrow_out1 : bit;
begin
if borrow_in='1' then
if (A='0' and B='0') then Y<='1'; borrow_out1:='1';
elsif(A='0' and B='1') then Y<='0'; borrow_out1:='1';
elsif (A='1' and B='0') then Y<='0'; borrow_out1:='0';
elsif(A='1' and B='1') then Y<='1'; borrow_out1:='1';
end if;
else
if (A='0' and B='0') then Y<='0'; borrow_out1:='0';
elsif(A='0' and B='1') then Y<='1'; borrow_out1:='1';
elsif (A='1' and B='0') then Y<='1'; borrow_out1:='0';
elsif(A='1' and B='1') then Y<='0'; borrow_out1:='0';
end if;
end if;
borrow_out<=borrow_out1;
end process;
end arh_scazator;

entity secv is
port (A :in bit;
clk: in bit;
B:out bit_vector (3 downto 0));
end secv;
architecture arh_secv of secv is
begin
process (A,clk)
variable B1: bit_vector (3 downto 0):="0000";
begin
if clk='1' and clk'event then
B1:=B1 srl 1;
B1(3):=A;
if B1="1100" then report "secventa a fost detectata";
end if;
end if;
B<=B1;
end process;
end architecture;

library
IEEE;
use IEEE.std_logic_1164.all;
entity sum_scaz is
port(A,B :in std_logic_vector (3 downto 0);
sel:in std_logic;
carry_out :out std_logic;
Y1: out std_logic_vector (3 downto 0));
end sum_scaz;
architecture arh_sum_scaz of sum_scaz is
signal A2 : std_logic_vector (3 downto 0):="0000";

begin
process(A,B,sel)
variable Y,C: std_logic_vector(3 downto 0);
variable A1,B1 : std_logic_vector (3 downto 0):="0000";
variable ok: bit :='0';
begin
A1:=A;
B1:=B;
if sel='1' then
if (A(0) and B(0)) ='1' then C(0):='1'; Y(0):='0';
else Y(0):= (A(0) or B(0)); C(0):='0'; end if;
for i in 1 to 3 loop
if (A(i) and B(i)) ='1' then
if C(i-1)='1' then C(i):='1'; Y(i):='1';
else C(i):='1'; Y(i):='0'; end if;
elsif (A(i) or B(i))='1' then
if C(i-1)='1' then Y(i):='0'; C(i):='1';
else Y(i):='1'; C(i):='0'; end if;
else Y(i):=C(i-1); C(i):='0';
end if;
end loop;
Y1<=Y;
carry_out<=C(3);

else
ok:='0';
if A1<B1 then
for i in 0 to 3 loop
if ok='1' then
A1(i):= not(A1(i)); end if;
if A1(i)='1' then ok:='1'; end if;
end loop;
else
for i in 0 to 3 loop
if ok='1' then
B1(i):= not(B1(i)); end if;
if B1(i)='1' then ok:='1'; end if;
end loop;
end if;
if (A1(0) and B1(0)) ='1' then C(0):='1'; Y(0):='0';
else Y(0):= (A1(0) or B1(0)); C(0):='0'; end if;
for i in 1 to 3 loop
if (A1(i) and B1(i)) ='1' then
if C(i-1)='1' then C(i):='1'; Y(i):='1';
else C(i):='1'; Y(i):='0'; end if;
elsif (A1(i) or B1(i))='1' then
if C(i-1)='1' then Y(i):='0'; C(i):='1';
else Y(i):='1'; C(i):='0'; end if;
else Y(i):=C(i-1); C(i):='0';

end if;
end loop;
Y1<=Y;
carry_out<=C(3);
end if;
end process;
end arh_sum_scaz;