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Introduction to VLSI

(1987 to Till Date)

1988

1.

1.

better than the P-channel type in the following

respects

a.

It has better noise immunity

b. It is faster

c.

It is TTL compatible

d. It has better drive capability

Answer: B & D

Solution

: https://www.youtube.com/watch?v=i0tBM4

SR3ug

1989

In a MOSFET, the polarity of the inversion

layer is the same as that of the

a.

Charge on the gate electrode

b. Minority carriers in the drain

c.

Majority carriers in the substrate

d. Majority carriers in the source

Answer: D

Solution

: https://www.youtube.com/watch?v=EoJQB

Xa0NT0

Answer: 1 mA

Solution

: https://www.youtube.com/watch?v=VPgDje

UybI4

1992

1. An n-channel MOSFET having a threshold

voltage of 2 volts is used in the circuit shown in

figure. Initially the transistor is OFF and is in

steady state. At time t = 0, a step voltage of

magnitude of 4 volts is applied to the input so

that the MOSFET turns ON instantaneously.

Draw the equivalent circuit and calculate the

time taken to the output Vo to fall to 5 volts.

The device constant of the MOSFET, K = 5

mA/ V2, CDS =0 and CDG = 0.

1990

1. Which of the following effects can be

caused by a rise in the temperature ?

a. Increase in MOSFET current

b. Increase in BJT current

c. Decrease in MOSFET current

d. Decrease in BJT current

Answer: B & C

Solution

: https://www.youtube.com/watch?v=BoRoL

Q2eN6o

Solution

: https://www.youtube.com/watch?v=ccRFcF

5_sQQ

1991

1.

MOSFETs are identical and their current

voltage characteristics are given by the

following expressions.

Find the current IDC as shown

1.

1994

The threshold voltage of an n-channel

MOSFET can be increased by

a.

Increasing the channel dopant

concentration

b. Reducing the channel dopant

concentration

c.

Reducing the gate oxide thickness

d. Reducing the channel length

Answer: A

Solution

: https://www.youtube.com/watch?v=1C8Crs

Gguu0

: https://www.youtube.com/watch?v=Uc3Eu

Oto9Pk

1998

2.

through the channel of an FET decides its

. characteristics.

Answer: Switching

Solution

: https://www.youtube.com/watch?v=vQJjm

HNsn3I

3.

a more positive voltage to the gate of a

depletion mode n-channel MOSFET. (TRUE /

FALSE)

Answer: False

Solution

: https://www.youtube.com/watch?v=W34k

Wifl15o

1.

figure is 2 volts. For this circuit to work as an

inverter, Vi must take the values

a.

-5 volts and 0 volts

b. -5 volts and 5 volts

c.

0 volts and 3 volts

d. 3 volts and 5 volts

Answer: A

Solution

: https://www.youtube.com/watch?v=pHfKL4

yw4Ko

4.

A typical CMOS inverter has the voltage

transfer characteristic (VTC) curve as shown in

the figure.

Evaluate the value of the

inverter threshold VINV, which is the value of

the input at which Vo falls

by

Vo = VTn + VTp.

3.

specifications of the circuit are :

VDD = 10 volts, = nCox(W/L) = 10-4 Amp/V2,

VT = 1 volt and IDS = 0.5 mA.

Evaluate VDS and RD. Neglect body effect.

Answer:

Solution

1999

1.

figure, the input Vi makes a transition from

VOL (= 0 volts) to VOH (= 5 volts). Determine

the High to Low propagation delay time (tpHL)

when it is driving a capacitive load (CL) of 20

pF.

Device data :

Answer:

Solution

0.156 Sec

: https://www.youtube.com/watch?v=0t8YIe

h7E_0

a.

Only S1 is TRUE

b. Only S2 is TRUE

c.

Both are TRUE

d. Both are FALSE

Answer: A

Solution

: https://www.youtube.com/watch?v=lm9CG

4kv7NU

2001

1.

2.

a.

Current controlled capacitor

b. Voltage controlled capacitor

c.

Current controlled inductor

d. Voltage controlled inductor

Answer: B

Solution

: https://www.youtube.com/watch?v=DYvtwv

byh8Q

The effective channel length of a MOSFET in

saturation decreases with increase in

a.

Gate voltage

b. Drain voltage

c.

Source voltage

d. Body voltage

Answer: B

Solution

: https://www.youtube.com/watch?v=yySAO

Iv7hiw

2002

1.

connection with the CMOS inverter in figure,

where both the MOSFETs are of enhancement

type and both have a threshold voltage of 2

volts.

S2: T1 is always in saturation when

Vo = 0 volts.

2003

1.

is connected at a higher potential than that of

the bulk (i.e. VSB > 0 volts), the threshold

voltage VT of the MOSFET will

a.

Remain unchanged

b. Decrease

c.

Change polarity

d. Increase

Answer: D

Solutoin

: https://www.youtube.com/watch?v=NkWe

ND6-BxI

MOSFET with threshold voltage of 400 mV.

The drain current observed is 1 mA. Neglecting

the channel length modulation effect, and

assuming that the MOSFET is operating at

saturation, the drain current for an applied

VGS of 1400 mV is

a.

0.5 mA

b. 2.0 mA

c.

3.5 mA

d. 4.0 mA

Answer: D

Solutoin

: https://www.youtube.com/watch?v=jvXncir

hK9c

metallization and S is source/drain diffusion,

then the order in which they are carried out in

a standard n-well CMOS fabrication process is

a.

P-Q-R-S

b. Q-S-R-P

c.

R-P-S-Q

d. S-R-Q-P

Answer: B

Solutoin

: https://www.youtube.com/watch?v=dS__K

GppUig

2005

2004

1.

characteristic of

1.

is shown in figure, then the threshold voltage

is

Answer: C

Solution

: https://www.youtube.com/watch?v=lPY4Xz

AWeSg

2.

a.

b.

c.

d.

S1: the threshold voltage (VT) of a MOS

capacitor decreases with increase in gate oxide

thickness

S2: the threshold voltage (VT) of a MOS

capacitor decreases with increase in substrate

doping concentration.

Which of the following is correct?

S1 is FALSE and S2 is TRUE

Both S1 and S2 are TRUE

S1 is TRUE and S2 is FALSE

Both S1 and S2 are FALSE

Answer: C

Solution

: https://www.youtube.com/watch?v=UYrsnuQIlU

2.

threshold voltage of 1 volt. The device

parameters K1 and K2 of T1 and T2 are

36 A/v2 and 9 A/v2 respectively. The output

voltage Vo is

Answer: D

Solution

: https://www.youtube.com/watch?v=jmKFR

Cr0xa0

3. The drain of an N channel MOSFET is shorted

to the gate so that VGS = VDS. The threshold

voltage (VT) of MOSFET is 1 volt. If the drain

current (ID) is 1 mA for VGS = 2 volts, then for

VGS = 3 volts, ID is

a.

2 mA

b. 3 mA

c.

9 mA

d. 4 mA

Answer: D

Solution

: https://www.youtube.com/watch?v=F1cZOG

LgZIA

Answer: C

Solution

: https://www.youtube.com/watch?v=6fIMwx

zffIo

is in the accumulation mode. The dominant

charge is due to the presence of

a.

Holes

b. Electrons

c.

Positively charged ions

d. Negatively charged ions

Answer: A

Solution

: https://www.youtube.com/watch?v=jlQ_ny0

L4C0

: https://www.youtube.com/watch?v=iwERJ

Kn2hUU

2.

Transconductance parameters of the NMOS

and PMOS transistors are Kn =

Kp = nCox(Wn/Ln) = pCox(Wp/Lp) =

40A/V2 and their threshold voltages are VTn =

|VTp| = 1 volt, the current I is

2006

1.

following two points on its ID verses VGScurve

are

(i) VGS = 0 at ID = 12 mA and

(ii) VGS = -6 volts at ID = 0 mA

Which of the following Q-points will give the

highest Transconductance gain for small

signals?

a.

VGS = -6 volts

b. VGS = -3 volts

c.

VGS = 0 volts

d. VGS = 3 volts

Answer: D

Solution

: https://www.youtube.com/watch?v=Kxd4IZ

qv1vU

2007

1.

devices. Match each device in Group I with its

characteristic property in Group II.

Answer:

Solution

a.

0 Amp

b. 25 A

c.

45 A

d. 90 A

Answer: D

Solution

: https://www.youtube.com/watch?v=wtboLp

HXLOA

3. The figure shows the high frequency

capacitance voltage (C V) characteristics of

MOS capacitor having an area of 1x10-4 cm2.

Assume that the permittivity of silicon and

SiO2 are 1x10-12 and 3.5x10-13 F/cm

respectively.

i.

The gate oxide thickness in the

MOS capacitor is

a.

50 nm

b. 143 nm

c.

350 nm

d. 1 m

Answer: A

ii.

The maximum depletion layer

width in silicon is

a.

0.143 m

b. 0.857 m

c.

1 m

d. 1.143 m

Answer: B

iii.

Consider the following

statements about the C V characteristics plot

:

S1: The MOS capacitor has an N type

substrate

S2: If the positive charges are introduced in

the oxide, the C V plot will shift to the left.

Then which one of the following is TRUE .

a. Both S1 and S2 are TRUE

b. S1 is TRUE and S2 is FALSE

c. S1 is FALSE and S2 is

TRUE

d. Both S1 and S2 are FASLE

Answer: C

Answer: B

Solution

: https://www.youtube.com/watch?v=pYDNlQ

anv2g

3.

transistors M1 and M2 are identical NMOS

transistors. Assume that M2 is in saturation

and the output is unloaded. The IX is related to

Ibias as

Solution

: https://www.youtube.com/watch?v=IKyIj6

hVTL8

Answer: B

Solution

: https://www.youtube.com/watch?v=CBXqcv

lx97A

2008

1.

2.

is inserted in a furnace at a temperature above

1000oC for further oxidation in dry oxygen.

The oxidation rate

a.

Is independent of current oxide

thickness and temperature

b. Is independent of current oxide

thickness but depends on temperature

c. Slows down as the oxide grows

d. Is zero as the existing oxide prevents

further oxidation

Answer: A

Solution

: https://www.youtube.com/watch?v=6yl7336

P2kA

4.

NMOS transistor operating in the linear region

is plotted against the gate voltage VG at

constant drain voltage VD. Which of the

following figures represents the expected

dependence of gm on VG?

is given by ID = K(VGS-VT)2, where K is a

constant. The magnitude of the

Transconductance gm is

Answer: A

Solution

: https://www.youtube.com/watch?v=KE_ML

vt-M-4

source to drain

Which of the following is correct?

a.

Both are TRUE

b. Both are FALSE

c.

Both are TRUE, but S2 is not a reason

for S1

d. Both are TRUE, and S2 is a reason for

S1.

Answer: D

Solution

: https://www.youtube.com/watch?v=qbq2JX

NCe_Q

are connected as shown below. Vbias is chosen

so that both transistors are in saturation. The

equivalent gm of the pair is defined to be dIout /

dVi at constant Vout, is

3.

a.

The sum of individual gms of the

transistors

b. The product of individual gms of the

transistors

c.

Nearly equal to the gm of M1

d. Nearly equal to gm1/gm2 of M2

Answer: C

Solution

: https://www.youtube.com/watch?v=oySwK

D3Vtjg

2009

1.

CMOS in reference to logic families are

a. Triple Transistor Logic and Chip Metal

Oxide semiconductor

b. Tristate Transistor Logic and Chip Metal

Oxide semiconductor

c. Transistor Transistor Logic and

Complementary Metal Oxide semiconductor

d. Tristate Transistor Logic and

Complementary Metal Oxide semiconductor

Answer: C

Solution

: https://www.youtube.com/watch?v=v0BYB0NkMI

2.

the internal conditions in an N channel

MOSFET operating in the active region.

S1: the inversion charge decreases from source

to drain

Linked Questions:

Consider the CMOS circuit shown, where the

gate voltage VG of the N channel MOSFET is

increased from zero, while the gate voltage of

the P channel MOSFET is kept constant at 3

volts. Assume that, for both transistors, the

magnitude of the threshold voltage is 1 volts

and the product of the transconductance

parameter and the (W/L) ratio i.e. the quantity

cox(W/L) is 1 mA/V2.

i.

For small increase in

VG beyond 1 volt, which of the following gives

the correct description of the region of

operation of each MOSFET?

a.

Both are in saturation region

b. Both are in triode region

c.

NMOS is in triode region

and PMOS is in saturation region

d. NMOS is in saturation region

and PMOS is in triode region

Answer: D

ii.

Estimate the output voltage,

Vo for VG = 1.5 volts. (Hint: use the appropriate

current voltage equation for each MOSFET,

based on the answer to above question)

Answer: C

Solution

: https://www.youtube.com/watch?v=_BU3w

B8FoBA

Solution

: https://www.youtube.com/watch?v=4J00rS

wlU6U

2010

1.

2.

mobility of electrons in the inversion layer of a

silicon N channel MOSFET is (in cm2/volt-sec)

a.

450

b. 1350

c.

1800

d. 3600

Answer: B

Solution: https://www.youtube.com/watch?v

=bXxmszDCh1U

2012

1.

preferably grown using

a.

Wet oxidation

b. Dry oxidation

c.

Epitaxial deposition

d. Ion implantation

Answer: B

Solution

: https://www.youtube.com/watch?v=7bi7sX

WZYEc

Answer: A

Solution

: https://www.youtube.com/watch?v=AOa8c

OFX7WA

2011

1.

transistors, ncox = 100 A/V2 and the

threshold voltage VT = 1 volt. The voltage VX at

the source of the upper transistor is

a.

1 volt

b. 2 volts

c.

3 volts

d. 0.367 volts

Answer: C

expression Y is

2.

hole motilities are equal, and M1 and

M2transistors are equally sized. The device

M1 is in the linear region if

Answer: A

Solution

: https://www.youtube.com/watch?v=Geh8H

iqWIoU

3.

channel MOS transistor shown below, = 20

nm. The transistor is of width 1 m. The

depletion width formed at every PN junction is

10 nm. The relative permittivitys of Si and

SiO2 are 11.7 and 3.9 respectively and 0 = 8.9

X 10-12 F/m.

Hius8

2.

the channel length modulation effect causes

a.

An increase in gate source

capacitance

b. A decrease in Transconductance

c.

A decrease in unity gain bandwidth

product

d. A decrease in output resistance

Answer: D

Solution

: https://www.youtube.com/watch?v=9QAOS

h8OjSY

2014

Set 1 (15th February 2014 (Forenoon))

1.

i.

The gate source overlap

capacitance is approximately

a.

0.7 fF

b. 0.7 pF

c.

0.35 fF

d. 0.24 fF

Answer: A

ii. The source body capacitance

approximately

a.

2 fF

b. 7 fF

c.

2 pF

d. 7 pF

Answer: B

Solution

: https://www.youtube.com/watch?v=60X82

BxUfd8

gate oxide of an N channel enhancement type

MOSFET, it will lead to

a.

a decrease in the threshold voltage

b. channel length modulation

c.

an increase in substrate leakage

current

d. an increase in accumulation

capacitance

Answer: A

Solution

: https://www.youtube.com/watch?v=em0Vv

bA7po4

2013

1.

oxygen) as compared to Wet oxidation (using

stream or water vapor) produces..

a.

Superior quality oxide with a higher

growth rate

b. Inferior quality oxide with a higher

growth rate

c.

Inferior quality oxide with a lower

growth rate

d. Superior quality oxide with a lower

growth rate

Answer: D

Solution

: https://www.youtube.com/watch?v=EEcf8a

Solution

: https://www.youtube.com/watch?v=7om91p

j90XE

1995

1. Calculate the capacitance of a circular MOS

capacitor, of 0.5 mm dia and having a

accumulation. Assume the relative dielectric

constant of SiO2, r = 4 and o = 8.854 X 1014 F/cm. calculate the breakdown voltage of the

capacitor if the dielectric strength of SiO2 film

is 107 V/cm.

Answer: 80 Volts

Solution

: https://www.youtube.com/watch?v=tAtC_p

W9Bcw

Solution :

3.

1996

1.

used as a voltage variable resistor. Determine

the expression for the resistance and compute

its value for Vi. Neglect body effect.

MOSFET Data :

Threshold voltage, VT = 1 volt

Channel Length Modulation

parameter, = - 0.3 V-1

Transconductance parameter, KN(W/L) =

40 A/V2

CLM)

Solution

: https://www.youtube.com/watch?v=f5B96

mqdE7I

2.

threshold voltage of 1 volts and oxide thickness

of 400 Ao. [r (SiO2) = 3.9, o = 8.854 x 1014 F/cm, q = 1.6 x 10-19]. The region under the

gate is ion implanted for threshold voltage

tailoring. The doping and type of the implant

(assumed to be a sheet charge at the interface)

required to shift the threshold voltage to -1 volt

are

a.

b.

c.

d.

1.08 x 1012/cm3, N -type

5.4 x 1011/cm3, P -type

5.4 x 1011/cm3, N -type

Answer:

was fabricated using N+ poly silicon gate and

the threshold voltage was found to be 1 volt.

Now if the gate is changed to P+poly silicon,

other things remaining the same, the new

threshold voltage should be..volts.

a.

-0.1

b. 0

c.

1.0

d. 2.1

Answer: D

Solution

: https://www.youtube.com/watch?v=JWuL

Wh-pz1c

1.

1997

For a MOS capacitor fabricated on a P-type

semiconductor, strong inversion occurs when

a.

Surface potential is equal to Fermi

level

b. Surface potential is zero

c.

Surface potential is negative is

negative and equal to Fermi potential in

magnitude

d. Surface potential is positive and equal

to twice the Fermi potential

Answer: D

Solution

: https://www.youtube.com/watch?v=351Kp6NM-k

2.

dominated by charge time rather than

discharge time because

a.

The driver transistor has larger

threshold voltage than the load transistor

b. The driver transistor has larger

leakage currents compared to the load

transistor

c.

The load transistor has a smaller W/L

ratio compared to the driver transistor

d. None of the above

Answer: C

Solution

: https://www.youtube.com/watch?v=D2kfxs

y-ypk

3.

specifications of the circuit are :

VDD = 10 volts, = nCox(W/L) = 10-4 Amp/V2,

VT = 1 volt and IDS = 0.5 mA.

Evaluate VDS and RD. Neglect body effect.

pF.

Device data :

1.

Answer:

4.15 Volts, 11.68 k

Solution

: https://www.youtube.com/watch?v=Uc3Eu

Oto9Pk

Solution

: https://www.youtube.com/watch?v=0t8YIe

h7E_0

1998

2001

figure is 2 volts. For this circuit to work as an

inverter, Vi must take the values

a.

-5 volts and 0 volts

b. -5 volts and 5 volts

c.

0 volts and 3 volts

d. 3 volts and 5 volts

Answer: A

Solution

: https://www.youtube.com/watch?v=pHfKL4

yw4Ko

1999

1.

figure, the input Vi makes a transition from

VOL (= 0 volts) to VOH (= 5 volts). Determine

the High to Low propagation delay time (tpHL)

1.

a.

Current controlled capacitor

b. Voltage controlled capacitor

c.

Current controlled inductor

d. Voltage controlled inductor

Answer: B

Solution

: https://www.youtube.com/watch?v=DYvtwv

byh8Q

2.

saturation decreases with increase in

a.

Gate voltage

b. Drain voltage

c.

Source voltage

d. Body voltage

Answer: B

Solution

: https://www.youtube.com/watch?v=yySAO

Iv7hiw

2002

1.

connection with the CMOS inverter in figure,

where both the MOSFETs are of enhancement

type and both have a threshold voltage of 2

volts.

a.

0.5 mA

b. 2.0 mA

c.

3.5 mA

d. 4.0 mA

Answer: D

Solutoin

: https://www.youtube.com/watch?v=jvXncir

hK9c

S2: T1 is always in saturation when

Vo = 0 volts.

Which of the following is correct.

a.

Only S1 is TRUE

b. Only S2 is TRUE

c.

Both are TRUE

d. Both are FALSE

Answer: A

Solution

: https://www.youtube.com/watch?v=lm9CG

4kv7NU

metallization and S is source/drain diffusion,

then the order in which they are carried out in

a standard n-well CMOS fabrication process is

a.

P-Q-R-S

b. Q-S-R-P

c.

R-P-S-Q

d. S-R-Q-P

Answer: B

Solutoin

: https://www.youtube.com/watch?v=dS__K

GppUig

2004

1.

characteristic of

2003

1.

is connected at a higher potential than that of

the bulk (i.e. VSB > 0 volts), the threshold

voltage VT of the MOSFET will

a.

Remain unchanged

b. Decrease

c.

Change polarity

d. Increase

Answer: D

Solutoin

: https://www.youtube.com/watch?v=NkWe

ND6-BxI

MOSFET with threshold voltage of 400 mV.

The drain current observed is 1 mA. Neglecting

the channel length modulation effect, and

assuming that the MOSFET is operating at

saturation, the drain current for an applied

VGS of 1400 mV is

Answer: C

Solution

: https://www.youtube.com/watch?v=lPY4Xz

AWeSg

2.

S1: the threshold voltage (VT) of a MOS

capacitor decreases with increase in gate oxide

thickness

S2: the threshold voltage (VT) of a MOS

capacitor decreases with increase in substrate

doping concentration.

Which of the following is correct?

a.

b.

c.

Both S1 and S2 are TRUE

S1 is TRUE and S2 is FALSE

d.

Answer: D

Solution

: https://www.youtube.com/watch?v=jmKFR

Cr0xa0

to the gate so that VGS = VDS. The threshold

voltage (VT) of MOSFET is 1 volt. If the drain

current (ID) is 1 mA for VGS = 2 volts, then for

VGS = 3 volts, ID is

a.

2 mA

b. 3 mA

c.

9 mA

d. 4 mA

Answer: D

Solution

: https://www.youtube.com/watch?v=F1cZOG

LgZIA

2005

1.

is shown in figure, then the threshold voltage

is

Answer: C

Solution

: https://www.youtube.com/watch?v=6fIMwx

zffIo

is in the accumulation mode. The dominant

charge is due to the presence of

a.

Holes

b. Electrons

c.

Positively charged ions

d. Negatively charged ions

Answer: A

Solution

: https://www.youtube.com/watch?v=jlQ_ny0

L4C0

2006

1.

Answer: C

Solution

: https://www.youtube.com/watch?v=UYrsnuQIlU

2.

threshold voltage of 1 volt. The device

parameters K1 and K2 of T1 and T2 are

36 A/v2 and 9 A/v2 respectively. The output

voltage Vo is

following two points on its ID verses VGScurve

are

(i) VGS = 0 at ID = 12 mA and

(ii) VGS = -6 volts at ID = 0 mA

Which of the following Q-points will give the

highest Transconductance gain for small

signals?

a.

VGS = -6 volts

b. VGS = -3 volts

c.

VGS = 0 volts

d. VGS = 3 volts

Answer: D

Solution

: https://www.youtube.com/watch?v=Kxd4IZ

qv1vU

2007

1.

devices. Match each device in Group I with its

characteristic property in Group II.

respectively.

i.

The gate oxide thickness in the

MOS capacitor is

a.

50 nm

b. 143 nm

c.

350 nm

d. 1 m

Answer: A

ii.

The maximum depletion layer

width in silicon is

a.

0.143 m

b. 0.857 m

c.

1 m

d. 1.143 m

Answer: B

iii.

Consider the following

statements about the C V characteristics plot

:

S1: The MOS capacitor has an N type

substrate

S2: If the positive charges are introduced in

the oxide, the C V plot will shift to the left.

Then which one of the following is TRUE .

a. Both S1 and S2 are TRUE

b. S1 is TRUE and S2 is FALSE

c. S1 is FALSE and S2 is

TRUE

d. Both S1 and S2 are FASLE

Answer: C

Answer: C

Solution

: https://www.youtube.com/watch?v=iwERJ

Kn2hUU

2.

Transconductance parameters of the NMOS

and PMOS transistors are Kn =

Kp = nCox(Wn/Ln) = pCox(Wp/Lp) =

40A/V2 and their threshold voltages are VTn =

|VTp| = 1 volt, the current I is

Solution

: https://www.youtube.com/watch?v=IKyIj6

hVTL8

a.

0 Amp

b. 25 A

c.

45 A

d. 90 A

Answer: D

Solution

: https://www.youtube.com/watch?v=wtboLp

HXLOA

3. The figure shows the high frequency

capacitance voltage (C V) characteristics of

MOS capacitor having an area of 1x10-4 cm2.

Assume that the permittivity of silicon and

2008

1.

is inserted in a furnace at a temperature above

1000oC for further oxidation in dry oxygen.

The oxidation rate

a.

Is independent of current oxide

thickness and temperature

b. Is independent of current oxide

thickness but depends on temperature

c. Slows down as the oxide grows

d. Is zero as the existing oxide prevents

further oxidation

Answer: A

Solution

: https://www.youtube.com/watch?v=6yl7336

P2kA

2.

is given by ID = K(VGS-VT)2, where K is a

constant. The magnitude of the

Transconductance gm is

Answer: B

Solution

: https://www.youtube.com/watch?v=pYDNlQ

anv2g

3.

transistors M1 and M2 are identical NMOS

transistors. Assume that M2 is in saturation

and the output is unloaded. The IX is related to

Ibias as

Answer: B

Solution

: https://www.youtube.com/watch?v=CBXqcv

lx97A

4.

dependence of gm on VG?

NMOS transistor operating in the linear region

is plotted against the gate voltage VG at

constant drain voltage VD. Which of the

Answer: A

Solution

: https://www.youtube.com/watch?v=KE_ML

vt-M-4

are connected as shown below. Vbias is chosen

so that both transistors are in saturation. The

equivalent gm of the pair is defined to be dIout /

dVi at constant Vout, is

a.

The sum of individual gms of the

transistors

b. The product of individual gms of the

transistors

c.

Nearly equal to the gm of M1

d. Nearly equal to gm1/gm2 of M2

Answer: C

Solution

: https://www.youtube.com/watch?v=oySwK

D3Vtjg

MOSFET?

a.

Both are in saturation region

b. Both are in triode region

c.

NMOS is in triode region

and PMOS is in saturation region

d. NMOS is in saturation region

and PMOS is in triode region

Answer: D

ii.

Estimate the output voltage,

Vo for VG = 1.5 volts. (Hint: use the appropriate

current voltage equation for each MOSFET,

based on the answer to above question)

2009

1.

CMOS in reference to logic families are

a. Triple Transistor Logic and Chip Metal

Oxide semiconductor

b. Tristate Transistor Logic and Chip Metal

Oxide semiconductor

c. Transistor Transistor Logic and

Complementary Metal Oxide semiconductor

d. Tristate Transistor Logic and

Complementary Metal Oxide semiconductor

Answer: C

Solution

: https://www.youtube.com/watch?v=v0BYB0NkMI

2.

the internal conditions in an N channel

MOSFET operating in the active region.

S1: the inversion charge decreases from source

to drain

S2: the channel potential increases from

source to drain

Which of the following is correct?

a.

Both are TRUE

b. Both are FALSE

c.

Both are TRUE, but S2 is not a reason

for S1

d. Both are TRUE, and S2 is a reason for

S1.

Answer: D

Solution

: https://www.youtube.com/watch?v=qbq2JX

NCe_Q

3.

Linked Questions:

Consider the CMOS circuit shown, where the

gate voltage VG of the N channel MOSFET is

increased from zero, while the gate voltage of

the P channel MOSFET is kept constant at 3

volts. Assume that, for both transistors, the

magnitude of the threshold voltage is 1 volts

and the product of the transconductance

parameter and the (W/L) ratio i.e. the quantity

cox(W/L) is 1 mA/V2.

Answer: C

Solution

: https://www.youtube.com/watch?v=_BU3w

B8FoBA

2010

1.

mobility of electrons in the inversion layer of a

silicon N channel MOSFET is (in cm2/volt-sec)

a.

450

b. 1350

c.

1800

d. 3600

Answer: B

Solution: https://www.youtube.com/watch?v

=bXxmszDCh1U

2.

preferably grown using

a.

Wet oxidation

b. Dry oxidation

c.

Epitaxial deposition

d. Ion implantation

Answer: B

Solution

: https://www.youtube.com/watch?v=7bi7sX

WZYEc

2011

1.

i. For small increase in VG beyond 1 volt,

which of the following gives the correct

transistors, ncox = 100 A/V2 and the

threshold voltage VT = 1 volt. The voltage VX at

the source of the upper transistor is

Answer: A

Solution

: https://www.youtube.com/watch?v=Geh8H

iqWIoU

a.

1 volt

b. 2 volts

c.

3 volts

d. 0.367 volts

Answer: C

Solution

: https://www.youtube.com/watch?v=4J00rS

wlU6U

3.

channel MOS transistor shown below, = 20

nm. The transistor is of width 1 m. The

depletion width formed at every PN junction is

10 nm. The relative permittivitys of Si and

SiO2 are 11.7 and 3.9 respectively and 0 = 8.9

X 10-12 F/m.

2012

1.

expression Y is

Answer: A

Solution

: https://www.youtube.com/watch?v=AOa8c

OFX7WA

2.

hole motilities are equal, and M1 and

M2transistors are equally sized. The device

M1 is in the linear region if

i.

The gate source overlap

capacitance is approximately

a.

0.7 fF

b. 0.7 pF

c.

0.35 fF

d. 0.24 fF

Answer: A

ii. The source body capacitance

approximately

a.

2 fF

b. 7 fF

c.

2 pF

d. 7 pF

Answer: B

Solution

: https://www.youtube.com/watch?v=60X82

BxUfd8

Solution

: https://www.youtube.com/watch?v=xzUDu

BbZUXM

2013

1.

2.

oxygen) as compared to Wet oxidation (using

stream or water vapor) produces..

a.

Superior quality oxide with a higher

growth rate

b. Inferior quality oxide with a higher

growth rate

c.

Inferior quality oxide with a lower

growth rate

d. Superior quality oxide with a lower

growth rate

Answer: D

Solution

: https://www.youtube.com/watch?v=EEcf8a

Hius8

In MOSFET operating in saturation region,

the channel length modulation effect causes

a.

An increase in gate source

capacitance

b. A decrease in Transconductance

c.

A decrease in unity gain bandwidth

product

d. A decrease in output resistance

Answer: D

Solution

: https://www.youtube.com/watch?v=9QAOS

h8OjSY

(Afternoon))

1.

well regions can be formed using

a.

low pressure chemical vapor

deposition

b. low energy sputtering

c.

low temperature dry oxidation

d. low energy ion implantation

Answer: D

Solution

: https://www.youtube.com/watch?v=NAHnsA124g

2.

the figure, the threshold voltage VTH is 0.8

volts. Neglect channel length modulation

effects. When the drain voltage VD = 1.6 volts,

the drain current ID was found to be 0.5 mA. If

VD is adjusted to be 2 volts by changing the

values of R and VDD, the new value of ID (in

mA) is

2014

Set 1 (15th February 2014 (Forenoon))

1.

2.

gate oxide of an N channel enhancement type

MOSFET, it will lead to

a.

a decrease in the threshold voltage

b. channel length modulation

c.

an increase in substrate leakage

current

d. an increase in accumulation

capacitance

Answer: A

Solution

: https://www.youtube.com/watch?v=em0Vv

bA7po4

biased in its linear region for use as a voltage

controlled resistor. Assume threshold voltage

VTH = -0.5 volts, VGS = 2.0 volts, VDS= 5 volts,

W/L = 100, Cox = 10-8 F/cm2 and n = 800

cm2/volt-sec. The value of the voltage

controlled resistor (in ) is ..

Answer: 500

a.

0.625

b. 0.75

c.

1.125

d. 1.5

Answer: C

Solution

: https://www.youtube.com/watch?v=wsv90

UUqYVY

3.

threshold voltage |Vt| = 2 volts and K =

0.5cox(W/L) = 0.1 mA/V2. The value of ID (in

mA) is

12 and 4 respectively. The peak electric field

(in V/m) in the oxide region is ..

Answer: 2.4

Solution

: https://www.youtube.com/watch?v=K4aRA

JxegSI

4.

assume W/L = 2, VDD = 2.0 volts, ncox =

100 A/V2 and VTH = 0.5 volts. The transistor

M1 switches from saturation region to linear

region when Vin (in volts) is ..

Answer: 0.9

Solution

: https://www.youtube.com/watch?v=abv9X

XV0jks

(Forenoon))

In MOSFET fabrication, the channel length is

defined during the process of

a.

Isolation oxide growth

b. Channel stop implantation

c.

Poly-silicon gate patterning

d. Lithography step leading to the

contact pads

Answer: C

Solution

: https://www.youtube.com/watch?v=QPQ5h

OdbGjE

2.

The slope of the ID vs. VGS curve of an N

channel MOSFET in linear region is 10-3 -1at

VDS = 0.1 volts. For the same device, neglecting

channel length modulation, the slope of

the ID vs. VGS curve (in A/V) under

saturation regime is approximately.

Answer: 0.07

Solution

: https://www.youtube.com/watch?v=rDjsCv

kSUtk

Answer: 1.5

Solution

: https://www.youtube.com/watch?v=AWde

mWJenw4

1.

3.

concentration of 1015 cm-3 in the substrate.

When a gate voltage is applied, a depletion

region of width 0.5 m is formed with a

surface (channel) potential of 0.2 volts. Given

that o = 8.854 x 10-14 F/cm and the relative

2015

1.

a.

b.

c.

d.

preferred to form the gate dielectric (SiO2)

of MOSFET?

Sputtering

Molecular Beam Epitaxy

Wet Oxidation

Dry Oxidation

Answer: D

Solution

:

https://www.youtube.com/watch?v

=aT-PUfpeyOY

2.

enhancement mode NMOS transistors

n.Cox(W/L) = 1 mA/V2, VTN = 1 volt.

4. For the NMOSFET in the circuit

shown, the threshold voltage is Vth greater

than zero. The source voltage VSS is varied

from 0 to VDD. Neglecting the channel

length modulation, the drain current ID as a

function of VSS is represented by

parameter is zero and body is shorted to

source. The minimum supply voltage

VDD (in volts) needed to ensure that

transistor M1 operates in saturation mode

of operation is ___________________

Answer: 3

Solution

:

https://www.youtube.com/watch?v=

nAvaaApnnao

3.

NMOS transistor biased in saturation

mode was measured to be 1 mA at a drain

to source voltage of 5 volts. When the

drain source voltage was increased to 6

volts, while keeping gate-source voltage

same, the drain current increased to 1.02

mA. Assume that drain to source

saturation voltages is much smaller than

the applied drain source voltage. The

channel length modulation parameter (in

V-1) is __________

Answer: 0.02

Solution

: https://www.youtube.com/watch?v=4

AebD_Jv5C8

Answer: A

Solution

: https://www.youtube.com/watch?v=qi

pvNgPQNDM

current of 1 mA for VDS = 0.5 volts. If the

channel length modulation coefficient is 0.05

V-1, the output resistance (in k) of the

MOSFET is ________

Answer: 20

Solution

: https://www.youtube.com/watch?v=uFm

H59NNz6s

thickness of 10 nm. The maximum depletion

layer thickness is 100 nm. The permittivitys of

the semiconductor and the oxide layer are

s and ox respectively. Assuming s/ox = 3,

the ratio of the maximum capacitance to the

minimum capacitance of this MOS capacitor

is ____________

Answer: 4.33

Solution

:

https://www.youtube.com/watch?v=eIk6

sCXiKbY

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