2010 3rd International Congress on Image and Signal Processing (CISP2010)

A General Radar Surface Target Echo Simulator

Chengfa Xu, Jingliang Bai, Ronggang Wu, Yongbin Hong
dept. of Electronic Engineering of Beijing Institute of Technology. Beijing, P.R.China
bitfengyun@bit.edu.cn, baijinliang@gmail.com, wurgang@bit.edu.cn, maturehyb@bit.edu.cn
AbstractA general radar echo simulator system proposed in
this paper is to satisfy the various needs of the radar signal
processor testing. This simulator is based on the type of echo
data playback device, the surface target echo data is precalculated and stored in the device at first, then according to the
external timing PRI signal, echo data is read out to the device
processor, on which target information is modulated and
interpolation operation is made. After the DA Converter, the
radar echo is created. The system is simple and easy to
implement general.

Echo simulator's task is to create the precise amplitude and

phase relationship among the different channels, different
pulse repetition period, and inside the waveform. The
existence of those basic amplitude and phase relationship
makes general purpose simulator become possible. With the
development of the radar, the computational complexity and
computation increasingly become a bottleneck in the
development of simulator. Real-time processing using DSP
and FPGA during echo simulation has a long duration, and it is
hard to implement the general purpose [6].

Keywords-component; surface target; echo simulator; general

purpose; data playback

Based on data playback style, the echo simulator

decomposite the complex task into several simple pieces.
Making full use of rapid programming of matlab, the data
playback styled simulator assigns the complex calculate task of
the target location and target size modulated information to
matlab, and distributes some fixed algorism and large amount
of computation of convolution or filtering operation to the
FPGA or DSP. So that for different radar system, a simple
modification needs to be done to achieve general purpose [7].

I.

INTRODUCTION

Radar echo simulator simulated all the target modulation

information for radar signal processor, for example, echo
simulator needs to do the convolution of waveform and target
amplitude modulation to support testing pulse compression
function of signal processor, and also need Doppler
modulation information to test the moving target detecting
function of signal processor [1]. For array radar, azimuth and
elevation information of target need to be modulated by
simulator to support operations such as digital beam forming
on signal processor [2]. Its a fact that, the complexity and
computation of the echo simulator are no less than those of the
corresponding signal processor [3].
With the rapid development of the radar system, the
functions of signal processor became complex and diverse, so
the radar signal simulator for testing the signal processor also
become increasingly complex [4]. Several elements during the
radar echo simulation process are analyzed in this paper, and a
general radar echo simulation system base on the data
playback technology is proposed. The simulator system only
needs to do a little modification to support different kinds of
signal processor [5].
II.

SYSTEM THEORY OF SIMULATOR

A typical radar signal processor functions is shown below.

Multi
Echo
input

pluse compress

MTI/MTD

CFAR

pluse compress

MTI/MTD

CFAR

pluse compress

MTI/MTD

CFAR

pluse compress

MTI/MTD

CFAR

DBF

target
parameter
measure

A typical playback echo simulator system theory is shown

below.

I
target size
module
information
produce
Q
(matlab)

time & parameter

control
delay & data
interpolation

I
DA

radar echo data playback device

Figure 2. A typical playback echo simulator system theory

The simulator system consists of two parts, the target echo

data generation software and data playback system. The
software is used to produce echo data which contains
information of only target location and size, and has no
relationship with the waveform.
The data playback system includes data storage module,
data modulation module and digital to analog conversion
module. The data storage module is used to store the echo data
generated by the first part-software.the data modulation
module driven by timing of the radar, such as PRI, reads the
echo data out, and do some interpolation and delay operations
according to the control information, after then the data is turn
to the digital to analog converter. The conversion module
receives the digital data and output the radar echo analog
signal.

Figure 1. A typical radar signal processor process

978-1-4244-6516-3/10/$26.00 2010 IEEE

target size
module
information
store

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III.

CHOISE OF CORE PROCESSING UNIT

At present, the more commonly used digital signal

processors in radar system are FPGA and DSP. Previously, as
the coprocessor of the DSP FPGA is mainly used to
implement the pre- processing of the data, but now with the
development of the technology, the newly existing of the
FPGAs which have ultra-large-scale, high performance and
low power consumption make the FPGA be fully capable of
completing some signal processing tasks independently.
Compared to the DSPFPGAs greatest feature is that it has
lots of multipliers, so its ability of parallel processing is
powerful, but its drawback is also obvious, such as long
development cycle and difficult debugging. DSP which is
based on serial pipelined computation cannot competent in the
case of intensive computation, but it is easier to program and
debug than FPGA.

Data playback board is a high-speed real-time signal

processing board based on the standard 6U CPCI bus [9], it has
several independent signal processing units for data
acquisition, processing, playback, and its block diagram is
shown below.
output L

Left

Hardware Platform
A general surface target radar echo simulator base on the
CPCI architecture consists of two standard 6U board, data
playback board and interface board, a second interface board
and a host board. Data playback board and motherboard
compact connected through the CPCI bus, data replay board
and interface board connected through the second interface
board. Its mainly system architecture is shown below [8].
CPCI bus

main
control
computer

interface floor board

data
playback
module

IQ

clk

CPCI
box
interface
module

control time
signal signal

Figure 3. Hardware platform of simulator

Motherboard is equivalent to a generic PC, on which the

software used to generate the echo data, and download echo
data to the data playback board. Interface boards is used to
achieve the external interfaces, it mainly used to receive the
external timing signal and external control signal.

DAC-L

Right

DAC-R

ZBT

V5
V4-L

DDR
V4-R

DDR
EMIFA
DSP

J4
self_defined

J1
PCI

J3
Rapid_IO

J5
self_defined

Figure 4. The architecture of data playback board

A SURFACE TARGET RADAR ECHO SIMULATOR

A.

output R

CLOCK

Considering each other's advantage and disadvantage, it is

better to make use of the FPGA to implement some structured
and intensive algorithms such as interpolation, convolution and
noise generation to bring its parallel capability into play. For
tasks which need complex algorithms and lots of programming
work but less computation, it is advised to use DSP for the
debugging convenience and shorter development cycle.
IV.

Clock_in

From the figure 4, data playback board includes two fully

symmetrical pathways, each path way consists of a clock
generation and distribution circuits, signal processing nodes
Virtex4SX55 FPGA [10], high speed DAC AD9736. Two
branch sharing the data rate rose nodes V5 FPGA XC5VLX30.
Board is equipped with a C6455 DSP [11], which can add
up to 256MB DDRII-SDRAM. Two processing nodes V4
FPGA are both mounted on the DSP's EMIF interface. The
right side FPGA V4-R hung up 256MB of DDRII-SDRAM.,
while the left side FPGA V4-L hung 18MbitZBTRAM
memory.
In addition to the analog signal interface at front panel, the
external interfaces include J1 for the PCI interface, two V4FPGA can communicate through custom IO J4 and J5, DSP
has Rapid IO interface with external using J3.
B.

System Implementation
According to the theory of the radar echo simulator, and
combined with the above hardware platform, the simulator
system implementation structure is shown as figure 5.

1) Host computer software: Host computer software

used to generate the echo data, and complete the system
control. Task. To take full advantage of MATLAB in the
complex mathematical calculations, the echo data generated
using MATLAB, and use MATLAB compiler to provide the
executable file which can be run without MATLAB engine.
Host computer software provides the main graphic control
interface, the interface can be used to set parameters for echo
generation, start the echo data generation, download echo data
to the DSP plug-in DDRII-SDRAM, it also can control the
process of echo data playback at real-time, such as signal

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attenuation and noise amplitude adjustment, start or stop the

playback process.

radar signal
interface module

DDR
SDRAM

level translation

data
ransfer
interrupt

PRI
main control PC
data produce

DSP TMS320C6455interrupt
echo
data

data flow control

host interrupt
echo
data

data interrupt
system control

FPGA V4SX55
data mudulate

module change
interrupt

data storage
interpolation

echo
data

data playback module

ec ho

echo
EMIF
inter
c ommand -face

DAC

echo
data

store
module

command

noise module

PCI bus
output

The control module receives the radar timing signal,

mode switching signal and system control commands
created by the main control interface. It also translates
different kinds of signal into control information for
other FPGA programming modules, such as mode
switch interrupt signal.

ec ho

command

inter-p
olation

ec ho

amp ec ho
control
module

data

data data
send
module

noise

control
module

noise
module

mode change
interrupt

command
radar
time
signal

FPGA
XC5VLX30
data transfer
speed up

mode
changes
ignal

I
data

DAC

speed
up
module

Figure 5. The implementation structure of the simulator

2) DSP on the data playback board: DSP on data

playback board using three types of interrupt to schedule the
system process: host interrupt, data transfer interrupt, mode
switching interrupt.
Host interrupts is triggered by the main graphic control
interface, DSP complete the data pre-analysis, data precaching, real-time control of playback process at various
branches of the program. Data transfer interrupted is triggered
by FPGA Virtex4SX55 on the data playback board. In the
interrupt service routine of this interrupt, DSP transfer the echo
data to the FPGA- Virtex 4SX55 using EDMA at every current
pulse repetition. Mode switching interrupt is also triggered by
FPGA Virtex4SX55 on the data playback board, In this
interrupt service routine, DSP will switch the system work
mode, and playbacks an another mode data.
3) FPGA on the data playback board: Virtex4SX55
FPGA using ping-pong buffer to store two PRI echo data
received from the DSP, and then driven by the radar timing
signal, FPGA need to do the data interpolation, filtering,
amplitude control and noise added process, at last,
Virtex4SX55 sends data to speed-up FPGA-V5 chip. In
addition, the data transfer interrupt and mode switching
interrupt is also generated by Virtex4SX55 FPGA.

Figure 6. The implementation structure of FPGA

To ensure the amplitude and phase accuracy of analog

signal, interpolation module, driven by timing of the
radar, read data from the data cache module, and do
the interpolation and filtering operation, it also
increases the data rate.

The amplitude adjustments module calculates the

current weighting coefficient according to the echo
signal attenuation set up by the main control interface
module, and then adjusts the signal amplitude using
the weighted coefficient.

The noise generated module generates Gaussian white

noise according to the main control interface module.
It use system generator tool to create the noise
generator IP core for programming.

The data transmission module sends the echo data to

the FPGA-V5 throught 14 pairs of differential data
lines. The data is sent in DDR mode under 300MHz
clock.

The acceleration module is implementation in V_5,

under 600MHz clock frequency, echo data was sent to
the high-speed DAC by two ways: I and Q.

Based on the general nature of modularization, FPGA

programming implementation structure design is shown as
figure 6.
Specific functions of each module are described below.

DSP interface module is used to communicate with the

DSP, it receivers the control commands, and echo data
from DSP.

The data cache module store the echo data within the
chip FIFO, and is responsible for generation of data
transfer interrupt signal.

V.

SUMMARY

The simulator mentioned in this paper adopts the general

design method, makes several improvements on the structure
of the implementation comparing with the traditional structure.
The first is that it is based on the data playback mode, so it can
make full use of the powerful mathematical calculations and
complex algorithms of matlab. Secondly, using low sampling
rate of echo data to reduce the heavy computation. Using
FPGA to interpolate data, and improve the data rate, which not
only saves the memory space to store the echo data, but also
ensure the amplitude and phase accuracy of the video output

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signal. Echo data generated by matlab software, so it is

portability and versatility.
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