Chapter 3

CHAPTER 3
MICROCOMPUTER
ORGANIZATION
M. Jimnez, R. Palomera, & I. Couvertier
INTRODUCTION TO EMBEDDED SYSTEMS:

Using Microcontrollers and the MSP430
M. Jimnez et al. 2014
Lecture
Slides
Series
INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430
OUTLINE
Base Microcomputer Structure

Microcontrollers Versus Microprocessors
Central Processing Unit
System Buses
Memory Organization
I/O Subsystem Organization
CPU Instruction Set
MSP430 Instructions and Addressing Modes
Introduction to Interrupts
Notes on Program Design
The TI MSP430 Microcontroller Family
Development Tools
2014 by M. Jimnez, R. Palomera, & I. Couvertier
Chapter 3: 2
3.1 BASE
MICROCOMPUTER
STRUCTURE
Base Structure
Architecture
Chapter 3: 3
BASE MICROCOMPUTER STRUCTURE

Central Processing Unit
System Memory
Program Memory
Data Memory
Input-Output Subsystem
System Buses
Address bus
Data bus
Control bus
Power & Support Logic

Fig. 3.1 General architecture of
a microcomputer system
Chapter 3: 4
MINIMAL HARDWARE
Central Processing Unit (CPU)
Fetches, decodes, and executes instructions from memory
System Memory
Program memory
Data memory
Input/Output Interface
Connect to the external world
Buses: Sets of lines grouped according to their

function
Address bus: Indicate address to be accessed
Data bus: carry data or instruction being transferred
Control bus: regulate the activity in address & data buses
Chapter 3: 5
3.2
MICROCONTROLLERS
VERSUS
MICROPROCESSORS
Microprocessor
Units
Microcontroller
Units
RISC Versus CISC
Architectures
Programmer and
Hardware Model
Chapter 3: 6
MICROPROCESSOR UNITS
Abbreviated MPUs
Contain a General Purpose CPU
ALU, CU, Registers, & BIU
Require External Components to form a basic system

Buses
Memory
I/O interfaces & devices
Additional Characteristics
Architecture optimized for accelerating data processing
Include elements to accelerate instruction execution
Chapter 3: 7
MICROCONTROLLER UNITS
Abbreviated MCUs
Contain a Microprocessor Core
Usually less complex than that of an MPU
Include memory and peripherals in a single chip

Denominated computer-on-a-chip
Most MCUs do not provide external buses
On-chip Memory
Includes both program and data memory
Typical Peripherals
Timers
I/O ports
Data converters
Chapter 3: 8
T YPICAL MICROCOMPUTER
Optional
Fig. 3.2 Structure of a

typical microcontroller
Chapter 3: 9
SOME MCU SERIES
Chapter 3: 10
RISC VS CISC
CISC (Complex Instruction Set Computer)
Variable length instructions
Large instruction set
Focuses in accomplishing as much as possible with each
instruction
Helps programmers tasks
Augments hardware complexity
RISC (Reduced Instruction Set Computer)

Fixed length instructions
Short (reduced) instruction set
Focuses on simple instructions
Makes programming harder
Simplifies the hardware structure
Chapter 3: 11
PROGRAMMERS AND HW MODEL (1/2)

General-purpose, High-level Programming
Do not require knowledge of the underlying hardware
Centered on compiler-level abstraction
Embedded Systems Programming

Need to consider both, hardware and software models
Requires awareness of underlying hardware infrastructure
Needs to use software programmers model
Might require some assembly-level programming

Mostly programmed in C-language
Allows mixed assembly- C-language programming
Other languages might be available
Chapter 3: 12
PROGRAMMERS AND HW MODEL (2/2)

Hardware Model
Knowledge of hardware characteristics is indispensable
Structure, protocols, timing, power, limitations
Supports the programmers model
Programmers Model Focus

Instruction set
Syntax
Addressing modes
Memory map
Transfers and execution time
Chapter 3: 13
Control Unit
3.3 CENTRAL
PROCESSING UNIT
Arithmetic Logic
Unit
Bus Interface Logic
Registers & Flags
Chapter 3: 14
CPU COMPONENTS
Hardware
Control unit (CU)
Arithmetic Logic Unit
(ALU)
Register set
Bus interface logic
(BIL)
Software
Instruction set
Addressing modes
Chapter 3: 15
CONTROL UNIT
Operation
Governs the CPU working
like a finite state machine
Cycles forever through
three states:
Fetch
Decode, and
Execute
The fetch-decode-execute
cycle is also known as the
instruction cycle or CPU
cycle
Fig. 3.4 States in control unit

operation: fetch, decode, and
execute
Chapter 3: 16
INSTRUCTION CYCLE
Fetch
The program counter (PC) provides the address of the instruction
to be fetched from memory
The instruction pointed by the PC is brought from memory into the
CPUs instruction register (IR)
Decode
The instruction meaning is deciphered
The decoded information is used to send signals to the
appropriate CPU components to execute the instruction
Execute
The CU commands the corresponding functional units to perform
the actions specified by the instruction
At the end of the execution phase, the PC has been incremented
to point to the address of the next instruction in memory
Chapter 3: 17
ARITHMETIC LOGIC UNIT

Performs Supported Logic and Arithmetic Operations
Logic: AND, OR, NOT, XOR, SHIFT, ROTATE
Arithmetic: ADD, SUB, CMP
Datapath Width
Established by the ALU operand width
Also sets the width of the data bus and data registers
Example: A 16-bit CPU

16-bit ALU operands
16-bit Data bus
16-bit Registers
Chapter 3: 18
BUS INTERFACE LOGIC (BIL)

Coordinates the interaction between the internal
buses and the system buses, if externally accessible
Defines how the external address, data, and control
buses operate
Present even in MCUs with no external buses to
coordinate internal bus activity
Transparent to the programmer
Chapter 3: 19
REGISTERS
Provide temporary storage for:
Data & operands
Memory addresses
Control words
Fastest form of storage

Smallest Capacity
Volatile Contents
Contents lost when CPU is de-energized
Register Types
General Purpose
Special Purpose
Chapter 3: 20
GENERAL PURPOSE REGISTERS

Are not tied to specific functions
Are available for programmers general usage
Can hold data, variables, or addresses

Usage depend on addressing mode and programmers
designation
Number of registers depend on CPU architecture

Accumulator architectures have only a few
Some as little as two GP registers
RISC CPUs use a register file with dozens of registers
Chapter 3: 21
SPECIAL PURPOSE REGISTERS

Instruction Register (IR)
Holds the instruction being currently decoded and executed
Program Counter (PC)

Holds the address of the next instruction to be fetched from
memory
Stack Pointer (SP)

Holds the address of the current top-of-stack (TOS)
Status Register (SR)

Holds the current CPU status
Status is indicated by a set of flags
A Flag: an individual bit indicating some condition
Chapter 3: 22
COMMON STATUS FLAGS

Zero Flag (ZF)
Set when the result of an ALU operation is zero, and cleared
otherwise
Carry Flag (CF)

Set when an ALU arithmetic operation produces a carry
Negative or sign flag (NF)

Set if the result of an ALU operation is negative and cleared
otherwise
Overflow Flag (VF)

This flag signals overflow in ALU addition or subtraction
operations with signed numbers
Interrupt Flag (IF)

Also called the Global Interrupt Enable (GIE)
Is not associated to the ALU status
Indicates whether or not the CPU would accept interrupts
Chapter 3: 23
MSP430 STATUS REGISTER
Chapter 3: 24
UNDERSTANDING FLAG OPERATIONS
Chapter 3: 25
FLAGS AFTER A -B COMPARISON
Chapter 3: 26
MSP430 REGISTER STRUCTURE (1/2)

Based on a 16-bit RISC architecture
CPUX: Extends base architecture to 20-bit wide
Register Structure
Organized as a 16, 16-bit register file (R0 R15)
Special Purpose Registers

Program Counter (PC): named R0 or PC
Stack Pointer (SP): named R1 or SP
Status Register (SR): named R2 or SR
Has a dual function as (SR) and as Constant Generator 1 (CG1)
Constant Generator 2, named CG2 or R3
PC & SP always point to even addresses

Their lsb is always 0
Chapter 3: 27
MSP430 REGISTER STRUCTURE (2/2)

Status Flags
Carry (C), Zero (Z), Sign or Negative (N), overflow (V), and
global interrupt enable (GIE)
Other flags in the PS
CPUOFF, OSCOFF, SCG1 and SCG0
Are used to configure the CPU, oscillator and low power modes
MSP430 ALU
16-bit wide (20-bit in CPUX)
Arithmetic ADD, SUB, CMP operations
BCD arithmetic
Bitwise logic operations
Does not provide for multiplication, division, or FP
Some MSP430 feature a hardware multiplier peripheral device
Chapter 3: 28
Data Bus
3.4 SYSTEM BUSES
Address Bus
Control Bus
Chapter 3: 29
SYSTEM BUSES
Data bus
Set of lines carrying data and instructions
Data bus lines are bidirectional to allow for reads & writes
READ: A transfer into a CPU register from memory or I/O
WRITE: A transfer or from a CPU register to memory or I/O
Address bus
Set of lines transporting the address information which
uniquely identifies a data cell in memory or peripheral
device
Control bus
Set of lines carrying the signals that regulate the system
activity
Chapter 3: 30
Data Address: Little

and Big Endian
Conventions
Program and Data
Memory
3.5 MEMORY
ORGANIZATION
Von Neumann and

Harvard
Architectures
Memory and CPU
Data Exchange: An
Example
Memory Map
MSP430 Memory
Organization
Chapter 3: 31
MEMORY STRUCTURE
The memory subsystem is organized as an array of cells or locations
Each memory location is identified by an address
The contents of a memory cell is a word
A memory word may store instructions or data
Fig. 3.6 Memory structure

Chapter 3: 32
MEMORY T YPES
Chapter 3: 33
16-BIT MEMORY ARRAY
Chapter 3: 34
ENDIANNESS
Big Endian:
Data is stored with the most significant byte in the lowest address
and the least significant byte in the highest address
Little Endian
Data is stored the the least significant byte in the lowest address
and the most significant byte in the highest address
Chapter 3: 35
MCU ARCHITECTURES
Von Neumann
A single set of buses for accessing both programs and data
and a single address space
Harvard
Uses separate buses for accessing programs and data and
has separate address spaces
Chapter 3: 36
CONCEPTUAL MEMORY CONNECTION
CS
Chapter 3: 37
TWO BANK DECODER (EXAMPLE 3.6)
Chapter 3: 38
MEMORY MAP EXAMPLE
(a)
(b)
Fig. 3.13 Example memory map for a microcomputer with a 16bit address bus. a Global memory map, b Partial memory map.
Chapter 3: 39
16 AND 20-BIT MSP430 MEMORY MAPS
Chapter 3: 40
Anatomy of an I/O
Interface
3.6 I/O SUBSYSTEM

ORGANIZATION
Parallel Versus
Serial I/O
Interfaces
I/O and CPU
Interaction
Timing Diagrams
MSP430 I/O
Subsystem and
Peripherals
Chapter 3: 41
I/O SUBSYSTEM
All the components other than the CPU & memory
connected to the system buses
Timers & Watchdog timers
Communication interfaces
Analog to Digital Converter (ADC)
Digital to Analog Converter (DAC)
Development peripherals
Its organization resembles that of memory

Memory mapped I/O
Address space inside the memory space, uses same instructions
used to access memory
I/O mapped I/O

Separate address space, instructions, and signals for I/O (rarely
used in modern processors)
Chapter 3: 42
CONCEPTUAL I/O INTERFACE

Serves as a bridge between a device & the buses
Has one or more registers each with their own addresses
Data, control, and status registers
Accessed like memory (read/write)
Fig. 3.15 Structure of an input/output (I/O) interface

Chapter 3: 43
I/O INTERFACE ANATOMY

Includes lines to connect to the system buses, I/O device
connection lines, and a set of internal registers
Internal register types
Control: to configure the operation of the device & interface
Status: to allow inquiries about the device & interface status
Data: for exchanging data with the device
Fig. 3.16 Anatomy of an input/output (I/O) interface

Chapter 3: 44
EXAMPLE 3.7 INTERFACE EXAMPLE
Chapter 3: 45
EXAMPLE 3.7 INTERFACE REGISTERS
Chapter 3: 46
I/O PIN HARDWARE CONFIGURATION
Pin
Pin
Chapter 3: 47
TIMING DIAGRAMS
The CPU and hardware components communicate
exchanging signals sent over the system buses
Signal exchanges require protocols
Indicate the times required for the steps in the process
Settling of states
Delays
Order of signals activation, etc.
Timing diagrams are the most common way to define

a signal protocol
Chapter 3: 48
TIMING DIAGRAM CONVENTIONS

Single Line and Bus Timings
High Z refers to a high impedance state
Fig. 3.20 : Definitions of timing conventions. (a) Single signal timing, (b) Bus timing
MPU Read and Write Timing Diagrams
Fig. 3.21 Example of simplified write &read timing diagrams. (a) Read timing, (b) Write timing
Chapter 3: 49
MSP430 I/O SUBSYSTEM

Memory mapped from address 0x0000h to 0x01FFh
Information stored in special function registers (SFR)
Located from 0x0000 to 0x000F
Control the operation of MSP430 peripherals
Available Peripherals (Specific list is device dependent)

General Purpose I/O Pins
Arranged as multiple 8-bit I/O ports
16-bit Timers
General purpose and Watchdog
Communication Support
USART, SPI, I2C
Data Converters
ADCs and DACs
System Support
POR and brownout reset circuitry
Clock generators and supply voltage supervisors
Chapter 3: 50
MSPG2231 & X1XX PINOUT
Chapter 3: 51
Register Transfer
Notation
Machine Language
and Assembly
Instructions
3.7 CPU INSTRUCTION

SET
Types of
Instructions
The Stack and the
Stack Pointer
Addressing Modes
Orthogonal CPUs
Chapter 3: 52
REGISTER TRANSFER NOTATION (RTN)

RTN: a notation for MCU operations
Independent from specific MCU architecture
Takes in consideration the system features
Source/destination Notation
destination source
Programmers Model Operands

Constants are expressed by their value
Ex.: 24, 0xF230, MyConstant
Registers are referred by their names

Ex.: Rn (Ex.: R5, R3, R7)
Memory and I/O locations are referred as (address) or (Rn)

Ex.: (0x345A) = the datum a memory address 345Ah
(R5) = the datum a memory address given by R5
Chapter 3: 53
EXAMPLE OF RTN OPERATIONS
Chapter 3: 54
MACHINE VS. ASSEMBLY LANGUAGE

Machine Language Instructions
Sequence of zeros and ones understood by the CPU
Hard to read by humans
Consists of several fields
Opcode, source and destination fields, and an optional datum
Assembly Language Instructions

A human understandable notation for machine language
One assembly instruction per machine language instruction
Consists of several fields
A mnemonic followed by zero or more operands
Assembly Process
Converts an assembly language program into a machine
language program
Chapter 3: 55
MACHINE CODE AND ASSEMBLY PROCESS (1/2)
Chapter 3: 56
MACHINE CODE AND ASSEMBLY PROCESS (2/2)
Assembly encoding for MSP430 machine instructions

Chapter 3: 57
INSTRUCTION T YPES
Data Transfer Instructions
Copy data from a source to a destination
Arithmetic-logic Instructions
Perform arithmetic and/or logic operations on operands
Program Control Instructions

Modify the default flow of execution in a program
Chapter 3: 58
DATA TRANSFER INSTRUCTIONS

Copy data from a source to a destination
destination source
Do not affect flags
Included Instructions:
Data transfer: MOVE
Data exchange: SWAP
Stack manipulation: PUSH & POP
Treat I/O locations like memory

Memory-mapped I/O
Examples:
MOV R8,R3 ; Copies the contents of R8 into R3
MOV (0xF348),R5 ; Copies into R5 the word at address F348h
PUSH R7 ; Copies onto the top of the stack the contents of R7
Chapter 3: 59
ARITHMETIC-LOGIC INSTRUCTIONS
Perform arithmetic and/or logic operations on data
destination (DestinationOperand SourceOperand)
Flags affected according to operation result

Arithmetic: ADD, SUB
Compare and test: CMP, TEST
Bitwise logic: AND, OR, XOR, NOT
Bit Displacement: SHIFT, ROTATE
Examples:
ADD R7,R5 ; Places on R5 the sum of the contents of R5 and R7
AND #05AD,R6 ; Places on R6 the bitwise result of anding the
contents of R6 and the value 05ADh
ROTL R3 ; Rotates the contents of register R3 one position to the
left
Chapter 3: 60
WORKING WITH BITS

Bitwise operations work directly on bits
Chapter 3: 61
PROGRAM CONTROL INSTRUCTIONS

Modify the default flow of execution in a program
PC NewAddress
Do not affect flags

Unconditional Jump: Always change the PC
Conditional Jump: Change the PC if condition is true
Subroutine Calls and Returns: Transfer control from main to
subroutines, returning to the calling point
Examples:
JMP #F345h ; Loads PC with the address 0xF345 so program execution
continues there
JZ #F345 ; Loads PC with the address 0xF345 if the Zero Flag is set
CALL Sub1 ; Saves PC onto the stack and loads PC with address Sub1.
When special instruction RET is executed, the PC is
restored from the stack
Chapter 3: 62
CONDITIONAL JUMPS
Conditional Jump Instructions enable decision
making in programs
Chapter 3: 63
FLOWCHARTS AND JUMP INSTRUCTIONS

Correspondence between some flowcharts constructs
and register transfer notation (RTN)
Chapter 3: 64
THE STACK
A portion of memory used to temporarily store data
Access through special register Stack Pointer (SP)
Last-in-First-out (LIFO) operation
Stack contents is volatile
Stack Operations
PUSH: Places data on top of the stack
POP (or pull) : Retrieves data from the top of the stack
Other instructions and events modifying the stack

Invoking and returning from a subroutine call
Responding and returning from an interrupt event
Chapter 3: 65
STACK OPERATIONS
Chapter 3: 66
STEPS IN PUSH AND POP OPERATIONS

Push
Update the stack pointer to point to the new TOS
Copy the operand to the new TOS
Pop or Pull
Copy the contents in the actual TOS to the destination
Update the stack pointer to point to the new TOS
Example: PUSH R9 and POP R9 (assume SP = 027Eh)
Chapter 3: 67
SAMPLE STACK OPERATIONS (1/3)

Store Before Update
Update Before Store
Chapter 3: 68
STACK OPERATIONS (2/3)
Chapter 3: 69
STACK OPERATIONS (3/3)

1.
Function Call
Saves PC onto stack
2.
Function Execution
PC loaded with function address
3.
Executing the Return

Restore the PC from the stack
4.
Back at Main Program

Continue at instruction after CALL
Chapter 3: 70
ADDRESSING MODES
Addressing modes tell the CPU how to obtain the
data needed to execute an instruction
The data may be
Explicitly supplied with the instruction
Stored in a CPU register
Stored at a memory location
Stored in an I/O device register
Implicit Addressing Mode

Operand is implicit to the instruction
Chapter 3: 71
BASIC ADDRESSING MODES

Immediate Addressing Mode
Syntax: #Number
Register Addressing Mode

Syntax: Rn
Absolute or Direct Addressing Mode

Syntax: Number
Indirect Addressing Mode

Syntax: @Rn
Indexed Addressing Mode

Syntax: X(Rn)
Chapter 3: 72
SAMPLE ADDRESSING MODES
Chapter 3: 73
ILLUSTRATING ADDRESSING MODES (1/2)
Fig. 3.33 Illustrating

addressing modes.
(a) Intial condition,
(b) mov R8, R6,
(c) mov @R8, R6,
(d) mov R10, 56h(R6),
(e) mov #0x025A, R10,
(f) mov 0x025A, R10
Chapter 3: 74
ILLUSTRATING ADDRESSING MODES (2/2)
Fig. 3.34 Illustrating addressing

modes with arithmetic-logic
instructions
Chapter 3: 75
ORTHOGONAL CPU
A CPU is said to be orthogonal if all its registers and
addressing modes can be used as operands
Either source or destination
Excludes using the immediate addressing mode as
destination
Enables writing compact code

No need for intermediate storage instructions
Require careful treatment

Special purpose registers can be adversely affected
Chapter 3: 76
3.8 MSP430
INSTRUCTIONS AND
ADDRESSING MODES
Instruction Set
Summary
Chapter 3: 77
MSP430 INSTRUCTIONS SET SUMMARY

Twenty seven (27) core machine language
instructions
One (1) to three (3) words long instructions
Twenty four (24) additional emulated instructions
Seven (7) addressing modes

Not fully orthogonal
Chapter 3: 78
3.9 INTRODUCTION TO
INTERRUPTS
Device Services:
Polling Versus
Interrupts
Interrupt Servicing
Events
What is Reset?
Chapter 3: 79
POLLING VS. INTERRUPT SERVICING

Service by Polling
The CPU periodically interrogates a device status to learn if it
need service
Usually done in a loop
When need is identified, CPU executes service instructions
Service by Interrupt
The device notifies the CPU when service is needed
Interrupt request
Meanwhile, the CPU can be used for other tasks or sent to sleep
mode
When service request arrives, CPU interrupts what it is doing to
execute the service instructions (Interrupt Service Routine ISR)
Upon completion (IRET) control is transferred back to interrupted
task
Chapter 3: 80
INTERRUPT T YPES
Maskable Interrupt
Can be blocked by clearing the GIE flag
Most common type of interrupt
GIE cleared by RESET
GIE automatically cleared when entering an ISR
Non-maskable Interrupt (NMI)

Cannot be blocked by clearing GIE
Reserved for system critical events
Requires an ISR to serve the critical event
Chapter 3: 81
INTERRUPT SERVICING EVENTS

Step 1: Finish the instruction being executed
Step 2: Save the current PC value and the status
register (SR), onto the stack
Step 3: Clear the global interrupt enable flag
Step 4: Load the program counter (PC) with the
address of the ISR to be executed
Step 5: Execute the corresponding ISR
A vector number is used to identify the corresponding ISR
Step 6: Restore the program counter and status that

were saved onto the stack in Step 2
Control transferred back to interrupted task
Chapter 3: 82
INTERRUPT SUPPORT INFRASTRUCTURE

A means for saving the program counter and status
register
Provided through a properly allocated stack
An interrupt service routine designed to render the

requested service
Provided by a properly designed ISR
A means for locating the ISR corresponding to a

particular request
Provided by a properly initialized vector table
An enabled interrupts structure

Achieved by setting the GIE and the peripheral device IF
Chapter 3: 83
WHAT IS A RESET?
An asynchronous signal causing the CPU to start from
a predefined known state
Power-on Reset
Generated when power is applied for the first time
Loads PC with Reset Address
Clears Status register, including GIE
Other Reset Triggers

Events that might compromise the system integrity
External hardware events (like a reset pushbutton depress)
Expiration of watchdog timer
Assertion of the CPU reset pin
Chapter 3: 84
3.10 NOTES ON
PROGRAM DESIGN
Chapter 3: 85
PROGRAMMING RECOMMENDATIONS
Program Planning & Design
Plan your program before start coding
Document Your Design

Begin documenting since the planning phase
Partition Your Design

Design modular programs
Code in the Selected Language

Be aware of syntax rules and language features
Integrate, Test, & Debug

Join modules one adding one at a time
Test under different conditions
Correct bugs as they appear
Chapter 3: 86
EMBEDDED SW RECOMMENDATIONS (1/2)

Write the shortest possible program
Short programs are easier to understand and modify
Evaluate shortcuts before implementing them

Avoid programming with tricks
Write programs easy to understand

Document well to later understand the code
Write programs easy to modify

Makes it easier maintaining the code
Document your program as you work on it

Will make code easy to modify and reusable
Never leave the documentation for last
Chapter 3: 87
EMBEDDED SW RECOMMENDATIONS (2/2)

Create your own catalog of functions for common tasks
Increases code reusability and productivity
Program for lowest power consumption

Activate the low-power modes in your hardware
Be self conscious about code efficiency
Know your hardware system

Embedded software needs to match your hardware
Avoid using unimplemented bits of memory or registers

Reduces the risk of early code obsolescence
Whenever possible, use a single resource for a single

purpose
Minimizes chances of bugs due to confusion in usage
Chapter 3: 88
3.11 THE TI MSP430

MICROCONTROLLER
FAMILY
General Features
Naming
Conventions
Chapter 3: 89
THE MSP430 MCU FAMILY

MSP430 Genealogy
Main Features
Standard 16-bit Architecture
1992
x3xx
2002
x1xx
1996
x4xx
Powerful Processing
2005
x2xx
Extensive Set of Memorymapped Peripherals
2008
x5xx
2009
x6xx
Extended to 20 bits in CPUX
Ultra Low-power Operation
0.1uA @ 1MHz @ 3.0V

Wake-up time of 6uS
Seven addressing modes
27 core instructions
GPIO, Timers, ADC/DAC, DMA, etc
Versatile Device Options

On-chip RAM & FLASH
JTAG Loader/Debugger
Chapter 3: 90
Internet Sites
3.12 DEVELOPMENT
TOOLS
Programming and
Debugging Tools
Development Tools
Other Resources
Chapter 3: 91
MSP430 TOOLS
Chapter 3: 92
END OF CHAPTER 3 SLIDES
Chapter 3: 93

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CHAPTER 3

INTRODUCTION TO EMBEDDED SYSTEMS:

M. Jimnez et al. 2014

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

Base Microcomputer Structure

2014 by M. Jimnez, R. Palomera, & I. Couvertier

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

2014 by M. Jimnez, R. Palomera, & I. Couvertier

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

BASE MICROCOMPUTER STRUCTURE

Power & Support Logic

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

Buses: Sets of lines grouped according to their

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

2014 by M. Jimnez, R. Palomera, & I. Couvertier

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

Require External Components to form a basic system

2014 by M. Jimnez, R. Palomera, & I. Couvertier

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

Include memory and peripherals in a single chip

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

Fig. 3.2 Structure of a

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

SOME MCU SERIES

2014 by M. Jimnez, R. Palomera, & I. Couvertier

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

RISC (Reduced Instruction Set Computer)

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

PROGRAMMERS AND HW MODEL (1/2)

Embedded Systems Programming

Might require some assembly-level programming

2014 by M. Jimnez, R. Palomera, & I. Couvertier

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

PROGRAMMERS AND HW MODEL (2/2)

Supports the programmers model

Programmers Model Focus

2014 by M. Jimnez, R. Palomera, & I. Couvertier

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

2014 by M. Jimnez, R. Palomera, & I. Couvertier

Registers & Flags

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

2014 by M. Jimnez, R. Palomera, & I. Couvertier

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

2014 by M. Jimnez, R. Palomera, & I. Couvertier

Fig. 3.4 States in control unit

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

ARITHMETIC LOGIC UNIT

Example: A 16-bit CPU

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

BUS INTERFACE LOGIC (BIL)

2014 by M. Jimnez, R. Palomera, & I. Couvertier

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

Fastest form of storage

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

GENERAL PURPOSE REGISTERS

Can hold data, variables, or addresses

Number of registers depend on CPU architecture

RISC CPUs use a register file with dozens of registers

2014 by M. Jimnez, R. Palomera, & I. Couvertier

INTRODUCTION TO EMBEDDED SYSTEMS: Using Microcontrollers and the MSP430

SPECIAL PURPOSE REGISTERS

Program Counter (PC)

Stack Pointer (SP)