Can we prepare for the IR Drop problem before silicon?

Yes - run a rail analysis tool - then update your power mesh + decap fillers until your target
IR drop is met.

: Can we prepare for the IR Drop problem before silicon?

Originally Posted by u24c02

What if I have congestion problem, then power mesh and decap fillers affect to congestion
problem. doesn't it ?
It sure does, that is why you have to try to address GLOBAL IR drop as soon as possible by
proper sizing/frequency of the power rings and stripes. Some local IR drop issues can be
fixed later with decaps.
1.

2. Re: why is post silicon

testing quicker than pre
silicon?
Pre Silicon testing process steps :
Scan Insertion thn Pattern Generation thn Pattern Validation
Post silicon:
ONly pattern validation which are generated by ATPG.
3.

20th August 2012, 12:38#3

kothandapani

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Re: why is post silicon testing quicker than pre silicon?

Hi, Thanks.
This answer seems to be the differences in the process steps.
Actually the question is , say we have scan vectros ready say 500 vectors, If I do presilicon
simulation it took say 28hrs But the same vectors run it on the ATE it's done fast.
Thats where the speed difference in reality Please describe on this context.
o

20th August 2012, 12:38

4.

21st August 2012, 14:16#4

maulin sheth

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Re: why is post silicon testing quicker than pre silicon?

Hello All,
As per my opinion,For pre-silicon, after PD, we have post layout netlist,So simulator has to
find every modules in library path,so for searching of the particular library cell in library
path,It takes more time.
Post silicon, we already have a circuitry,so only pattern pass through the exact path.They
dont need to search module/cell in library path.
Pl correct me if I am Wrong.
5.

21st August 2012, 14:26#5

dftrtl

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Re: why is post silicon testing quicker than pre silicon?

There is no comparision between these two. One is simulation based and other one is
hardware based.
6.

21st August 2012, 14:34#6

maulin sheth

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Re: why is post silicon testing quicker than pre silicon?

Yea that is true,Because after comparision nothing to achieve.
But we can compare it only in terms of timing perspective.Because if we want to reduce
total test time thn we have to think about both the time.
o

21st August 2012, 14:34

7.

21st August 2012, 14:44#7

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Re: why is post silicon testing quicker than pre silicon?

Still could not understand
8.

21st August 2012, 16:42#8

maulin sheth

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Re: why is post silicon testing quicker than pre silicon?

If we want to reduce the total test time, thn we have to think both the possibilities means 1)
Pre silicon testing 2) Post silicon testing.

I think this is the one thing to compare both the timing.

Right???
9.

21st August 2012, 17:02#9

dftrtl

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Re: why is post silicon testing quicker than pre silicon?

If you are talking about these two things independently then it make sense.
calculate time independently. post heading is misleading.
10. 27th August 2012, 09:20#10
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Re: why is post silicon testing quicker than pre silicon?

Hi Friends,
Still I did'nt get ansfer for my question. it's all the answers are the dfferences in the setup
and step we do for these pre and post silicon simulations.
o

27th August 2012, 09:20

11. 27th August 2012, 09:38#11

yadavvlsi

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Re: why is post silicon testing quicker than pre silicon?

Before fabrication (per-silicon), we do simulations. We don't have actual hardware available.
We have circuit in form of netlist which have gates and their connectivity information.
Simulation process (applying vector, propagating it through circuit and getting final output)
is fully handled by software. This required a lot of computation and hence require a lot of
simulation time. In case of post-silicon testing you have just apply vectors at inputs and
check the output. Hence time required is very less.
12. 27th August 2012, 11:53#12
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Re: why is post silicon testing quicker than pre silicon?

Hi,
I agree with all these copilation and elaboratin happens in the simulations side but once the
snapshot is ready the simulator starts feeding the vectors to the DUT the same way the ATE
also feeds the vectors to DUT. Here on ATE just applying vectors and checking for the
expected results. Still we see the differences in the time on ATE it is too fast but on the
simulation environment it is taking more hrs to complete. You think its bcoz of clock running
at speed in post silicon thats where the post silicon testing is quicker than the simulation
environment.
13. 27th August 2012, 17:47#13
maulin sheth

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Re: why is post silicon testing quicker than pre silicon?

Originally Posted by kothandapani

Hi,
I agree with all these copilation and elaboratin happens in the simulations side but once the
snapshot is ready the simulator starts feeding the vectors to the DUT the same way the ATE
also feeds the vectors to DUT. Here on ATE just applying vectors and checking for the
expected results. Still we see the differences in the time on ATE it is too fast but on the
simulation environment it is taking more hrs to complete. You think its bcoz of clock running
at speed in post silicon thats where the post silicon testing is quicker than the simulation
environment.
See when we are doing simulation.at that time, in any path for applying patterns,the
module/cell comes into path,so simulator have to find that particular cell from huge cell
library..so its take more time.

1. Re: pre-silicon verification

Silicon is costly
You need to test each and every possible condition before the chip can be
taped out and fabricated. Else it will hurt the company big time
23rd November 2011, 08:14

2.

17th August 2012, 18:01#3

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Re: pre-silicon verification

If you do not do presilicon verification How do you know you have functional circuit what
you have coded for.
o

17th August 2012, 18:01

3.

21st August 2012, 17:39#4

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Re: pre-silicon verification

Because tooling/setup fee for ASIC fabrication is something like $500k for CMOS process in
best case and probably like 1.5x that for BiCMOS o.O

1. setup/hold timing check during library silicon

verification
question to experts: does all known providers of standard cell libraries during a silicon
verification check setup/hold timing of flip-flops, and does their test report incorporates
result of this check?
Another question: what is most reliable method to implement setup/hold timing check
during library silicon verification?
o

1. sta setup hold

Who can tell me how to report all the setup and hold timing information in sta?
((report_timing -input -delay_type max -max_paths 100)),Thanks .
o

9th April 2004, 05:52

2.

9th April 2004, 07:28#2

linuxluo

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setup hold sta

hi,
report_timing -min for hold report_timing -max for setup
o

9th April 2004, 07:28

3.

9th April 2004, 10:40#3

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sta setup
report_constraint -max_delay for setup
report_constranit -min_delay for hold
Best Regards!
9th April 2004, 10:40

4.

9th April 2004, 18:05#4

eekenneth

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worst = setup best hold

First of all, this is a tricky question.
I assume you want to get the worst corner for both setup and hold time in your design
so worst corner for setup time happens in slow corner and worst corner for hold time
happens in fast corner, so when you run the STA, you have to import DIFFERENT db
of standard cells, memory db into the STA script, otherwise, you will not get safe results
when you tape out
here are the commands
report_timing -delay max -net -path_type full_clock -max_paths 2000 >
timing_setup_ss.rpt
report_timing -delay min -net -path_type full_clock -max_paths 2000 >
timing_general_ss.rpt
it's good you report the violations always as well
report_constraint -verbose -all_violators > vio.rpt
1 members found this post helpful.

5.

11th April 2004, 20:00#5

realtek

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setup/hold time
If you use Synopsys PT(primetime) or Cadence Buildtgate
you can get more information then DC
or you can reference the eBook which I upload
: http://www.elektroda.pl/eboard/ftopic73639.html

11th April 2004, 20:00

6.

23rd March 2012, 17:51#6

ivlsi

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Re: setup/hold time

you have to import DIFFERENT db of standard cells, memory db into the STA script
So, how many times the tool should be ran for the setup and hold checks?
Should it be ran once for the Setup Checks and once for the Hold Checks? Could not it be
done in a single run?
Thank you!

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1. setup hold timing during post layout simulations

using ncsim
When doing post layout simulations, ncsim is given both sdf and library_model.v files. The
library_model.v file has all the models + timings for the cells in the libraray. The default is
1ns for both setup and hold. When doing simulations using ncsim, are sdf values taken into
acccount only and info in library_model.v discarded ? I need to find out how both the files
are used and where do the setup hold timing requirements for the Flops come from during

post layout simulations

Thanks
3rd August 2006, 14:37

2.

10th August 2006, 06:52#2

anant

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setup hold timing during post layout simulations using ncsim

all the timing related information is present in sdf file "Delays: module path, device,
interconnect, and port Timing checks: setup, hold, recovery, skew, width, and period." when
you do back annotation the timming information from sdf file is used.