Lithography

Photolithographic Process

Photomask Fabrication

Exposure Systems

Exposure Sources

Optical and Electron Microscopy

Optical Microscopy
Scanning Electron Microscopy
Transmission Electron
Microscopy

Advanced lithography (reference)

Process details (reference)

Lithography

A patterning process that transfers the designed pattern from the

mask or reticle to the photoresist on the wafer surface. These
patterns define the various regions in an IC, such as the implantation
regions, the contact windows, and bonding-pad areas. It takes about
40 % to 50 % of the total wafer-processing time.

Masks contain the patterns of windows which are transferred to the

surface of the silicon wafer

The patterns are first transferred from the mask to a light-sensitive

material called photoresist (PR), and
then, chemical or plasma etching is then used to transfer the
pattern from the photoresist to the barrier material.

Each mask step requires successful completion of numerous

processing steps, and therefore, the complexity of an IC process is
often measured by the number of photographic masks used during
fabrication.

The lithographic process includes mask fabrication, PR

processes, and etching.

Figure 2.1 Steps of the photolithographic process

Patterns are defined on a wafer

through the various steps of the
photolithographic process.
(a) Substrate covered with silicon
dioxide barrier layer;
(b) positive photoresist applied to
the surface of the wafer;
(c) mask aligned in close proximity
to the surface of the resist-covered
wafer;
(d) substrate following resist
exposure and development;
(e) substrate following etching of
the silicon dioxide layer;
(f) oxide barrier on wafer surface
after resist removal;
(g) view of substrate with silicon
dioxide pattern on the surface.

Photoresist (PR):
Photo-sensitive organic polymers that are spun onto wafers and
prebaked to produce a film 0.5~1 um

PHOTOMASK (or RETICLE) FABRICATION

A glass plate (transparent, white) with patterns (opaque, black)
Pattern is generated by selective etching of Cr thin layer (~70nm)
Cr layer prevent transfer of light, but the clear region is free to
light transfer
Light-field and dark-field masks
Reticle : unit mask pattern of usually magnified of the real

Reticle(10X)

pattern size (10X, 5X) for a stepper

Photomask : repeated pattern in real size for contact/proximity

Photomask

Light field

Dark field

Cr

2.5 EXPOSURE SYSTEMS

The performance of exposure system is usually determined by (1) Resolution: min. feature
dimension that can be transferred with high fidelity, (2)Registration: a measure of how accurately
patterns on successive masks can be aligned with respect to previously defined patterns on the
wafer, (3)Throughput: the # of wafers that can be exposed per hour for a given mask level.

Because contact printing can damage

the surfaces of both the mask and the
wafer, manufacturing lines utilize
proximity and projection printing
systems. (Figure 2.11)

Contact printing

In proximity printing, the mask is

brought in very close proximity to the
wafer, not contacting with the wafer
during exposure, thus preventing
damage to the mask.
Projection printing uses a dual-lens
system to project a portion of the
mask into the wafer surface. The
wafer and masks may be scanned or
the system may operate in a stepand-repeat mode.

Figure 2.11
Artists conception of various printing techniques.
(a) Contact
printing, in which wafer is in intimate contact with mask; (b)
proximity printing, in which wafer and mask are in close
proximity; (c) projection printing, in which light source is
scanned across the mask and focused on the wafer.

In large-diameter wafers, it is difficult to maintain alignment between mask levels

across the complete wafer, particularly with features whose size approaches 1.

High-resolution systems now use direct step-on-wafer techniques.

The pattern is aligned and exposed separately at each site directly on the wafer with a 1 or
10 reticle.
Very narrow patterns are often produced by writing the pattern using electron beams on the
wafer directly. (Direct writing)

Step and Repeater (stepper)

A single die image is projected directly onto the

surface of the wafer.
The reticle pattern may range from 1 to 10 times the
final die size.
The wafer is moved from die site to die site on the
wafer, and the pattern is aligned and exposed at each
individual site.

Figure 2.12 Concept of lens

system for a wafer stepper

Resolution & Depth of Focus

The minimum feature size that can be reproduced using optical lithography, resolution, is intimately tied
to the wavelength of light used for exposure.
A rough estimate of the minimum feature size F (line or space) that can be transferred to the wafer
surface is given by
l

F = 0.5

(2.1)

NA

where is the wavelength of the illumination, and NA is

numerical aperture of the lens defined in terms of the
convergence angle

(2.2)

NA = sin q

For NA=0.5, Eq. (2.1) predicts the minimum feature size to

be approximately the same as the wavelength of the optical
illumination.
A second concern is the depth of field DF over which focus
is maintained; an estimate for DF is

DF = 0.6

l
( NA)

(2.3)

Based upon Eqs. (2.1) and (2.2) with NA=0.5, one-tenthmicron technology (F=0.10 ) would require a 100
illumination source and have only a 240 depth of field.

Focus will be maintained over a distance of only 0.12

from the primary focal plane.

Figure 2.14
Optical focal plane and depth of focus

Resolution & Depth of Focus

l = Wavelength of illuminating light

Resolution = K 1
NA

K1 = Process constant
NA = Numerical aperture

Smaller

light source & optics

Lower K 1

process/resist improvements
improved optical schemes

Higher NA

lens design improvements

DOF = K2

(NA) 2

K2 : depending on the criteria used to define

acceptable imaging & on the type of feature

EXPOSURE SOURCES

A typical emission spectra from a Hg-Xe lamp

Output is relatively low in the deep ultraviolet

(DUV) region (200300 ), but exhibits
several strong peaks in the UV region
between 300450

To minimize problems in the lens optics, the

lamp output must be filtered to select one of the
spectral components.
The most common monochromatic selections
are the 436 , or g-line, and 365 , or i-line,
spectral components

Figure Spectral content of an Xe-Hg lamp

(Courtesy of SVG) The high-pressure
mercury-arc lamp is widely used in exposure
tools because of high intensity and reliability

Used for mass production

with a R of 70nm for F2

In this deep UV case, it is important to find

suitable resists and transparent optical
components at these wavelengths

Resolution enhancement techniques

Diffraction spreads

(a) Resolution is lost, because diffraction

has caused overlap of the individual line
images.

Prof. Nathan Cheung, U.C. Berkeley

(b) A 180 phase-shifting layer is applied

over one of the openings on the mask, and
the two individual lines appear well defined
in the intensity profile at the image plane

reference

Advanced lithography
Needs:
Optical lithography has advantages of high throughput, good resolution,
low cost, ease in operation. However, due to the requirement for deepsubmicron or nanometer IC processes, we need to find alternatives.

- Electron beam lithography

- Extreme UV lithography
- X-ray lithography
- Ion beam lithography
- LIGA process for MEMS/NEMS

Electron-beam lithography
Primarily used to produce high-quality masks and reticles
Exposure system
e gun: generate a beam of e with a suitable current density (LaB6)
Condense lens: focus e beam to a spot size 10 to 25um
Beam blanker: e beam on/off
Beam deflection coils: direct the focused beam to any location
in the scan field on the substrate.

Advantages
- Highly automated and precisely controlled, greater DOF,
high resolution ~10nm, direct patterning

Disadvs.
- low throughput ~10 wafers/h for <0.25um, high cost
Raster scan:
- resist patterns are written by a vertically-oriented beam that moves in a mode, blanked where no exp. required
Vector scan:
- beam is directed only to the requested pattern features and jumps from feature to feature, rather than scanning
the whole chip

Electron-beam resist : similar to the behavior of a PR

Common positive e-beam resists:
poly-methyl methacrylate (PMMA), poly-butene-1 sulfone (PBS). R is ~ 0.1 um or better
Common negative e-beam resists:
poly-glycidyl methacrylate-co-ethyl-acrylate (COP). R is limited to ~1um due to swelling
during development

The Proximity Effect :

In e-beam lithography, R is not limited by diffraction (because the W/L associated with e
of a few keV and higher energies are less than 0.1 nm) but by electron scattering.
Collisions involve as the e penetrate the resist film and underlying
substrate, leading to energy losses and pass changes.
Thus, incident e spreads out until either all the energy
is lost or it leaves the material because of backscattering.
Ebeam irradiation at one location will affect the irradiation in neighboring locations since
the dose of a resist is given by the sum of the irradiations from all surrounding areas,
limiting the minimum spacing between pattern features.

Extreme ultraviolet (EUV) lithography

promising NG lithographic technology to extend the min. linewidth to 30nm
w/o throughput losses
4x optical projection lithography with EUV
laser-produced plasma or synchrotron radiation serves as the
source, whose W/L 10~14nm
EUV radiation is reflected by a mask that is produced by
patterning an absorber material deposited on a multilayer
coated flat Si or glass-plate mask blank.
EUV radiation is reflected from the nonpatterned regions of
of the mask through a 4x camera and imaged into a thin layer
of resist on the wafer.

Problems
Must be performed in a vacuum due to strong absorption of EUV
Required defect-free multilayered reflection masks higher cost
Required an EUV source: higher cost
Must be considered sensitivity and line edge roughness of production resist

X-ray lithography
potential candidate for the fabrication of IC at 100nm. XRL uses a
shadow printing method similar to optical proximity printing
Characteristics
Very short wavelength : 4~50
Projection system of full size mask
Higher output with short exposure time
Little scattering and reflection
Low level of defects

Problems
hard to make an x-ray mask, low transparency at 1nm
Au should be used instead of Cr/glass
Need of high energy x-ray source
hard to develop x-ray resist use ebeam resist
X-ray aligning/exposure with 1:1 mask

Not applicable to mass production line, yet.

Ion-beam lithography
Among the highest resolution because ions have a higher mass and thus
scatter less than electrons little spread of ion beam, no backscattering

Problem
Difficulty in fabricating a Si stencil mask: due to problems such as stitching, complementary
mask stress control, Si trench etch

2.6 OPTICAL AND ELECTRON MICROSCOPY

H.W

Optical microscopy, Scanning Electron Microscopy (SEM), Transmission Electron Mi

croscopy (TEM) find wide application in the visualization of VLSI morphologies and p
rovide increasingly higher levels of magnification.

2.6.1 Optical Microscopy

Using white light for illumination with wavelengths centered on 0.5 , and with a
numerical aperture of 0.95, the resolution is approximately 0.25 (the resolution of
the human eye itself is approximately 0.25 .)

Optical microscopes have a maximum magnification of 1,000.

The lower end of the magnification range is 1 ~ 5.

Analytical microscopes can operate in either the bright-field or dark-field mode.

Bright-field operation is the mode that we most often encounter. The sample is illuminated
by light perpendicular to the plane of the sample back up into same operation path in the
microscope.
For dark-field mode, the sample is illuminated from an oblique angle, and light that is
reflected or refracted from features on the surface of the sample enters by the microscope
lens system. The surface of the sample appears mostly dark with the surface features
standing out in bright contrast against the dark back-ground.
; Surface feature that are washed out in bright-field mode can be clearly observed.

2.6.2 Scanning Electron Microscopy (SEM)

The surface of the sample is bombarded with a low-energy (0.5~40KeV) beam of

electrons. The incident electron beam causes low-energy (0~50eV) secondary
electrons to be ejected from the inner shells of the atoms making up the surface of the
sample under analysis. An image is formed by scanning the surface of the sample and
recording the intensity of the secondary electron current.

The magnitude of the secondary electron current depends upon the materials present and on
the curvature of the surface, and significant contrast can be achieved due to varying surface
morphology and materials.
The SEM extended the minimum resolution limit to 20~30, with magnifications up to 300,000.
at a magnification of 10,000 the SEM provides a depth of field of 2~4 .
; useful tool for investigating VLSI structure.

Some types of SEMs can suffer from

electrical charge-up of the sample by the
electron beam. (on insulating surface)

This can be eliminated by coating the surface

with a thin conducting layer of gold.
This requires special processing of samples
prior to their imaging by the SEM.

Figure 2.17
SEM image of a three-dimensional
micromechanical system (MEMS) structure

2.6.3 Transmission Electron Microscopy (TEM)

TEM extended the resolution of microscopy another order of magnitude down to the 2
range, which corresponds to a distance below the radius of most atoms.

In this instrument, a 60 ~ 400 KeV beam of electrons is used to illuminate a thin sample only
0.5~2 thick. The amplitude of the electron current that passes through the sample is detected,
and an image is created as the beam scans the sample.
In MOS structure, TEM can display an image of transition from the regular array of atoms in the
silicon lattice to the irregular amorphous layer of the silicon dioxide gate insulator (Figure 2.18)
TEM provides very high resolution, its application requires special preparation of the extremely
thin samples.

Figure 2.18
Cross-sectional high-resolution TEM images for CMOS structure with (a) 27 and (b) 24 image.
The polysilicon grains are easily noticeable in (a), the Si/SiOand poly Si/SiO2 interfaces are shown in
part (b). On a local, atomic scale, thickness variation of 2~3 are found which are a direct result of
atomic silicon steps at both interfaces.

SUMMARY
Photography is used to transfer patterns from masks to photoresist
on the surface of silicon wafers.
The resist projects portions of the surface while windows are
etched in barrier layers such as silicon dioxide, silicon nitride, or
metal.
The windows may be etched using either wet- or dry-processing
techniques.
Wet chemical etching tends to etch under the edge of the mask,
causing a loss of linewidth control at small dimensions.
Dry etching can yield highly anisotropic etching profiles and is
required in most VLSI processing.
After etching, impurities can be introduced into the wafer through
the windows using ion implantation or high-temperature diffusion, or
metal can be deposited on the surface making contact with the
silicon through the etched windows.

SUMMARY(Contd)

Masking operations are performed over and over during IC processing, and the
number of mask steps required is used as a basic measure of process
complexity.
Mask fabrication uses computer graphics systems to draw the chip image at 100
to 2,000 times final size.
Reticles 1 to 10 times final size are made from this computer image, using
optical pattern generators or electron-beam systems.
Step-and-repeat cameras are used to fabricate final masks from the reticles, or
direct step-on-wafer systems may be used to transfer the patterns directly to the
wafer.
Today, we are reaching the limits of optical lithography.
Present equipment can define windows that are approximately 0.15 wide.
(Just a few years ago, experts were predicting that 1 ~ 2 would be the limit!)
Electron-beam and X-ray lithography are now being used to fabricate devices
with geometrical features smaller than 0.10 , and lithography test structures
have reproduced shapes with minimum feature sizes below 0.05 .
The wavelength of light is too long to produce much smaller geometrical features,
because of fringing and interference effect.

Details on unit step

for Optical lithography

THE PHOTOLITHOGRAPHIC PROCESS (clean room)

Ultraclean conditions must be maintained during the lithography process.

Any dust particles on the substrate can result in defects in the final resist coating.
If defects occur in only 10% of the chip sites at each mask step, then <50% of the chips will be
functional after a 7-mask process is completed.
Vertical laminar-flow hoods in clean rooms are used to prevent particulate contamination
throughout the fabrication process.
Clean rooms use filtration to remove particles from the air and rated by the maximum number of
particles per cubic foot ( Class #) or cubic meter of air. (Table 2.1)

TABLE 2.1 Ratings by Class of Effectiveness of Filtration in Clean Rooms

Class
10,000
1,000
100
10
1

Number of 0.5 particles

per ft3(m3)
10,000
1,000
100
10
1

(350,000)
(35,000)
(3,500)
(350)
(35)*

Number of 5 particles
per ft3(m3)
65
6.5
0.65
0.065
0.0065

*It is very difficult to measure particulate counts below 10 per ft3.

(23,000)
(2,300)*
(230)*
(23)*
(2.3)*

PROCESS

An Example of Photolithography Process

Solvent
PR
SiO2

SiO2

1. Surface preparation

Wafer

6. Hard bake

PR
SiO2

2. Photoresist coating

Wafer

7. Develop inspection

Wafer

PR
SiO2
Wafer

Solvent

3. Soft bake

PR
SiO2
Wafer

8. Etch

PR
SiO2
Wafer

UV

4. Alignment and
Exposure

5. Development

PR
SiO2
Wafer

PR
SiO2
Wafer

9. Photoresist removal
(strip)

10. Final inspection

SiO2
Wafer

SiO2
Wafer

1. Surface preparation
Purpose
To clean and dry wafer surface

Chemical cleaning
To remove organic and inorganic contaminant residues

Chemical clean

DI water rinse

Spin dry

Dehydrate bake
Heating process for removing the moisture adsorbed on the wafer surface

Wafers and Wafer Cleaning

Figure 2.3 Illustration of wafer flat standard used to identify 100mm wafer

Wafers are chemically cleaned to remove particulate matter on the surface as well as any traces
of organic, ionic, and metallic impurities.

HF acid is used to remove any oxide.

A typical cleaning process (Table 2.2)

One very important chemical used in wafer cleaning and fabrication process is deionized(DI)
water, which is highly purified and filtered to remove any traces of ionic, particulate, and bacterial
contamination

Typical DI water systems achieve resistivities

Solvent Removal
18in-
at 25
1. of
Immerse
boiling trichloroethylene
(TCE)with
for 3 min.<1.2 colonies of
2.
Immerse in boiling acetone for 3 min.
bacteria
3.
Immerse in boilingper
methyl milliliter
alcohol for 3 min.and with no particles
4.
Wash in DI water for 3 min.
larger
than
0.25
.
Removal
of Residual
Organic/Ionic
Contamination

TABLE 2.2 Silicon Wafer Cleaning Procedure

A.

B.

1.

C.

D.

Immerse in a(5:1:1) solution of H2O-NH4OH-H2O2; heat solution to 7580 and hold for 10
min.
2.
Quench the solution under running DI water for 1 min.
3.
Wash in DI water for 5 min.
Hydrous Oxide Removal
1.
Immerse in a (1:50) solution of HF-H2O for 15 sec.
2.
Wash in running DI water with agitation for 30 sec.
Heavy Metal Clean
1.
Immerse in a (6:1:1) solution of H2O-HCl-H2O2 for 10 min at a temperature of 7580
2.
Quench the solution under running DI water for 1 min.
3.
Wash in running DI water for 20 min.

1. Surface preparation
Primer deposition
To promote adhesion between the organic photoresist and the inorganic silicon or
silicon compound wafer surface
HMDS (HexaMethylDiSilane)
(CH3)3SiNHSi(CH3)3)

2. Photoresist coating
Purpose
To coat a thin layer of photoresist on surface

After formation of a thin film, the surface of the wafer is coated with PR.

The surface must be clean and dry for a good PR adhesion.

A liquid adhesion promoter is often applied just prior to PR application. (HMDS)

PR is typically applied in liquid form by spin coating to for a thin uniform coating.

The PR thickness depends on its viscosity and spinning speed. (tPR speed1/2)

t = Ks[v /(wR )]
Where,

K : constant
s : quantity of polymer
v : viscosity coefficient
w : angular velocity
R : radius of wafer

2. Photoresist coating
Schematic of a photoresist spin coater

PR dispense method
Static dispense method
Dynamic dispense method

2. Photoresist coating
Method of edge-bead removal (EBR)

Chemical EBR

Optical EBR

3. Soft bake
Purpose
Partial evaporation of photoresist solvents by heating
To improve the PR adhesion to the wafer surface

After soft bake

The PR thickness shrinks about 10 % to 20 %.
The PR consists of about 5 % to 20 % solvent residue.

Under-baking in the soft bake step

Either because the baking temperature is too low or the baking time is too short.
The PR might peel off from the wafer surface during subsequent processes due to
adhesion failure.
Can affect the pattern resolution

Over-baking in the soft bake step

Can cause premature polymerization of the PR insensitive to the exposure light
Can cause insufficient catalysis chemical reaction image underdevelopment

3. Soft bake
Methods

Can avoid the PR crust problem

90~120 C, 30 minutes

No crust by bottom-up heating

A single wafer system

Hot nitrogen flowing oven

Very short time for microwave

Possible in-line coating, baking,

Batch process

due to high energy

and developing

Crust traps solvent on the film

4. Photoresist Exposure and Development

Following alignment, the PR is exposed

through the mask with UV light.

The exposed PR is developed with a

process very similar to that used for
developing ordinary photographic film,
using a developer.
Positive resist : PR which has been
exposed to UV light is washed away.
Negative resist : PR which has been
exposed to UV light remains on the
surface.
Positive PR yields better process control
in small-geometry structures and is now
the main type of resist used in VLSI
process.
Figure 2.6 Resist and silicon dioxide patterns following
photolithography with positive and negative resist

4.1 Mask Alignment

A photomask : a square plate with a patterned emulsion or metal film on one side.
Each mask following the first must be carefully aligned to the previous pattern on the
wafer, by either operating the alignment equipment (mask aligner) manually or at
computer-controlled mode.

Minimum feature size of 100 (0.1 ) will require a worst case alignment error of better
than 35 (mean + 3).
The wafer is held on a vacuum chuck and moved into position below the mask.
The mask is spaced 25-125 above the surface of the wafer during alignment.
If contact printing is used, the mask is brought into contact with the wafer after alignment.

Alignment marks are introduced on each mask and transferred to the wafer as part of
the IC pattern. A sample set of alignment marks is shown in Figure 2.5.

Split-field optics are used to simultaneously align two well-separated areas.

Figure 2.5
A simple set of alignment marks. At some
steps a cross may be aligned within a box. At
others, a box may be placed around the cross.
The choice depends on the type of resist being
used at a given mask step.

4.2 Alignment and Exposure

1. Contact and Proximity printers
Contact aligner
The earliest and simplest alignment and exposure process
Full wafer size photomask
High defect level, mask cost, resolution, alignment limitation
Mask-to-wafer contact particle contamination, damage in PR and mask
Proximity aligner
The mask about 10 to 20 um away from the PR
Much less particle contamination and much longer mask lifetime

Contact aligner

Proximity aligner

4. Alignment and Exposure

2. Projection printer
Projection exposure system
The VLSI semiconductor fabs.
1 um minimum feature sizes.
Scanning projection exposure system
Synchronized mask and wafer movement

Projection exposure system

Scanning projection exposure system

4. Alignment and Exposure

3. Steppers
Stepping image using reticle
Better overlay and alignment
by individual
5x or 10x reticle use
Resolution improvement
G- or I-line
Automatic alignment system

Stepper exposure system

4. Alignment and Exposure

Requirement of exposure light source
Stable

Short wavelength

Reliable

High intensity

Adjustable

Long lifetime

Light sources for photolithography in fabrication and R&D

4. Alignment and Exposure

Accurately aligned

Poorly aligned

5. Development
Purpose
Removal of unpolymerized resist

Schematic of a spin developer system

The three steps of the development process

Development

Rinse

Spin dry

5. Development
Positive PR
Exposed region unpolymerize
Developer : alkaline-water (NaOH, KOH), nonionic solution (TMAH, (CH3)4NOH))
Rinser : water
More sensitive than negative PR

Negative PR
Exposed region polymerize
Developer : xylene
Rinser : n-butylacetate

5. Development
Photoresist profile for different developments

Normal
development
scum
Incomplete
development
Underdevelopment
Overdevelopment
Positive PR

Negative PR

6. Hard bake
Purpose
To improve the PR etch and implantation resistance and improve its adhesion to
the wafer

Similar to soft bake process

The most commonly used way is the hot plate (100~130C, 1~2 minutes).
130~200 C / 30 min in convection oven

7. Pattern inspection
Purpose
To inspect surface for alignment and defects

Methods
Optical microscope : larger-dimension
features inspection
SEM (Scanning Electron Microscope) :
sub-half-micron features inspection

Defects
1. Contamination
2. Opaque spot
3. Large hole
4. Pin hole

5. Excess material
6. Lack of adhesion
7. Intrusion
8. Scratch
9.

8. Next process
Etch
Wet etch
Dry etch
Plasma etch
Ion beam etch
RIE (Reactive Ion Etch)

Ion implantation

9. PR strip
Purpose
To remove photoresist layer from wafer

Methods
Wet chemical removing ; strip, rinse, and dry
H2SO4:H2O2=4:1 @120
Cost effective
Metallic ion removal
No plasma damage
Plasma O2 strip
CxHy (resist) + O2 CO + CO2 + H2O

10. Final inspection

Purpose
Surface inspection for etch irregularities and other problems

Method
Similar to develop inspection process