Designing with Qsys

Lab Exercises

2011 Altera Corporation. The material in this wiki page or document is provided AS-IS and is not supported by Altera
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2011 Altera Corporation

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Lab Exercise Introduction

These lab exercises help you become familiar with the Altera Qsys system integration
tool by completing the following objectives:

Build a design with Qsys

Create custom IP for the Qsys library
Design a Qsys system with hierarchy
Simulate the Qsys system with Bus Functional Models (BFMs)
Debug and test the Qsys system with System Console

The exercises include the following labs:

Lab
Lab
Lab
Lab
Lab
Lab
Lab

1:
2:
3:
4:
5:
6:
7:

Explore an existing Qsys design

Migrate a design from SOPC Builder to Qsys
Import a new component
Design a Qsys system
Perform simulation for a system (optional)
Use hierarchy to assemble the final Qsys system
Use System Console to debug the system (optional)

Lab Prerequisites
The labs are bundled with supporting project files for each lab in the lab_qsys.zip archive.
The included project files ensure that you do not have to supply all constraints or top-level
code. You should start each lab by opening the project file from the appropriately
numbered lab directory. The fully completed design and programming files are also
provided.
These labs require the following software and optional hardware.
Table 1: Required Software and Optional Hardware
Required Software

Quartus II software
version 11.0

ModelSim Altera
Edition version 11.0

lab_qsys.zip
designs

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Optional Hardware
Nios II Embedded Evaluation Kit
(NEEK)
3.5mm audio cable

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Design Overview
The lab exercise uses the design illustrated in Figure 1 to teach you about designing with
the Qsys system integration tool.
Figure 1: Top-Level Design Block Diagram

In these labs you design a system to analyze the frequency spectrum of an input audio
signal, generate a picture of the frequency spectrum according to the results, and display
it on an LCD screen. All of the data paths use Avalon Streaming (Avalon-ST) interfaces.
All the control signals use Avalon Memory-Mapped (Avalon-MM) interfaces. The design
includes the following major components.

Audio Controller
The Audio In block formats the data into Avalon-ST data. The audio signal comes in on the
line-in port on the board. There is an audio ADC chip on the board which converts the
audio signal to digital data before the signal enters the FPGA. The Audio ADC chip on the
board can be configured through the I2C interface. The labs use the I2C controller to
convert the Avalon-MM interface into the I 2C control signal. The I2C controller configures
the audio chip when the board is powered up.

Data Analysis System

This data analysis subsystem analyzes the input audio data using a filter array and energy
calculation. The same input audio data is sent into 16 filters with the different pass and
stop frequencies. Figure 2 illustrates the frequency response for 16 filters in which the X
axis is frequency and the Y axis is frequency response value.

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Figure 2: Frequency Response Diagram for 16 Filters

The audio input data is sampled at 48 KHz. The labs use 16 filters with 40 taps each. 48
KHz x 16 x 40 = 30.72 MHz. Thus 30.72 MHz is the throughput requirement of the system.
The lab design uses the 48 MHz clock as the main clock for the calculation, which is higher
than the throughput requirement of the system. This means you can use a single
multiplier and accumulator to design this whole filter array. Figure 3 shows the outputs of
the 16 filters, where the X axis equals the time line and the Y axis equals the data value.
Figure 3: Example Data Results of FIR Filters

The Energy block accumulates the absolute value of the filter result and sends the energy
data out as a packet with 16 bits of data in Avalon-ST format, as shown in Figure 4, where
the X axis equals the filter frequency area and the Y axis equals the energy reset value.
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Figure 4: Energy Diagram for 16 Frequency Areas

Figure 4 shows that the frequency response area increases from left to right. A parallel
I/O (PIO) connected to a push button on the board configures the calculation period for the
energy. You can change the value to 256, 1024, 4096, or 16384 samples. The Analysis
Controller triggers when the button is pushed, and configures the register in the Energy
block to set the sample number. The Energy block accumulates the absolute value of the
FIR results with samples according to the number. For example, if the sample number is
specified as 4096, the Energy block accumulates 4096 times and outputs one result.
Energy results are sent out as streaming data. Figure 4 shows an example of the energy
result for each of the 16 filters.

Energy2LCD Block
The Energy2LCD block converts the energy signals into a graphical representation and
sends the results to the LCDController block. To save resources, the real picture is not
stored in the design.
The on-board LCD has a resolution of 480x800 pixels, divided into 16 sections that each
represent the energy result of one filter. The energy result is nine bits of data (and any
data bigger than 480 is treated as 480). For example, if the energy result is 100, all of the
lines smaller than 100 are sent out in red color. For all of the lines greater than or equal to
100, the lines are sent out in blue color. This displays the entire energy diagram with
minimum resource usage. The Energy2LCD block receives the data from the Energy block
as a streaming input, and sends out the frame as streaming data.

LCD Controller
The LCDController converts the video data into an LCD format and drives the LCD
display directly. The LCD Controller accepts 32-bit data. The PixelConverter changes

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the 32 bits into 24 bits. The DataFormatAdapter changes the data from parallel into
serial with the sequence of R, G, B (red, green, blue). The VideoSyncGenerator
generates the sync signal for the LCD, and controls the frame rate of the output. There is a
control port on the LCD, that uses the I2S bus. There is one I2S block in the LCD
controller to convert the Avalon-MM control signal into an I 2S bus, and uses a State
Machine to initialize the LCD on the board.

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Lab 1: Explore an Existing Qsys Design

This lab introduces you to the Qsys GUI by exploring a complete design. The estimated
time to complete this lab is 60 minutes, including optional board programming.

LCD Controller Subsystem Overview

This lab describes the LCD control system in Qsys, generation of the Qsys system,
compilation of the project with the Quartus II software, and optional downloading of the
the result to the NEEK board. Figure 5 shows the components in the LCD controller.
Figure 5: LCD Controller Block Diagram

The LCD controller includes the following components:

The Energy2LCD block generates the image displayed on the LCD. It provides an image even
without any input. In this system, you can treat the block as a pattern generator. This block
sends 32-bit wide streaming data, representing parallel pixel data.
The Pixel Converter block converts the 32-bit input into 24-bit RGB video parallel data.
The Data Format Adapter block converts the parallel data into serial R, G, B with an 8-bit
streaming output. This satisfies the Video Sync Generator block data width requirement.
The Video Sync Generator generates the video sync signals, such as the frame sync and
line sync signals. This block also receives and sends data from the Data Format Adapter
block.
A FIFO is typically required between the data format converter and the Video Sync
Generator to ensure that the Video Sync Generator can control the LCD frame rate. But in
this design, since the Energy2LCD block can provide data whenever necessary, the FIFO is
not needed.
The I2S block configures the LCD chip on-board based on the I 2S bus. The system can
control or monitor status of the block through its Avalon-MM slave interface. In this lab, the
block performs the initial configuration. The Avalon-MM slave interface is present in this lab
only to show the capability of the bus and available options.

View the LCD Controller

To view the LCD controller, follow these steps:
1. In the Quartus II software version 11.0, click Open Project and open the
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LAB_1 /Qsys_lab.qpf project.

2. On the File menu, click Open and select the lcd_ctrl_subsys.qsys Qsys file. Qsys refreshes
the libraries and displays the system as shown in Figure 6.
Figure 6 LCD Controller System in Qsys

3. Review the system to become familiar with the Qsys GUI. The left pane contains the
Component Library, and the right pane shows the system connections in the System
Contents tab.
4. To filter the connections view based on the Qsys-supported interface types, click the Filter
button. Qsys supports Avalon-MM, Avalon-ST, clock, and reset interfaces. In addition Qsys
supports conduit interfaces for non-standard groups of signals.
5. Click the Address Map tab to show the address mapping information between all of the
Avalon-MM master and Avalon-MM slave interfaces. You can also edit the start address for
each slave interface, as illustrated in Figure 7.
Figure 7: LCD Controller System in Qsys

6. Click the Clock Settings tab to view all clocks in the design, as shown in Figure 8. In Qsys,
clocks are interfaces that are connected to components in the same manner as other
component interfaces. You can also use the Clock column in the System Contents tab to
make clock connections.

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Figure 8: Clock Settings Tab

7. Click the Project Settings tab to show global information about the system, including a
block diagram showing the exported top-level input and output interfaces and some other
global settings.
8. Click the System Inspector tab to inspect the system connections, including the external
signals list, the internal connections, and all of the submodules in the system, as shown in
Figure 9.
Figure 9: System Inspector Tab

9. Click the HDL Example tab to display an example Verilog HDL or VHDL instantiation of the
top-level design file that Qsys generates. You can copy from this tab and paste into your toplevel HDL file when you are creating a design that instantiates a Qsys system.
10. Click the Generation tab to generate code for simulation and synthesis under a
subdirectory of the specified path. The simulation files are generated in the simulation
directory, including the simulation model files and a Tcl file to set up the simulation
environment in ModelSim. The Qsys testbench system is generated in the testbench
directory. If you enable the option to create a testbench simulation model, the simulation
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files are generated in the same directory. Qsys generates a simple testbench that provides
only the clock and reset signal stimulus (along with any simulation partner modules specific
by your IP), as well as a standard testbench that also includes simulation BFM blocks for all
of the exported Avalon interfaces. Use of this testbench is described in a subsequent lab.
Figure 10 shows the Generation tab.
Figure 10: Generation Tab

11. On the Generation tab, make sure that Create HDL files for Synthesis is turned on, and
disable all other options. Because this step does not include simulation, make sure that the
Create simulation model and Create testbench Qsys system options are set to None.
12. Click Generate to generate HDL files for the Qsys design. Click Close when generation is
complete. The synthesis code is generated at the specified location. You can view the files in
the synthesis directory.
13. To add the Qsys-generated design files to the Quartus II project, click Settings on the
Assignments menu in the Quartus II software.
14. In the Category list, click Files and add lcd_ctrl_subsys.qip to the project. Qsys updates
the .qip file each time you modify and generate the system.
15. To compile the project, click Start Compilation on the Processing menu.
16. You can now use the Quartus II Programmer to download your design to the NEEK.

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Lab 2: Migrate a System from SOPC Builder to Qsys

This lab teaches you how to take advantage of the Qsys advanced system integration
features by migrating a system created with Alteras legacy SOPC Builder to Qsys. The
LAB_2 directory of the lab_qsys.zip archive contains the supporting files for this lab. The
estimated time to complete this lab is 30 minutes.

Convert the SOPC Builder Project

The files for this lab include an example SOPC Builder audio controller design that you can
migrate to Qsys. This example is a very simple design that includes a PLL that generates a
48-MHz clock domain based on the 50-MHz input clock. The data streaming uses the 48MHz clock, and the I2C configuration logic uses the 50-MHz clock. The I 2C configures the
Audio AD chip on the board, and is controlled by the State Machine block. The Audio
Interface block accepts the audio data from the AD chip, groups it into the Avalon-ST
interface, and sends it out through the source interface. Figure 11 illustrates the SOPC
Builder audio controller design.
Figure 11: Audio Controller Diagram for SOPC Builder System

You must first prepare the SOPC Builder project prior to migration. To prepare the sample
SOPC Builder project for migration, follow these steps:
1. In the Quartus II software, click Open on the File menu and select the
LAB_2/audio_controller.sopc file. Reject the prompt to launch Qsys and remain in SOPC
builder for this section of the lab.
2. To complete the design and avoid errors in SOPC Builder, add an additional Avalon-ST sink
BFM block and connect it to the source interface of the AUDIO_IF block. In Qsys, such
unconnected interfaces generate only a warning and system generation is not prevented.
3. Save the system and close SOPC Builder.

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Export the SOPC Builder Design to Qsys

To export the SOPC Builder design to Qsys, follow these steps:
1. Reopen the /LAB_2/audio_controller.sopc file, allowing the file to open in Qsys when
prompted.
2. When prompted, enable the option to clean up SOPC Builder files. Qsys generates the
top-level code with the same name as the SOPC Builder project under a different location.
While SOPC Builder exports all of the PLL signals to the top level. Qsys provides more
flexibility for system integration. For example, while Qsys exports areset_conduit,
locked_conduit, and phasedone_conduit interfaces as I/O ports or signals, only the
locked signal must be exported to the top level.
3. Click in the Export column for the areset_conduit and phasedone_conduit rows, and
delete the exported interface name so these interfaces are not exported. This is how you
define which interfaces should be exported as I/O signals of the system.
4. Select and delete the unneeded c0 (clock bridge) block.
5. Save the file. The design should now appear as shown in Figure 12.
Figure 12: Audio Controller Qsys System

6. Click the Generation tab and click Generate to create the synthesis files for the design.
7. In the Quartus II software, click Start Compilation on the Processing menu.
8. After compilation is complete, use the Quartus II Programmer to download the .sof to the
NEEK board.

Once these steps are complete you can use Qsys to generate the synthesis files for the
Audio Controller block, add the generated audio_controller.qip to the Quartus II
project, and compile the design in the Quartus II software, as described below.

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Download Configuration Data

To download configuration data, follow these steps:
1. Connect the download cable to the NEEK board. You must first install the driver if you have
not done so.
2. Download the design to the board with the Quartus II Programmer.
3. Make the following connections to the three audio jacks on the top of the board:
Table 2: Required Software and Optional Hardware
Connect From
PC audio output
Earphone cable jack

Connect To
Blue line-in port of the NEEK board
Green line-out of the NEEK board

Because Qsys can perform reset synchronization, you can choose to connect all resets in a
single global reset domain by selecting Create Global Reset Network on the System
menu. If your design requires more than one reset domain, you can implement you own
reset logic and connectivity.

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Lab 3: Import a New Component

You can create a reusable, custom IP component by importing HDL code to the Qsys
Component Editor. This lab shows you how to create a custom reusable IP block for use in
Qsys. The LAB_3 directory of the lab_qsys.zip archive contains the supporting files for
this lab. The estimated time to complete this lab is 45 minutes.
The LAB_3 directory provides the HDL code files for the Energy block calculation. The
Energy block accepts data from the Avalon-ST sink interface, and sends the result out
through the Avalon-ST source interface. This block contains an Avalon-MM slave interface
for control. Table 3 shows the register mapping for the Energy block:
Table 3: Energy Block Address Map
Address

Access

Register

0x00 0x1f

Read Only

The energy result for each frequency area.

0x20

Write/Read

The calculation length for the energy

calculation. For example if the data is 2048,
the Energy block accumulates 2048 samples
of input as the output.

To create a new Qsys component by importing HDL code, perform the following steps:
1. In the Qsys Component Library, double click New Component. The Component Editor
appears.
2. Click the HDL Files tab.
3. Click Add and add the energy.v, res_ram.v, and ram_bk.v files from the LAB_3 directory
to the HDL Files list.
4. For each file, make sure that the Synth and Sim options are enabled.
5. Turn on the Top option for energy.v to designate it as the top-level file. Note that memory
initialization files need to be included into this file list if they are needed. Qsys copies all of
the IP files into the submodules directory, thus any files necessary for synthesis or
simulation must be included.
6. To define the interface signals, click the Signals tab. Qsys recognizes the clock signal as a
clock interface automatically. You may need to define the signals for other interfaces. If the
correct interface type is not listed, you can define a new interface on the Interface tab.
7. To define the rst_n signal as a reset_sink interface, click the Interface column and select
new Reset Input.
8. Define the signals in Figure 13 for the clock, reset input, Avalon slave, Avalon-ST sink, and
Avalon-ST source interfaces. The interfaces you define now appear on the Interfaces tab.

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Figure 13: Signal Definitions in Qsys Component Editor

9. Click the Interfaces tab.

10. Click Remove Interfaces With No Signals.
11. For each interface, specify clock for Associated Clock, and reset_sink for Associated
Reset. Note that reset interfaces are different between Qsys and SOPC Builder. You can
define both reset input and reset output interfaces in Qsys.
12. For the Avalon-ST source and sink interfaces, specify 16 as the Data bits per symbol. The
Energy block receives the data from FIR and outputs the result to the next stage. Therefore
these interfaces are 16 bits wide.
13. To view any HDL parameters associated with the interfaces, click the HDL Parameters tab.
If the HDL code includes any parameters, the Component Editor generates a GUI for use in
setting these values during instantiation. This lab includes the OUTPUT_MSB parameter in the
energy.v file.
14. Click the Library Info tab. In Display name, type Energy and do not modify the value of
Version. In the Group box, specify FAE Certification Lab.
15. Confirm that there are no error or warning messages, and then click Finish in the
Component Editor.
16. In Qsys, click Save to save your changes.

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Lab 4: Design a Qsys System

You can create your own Qsys system from scratch. This lab shows you how to create the
new Qsys system shown in Figure 14. The LAB_4 directory of the lab_qsys.zip archive
contains the supporting files for this lab. The estimated time to complete this lab is 30
minutes.
Figure 14: Data Analysis System Block Diagram

Create a New Qsys Design

To create a new Qsys design, perform the following steps:
1. In the Quartus II software, open the LAB_4/quartus_lab.qpf project.
2. On the Tools menu, click Qsys. Qsys displays a new system with only a single clock source.
3. Save the new system as data_analysis.

Define an IP Component
You must add four IP blocks to the system and make the connections. To add the IP blocks
to the system, follow these steps:
1. In the Qsys Component Library, double-click Peripherals > Microcontroller
Peripherals > PIO (Parallel I/O). The parameter editor displays the properties of the IP
core. The PIO IP core is provided with Qsys for general purpose I/O signals. In this lab, you
simply connect it with the push button on the board.
2. Specify the following options shown in Figure 15 for the PIO component:

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Figure 15: PIO Parameters

3. Click Finish to generate the component.

4. Click Save and rename the system as data_analysis.
5. In the Qsys System Contents tab, right-click the PIO component you defined and rename
the PIO instance to as push_buttons.

Add Other IP Components

This lab includes an FAE Certification Lab group in the Qsys Component Library. This
group includes all of the IP cores necessary for this lab. To add IP cores from this group to
your system, follow these steps:
FIR
1. Under the FAE Certification Lab group in the Qsys Component Library, double-click the
FIR component. The parameter editor appears.
2. To accept the default parameters and add the component to the system, click Finish.

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data_analysis_state_machine
The data_analysis_state_machine component is required in the system to accept the
interrupt signal from the PIO and configure the Energy block. To define the
data_analysis_state_machine component, follow these steps:
1. Under the FAE Certification Lab group in the Qsys Component Library, double-click the
data_analysis_state_machine component. The parameter editor appears.
2. Specify the following values:
CALCULATE_NUM0: 256
CALCULATE_NUM1: 1024
CALCULATE_NUM2: 4096
CALCULATE_NUM3: 16384

The state machine switches between these four numbers, and writes the number into the
Energy block when the push button is active. There are two master interfaces in this state
machine, and you use the avalon_master interface to control the PIO and accept the
interrupt. You use the avalon_master_1 interface to write the calculation number into the
Energy block.

Export Interfaces
The fir_in interface of the FIR block drives the data_in for the data path. This is an AvalonST sink interface. To export appropriate interfaces, follow these steps:
1. On the Qsys System Contents tab, click the Export column for the data_in interface and
type fir_in as the name of the exported interface. fir_out is connected to the energy_in
interface in the Energy block.
2. On the Qsys System Contents tab, click the Export column for the energy_0 interface and
type energy_out as the name of the exported interface.
3. On the Qsys System Contents tab, click the Export column for the push_buttons interface
and type push_buttons_external_connection as the name of the exported interface.

Make Connections
To make connections between the components, follow these steps:
1. On the System Contents tab, connect all clock and reset signals to the clock output and
reset output from the clock source:
a. To connect the clocks, specify the clock signal name in the Clock column.
b. To connect the resets, click Create Global Reset Network on the System menu.
2. Click in the Connections column to fill in the black dot for each connection shown in Figure
16. Use the up and down arrows in the toolbar to change the order of components in the
system.

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Figure 16: Data Analysis System Connections in Qsys

3. Click the Generation tab.

4. Click Generate to create the HDL design files for synthesis.
This lab completes the basic system design. In the next labs you simulate this design and
perform in-system debug with the System Console. You connect this system with the other
subsystem to create the top-level Qsys design.

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Lab 5: Simulate the Data Analysis System (optional)

You can simulate the data analysis system. This lab shows how to use the Altera Avalon
Verification BFMs to verify the Qsys system from Lab 4. The LAB_5 directory of the
lab_qsys.zip archive contains the supporting files for this lab. The estimated time to
complete this lab is 45 minutes.
In this lab, you use Verilog HDL to highlight the BFMs and automated testbench
generation. The data_analysis design is the design under test (DUT), the FIR block is
driven by an Avalon-ST source BFM component, and the data from the Energy block is
verified by an Avalon-ST sink BFM component.
If your design is based on VHDL, you do not have to use a Qsys-generated testbench with
Avalon BFMs. You can create your own simulation environment and generate VHDL
simulation model files in Qsys.
This lab includes the following sections:

Create Avalon standard BFMs for your DUT

Prepare a test program that calls BFM APIs
Start a simulation

Create Avalon standard BFMs for your DUT

To create Avalon standard BFMs for your DUT, follow these steps:
1. In the Quartus II software, open the LAB_5/quartus_lab.qpf project.
2. On the Tools menu, click Qsys.
3. On the File menu, click Open and select the completed data_analysis.qsys file.

4. Review the following exported interfaces shown in Figure 17:

clk
reset
push_buttons_external_connection
fir_in
energy_out

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Figure 17: Data Analysis System Connections in Qsys

5. Click the Generation tab.

6. For Create testbench Qsys system, select Standard, BFMs for standard Avalon
interfaces.
7. For Create testbench simulation model, select None.
8. Under Synthesis, turn off all options. Figure 18 shows the correct settings.
9. Click Generate. Qsys generates a testbench system for the design under test.
Figure 18: Generation Settings for Qsys Testbench System

10. From the \LAB_5\data_analysis\testbench directory, open the data_analysis_tb.qsys

file to change BFMs component settings or rename BFM components, if needed.

The Qsys-generated testbench automatically includes matched BFMs for all

exported interfaces of the DUT as shown in Figure 19.

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Figure 19: Matched BFMs for all Exported Interfaces of the DUT

Qsys inserts clk_bfm, reset_bfm, fir_in_bfm, energy_out_bfm and a conduit bfm for
this DUT. The Avalon-ST source or sink BFM component includes the following four
parts related to Avalon-ST protocol parameters. If you add BFMs manually, you need
to adjust them to meet your requirement.
Port enables
Port widths
Timing attributes
Channel attributes
11. After reviewing the testbench, click the Generation tab.
12. For Create simulation model, select Verilog.
13. For Create testbench Qsys system, select None.
14. Under Synthesis, turn off all options.
15. Click Generate. Qsys generates the testbench system simulation models in the
\LAB_5\data_analysis\testbench\data_analysis_tb\simulation directory.

Prepare a test program that calls BFM APIs

You can generate the simulation model for the Qsys testbench system at the same time
that you create the system by turning on Create testbench simulation model.
However, for demonstration purposes this lab shows you how to create the models in two
steps so you can control the instance names or adjust settings to make it easier for you to
write your own test program for the BFMs, as illustrated in Figure 20.

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Figure 20: Generation for Simulation Model

Qsys generates the simulation models and a ModelSim simulation script

(msim_setup.tcl), which compiles the required files for simulation and sets up commands
to load the simulation in the ModelSim simulator.
This lab section uses the provided test_program.sv external test program to call BFM
APIs that provide simulation stimulus. The provided load_sim.tcl simulation script
compiles the top-level simulation file and test program, and calls the msim_setup.tcl
Qsys-generated script to compile the required files.
Copy the simulation files (load_sim.tcl, test_program.sv, top.sv, wave.do) from the
simulation files folder into the
\LAB_5\data_analysis\testbench\data_analysis_tb\simulation directory.
1. To understand how to use the BFM APIs, open and view the test_program.sv. Test
programs should be implemented in SystemVerilog. The test_program implements the
following functions:
Initializes BFMs
Calls APIs to Avalon-ST source BFM
Constructs stimulus Avalon-ST transactions
Pushes transactions
Calls APIs to Avalon-ST sink BFM
Monitors signal_transaction_received
Pops transactions to receive the data

For details on the BFM APIs, please refer to Avalon Verification IP Suite User Guide
available at http://www.altera.com/literature/ug/ug_avalon_verification_ip.pdf.
2. Launch the ModelSim Altera Edition software.
3. On the Compile menu, click Compile Options and turn on Use SystemVerilog.
4. Turn off the Use vopt flow option, as shown in Figure 21.
Figure 21: Enable SystemVerilog Support

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5. From the File menu, change to the

\LAB_5\data_analysis\testbench\data_analysis_tb\simulation directory.
6. To speed up the simulation process, open the
\LAB_5\data_analysis\testbench\data_analysis_tb\simulation\submodules\energ
y.v file and change the value 4096 to 512 on line 121, as shown in Figure 22.
Figure 22: Changes to Energy.v.

7. From the Tools menu, go to Tcl -> Execute macro, and execute load_sim.tcl.
8. Run the simulation for 12ms with the run 12 ms command.
9. Observe the wave results. As you can see from the simulation, the result for the first
packet is
[2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0], as shown in Figure 23.
Figure 23: Simulation Wave Diagram

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Lab 6: Use Hierarchy to Assemble the Final Qsys system

You can use hierarchy features in Qsys to assemble the top level system. This lab shows
you how to design a top-level Qsys system by combining multiple Qsys subsystems. The
LAB_6 directory of the lab_qsys.zip archive contains the supporting files for this lab. The
estimated time to complete this lab is 90 minutes.
The uses the following components:

LCD Controller system (the design you explored in Lab 1)

Audio Controller system (the design you converted from SOPC Builder in Lab 2)
Data Analysis system (the design you made in Lab 4 )
Clock controller

Review and Adjust the Clock and Reset Structure

To review the clock and reset structure, follow these steps:
1. In the Quartus II software, open the LAB_6/quartus_lab.qpf project.
2. On the Tools menu, click Qsys.
3. Use the Open command on the File menu to open the following Qsys projects:
Lcd_ctrl_subsys
Audio_in_subsys
Data_analysis_subsys
Clock_subsys
4. Open the clock_subsys.qsys project to review the clock and reset structure of the design,
as illustrated in Figure 24.

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Figure 24: Clock Controller System

Use this system to review the structure of clocks and resets. Use a reset bridge to
bring the reset into the system, and use a clock source to bring the clock in. Use the
PLL to generate three internal clock domains. The video_clk is exported on board
as the video chip clock. The LCD_controller uses LCD_clock. The audio controller
and data analysis systems use audio_clk.
5. Review the other three systems. Because the design for this lab has an independent clock
system, the PLL and reset control part in the Audio block and the LCD controller are
removed. This is the only difference between the subsystems here and the systems in
previous labs.
6. On the Qsys File menu, click New System and save the new design as system.
7. On the System Contents tab, change the name of the clk_0 Clock Source instance to
clk_in, and set the exported Clock Input interface name to clk_in.

Add the Reset Bridge

1. From the Component Library, double-click the Reset Bridge to define the global reset
block that creates the reset connection. Specify the following options for this component:
a. Turn on Active Low Reset.
b. In the Synchronous Edges list, select None.
2. In the Export column, specify the export of the in_reset interface with the name of reset_n
and connect the out_reset Reset Output interface with the clk_in_reset Reset Input
interface of the clk_in block.

Add the Clock Subsystem

1. From the Component Library, double-click the Project -> System -> clock_subsys
component to add it to the system. There are no parameters available when instantiating
subsystems.
2. Change the clock_subsys instance name to clock_generate.
3. Connect the clk_in of the clock_generate block to the clk_in output of the clk_in block.
4. Connect the reset_n input to the out_reset from the global_reset block.
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5. Export the video_clk and the pll_locked interfaces with the default names. Clocks and resets
are exported by default when instantiated. You can click on the Export column to delete the
contents when the signal should be connected internally instead of being exported.
6. Add audio_in_subsys into the system and name the instance audio_in.
7. Connect audio_clk_in with the audio_clk_clkfrom the clock_generate block.
8. Connect config_clk with the clk_in signal of the clk interface.
9. Connect the corresponding reset interfaces for each clock.
10. In the Export column, export audio_if_0_audio_export interface as audio_export.
11. In the Export column, export i2c_audio_conduit_end as i2c_audio.

Add the Data Analysis Subsystem

1. From the Component Library, double-click the Project -> System ->
data_analysis_subsys component to add it to the system.
2. Change the subsystem instance name to data_analysis.
3. Connect the clock source to audio_clk_clk and connect the corresponding reset.
4. Export push_button_external_connection as push_buttons.
5. Connect the fir_in interface with the audio_if_0_audio_st interface from the audio_in block.

Add the Engery2LCD Subsystem

1. From the Component Library, double-click the FAE Certification Lab -> Energy2LCD
component to add it to the system. This is the block to convert the energy result to be the
LCD video pictures.
2. Rename the Energy2LCD block as Energy2LCD_inst.
3. Connect core_clk with the lcd_clk.
4. Connect sink_clk with audio_clk.
5. Connect the corresponding reset interfaces.
6. Connect the st_sink interface with the energy_out interface from the data_analysis block.

Add the LCD Controller Subsystem

1. From the Component Library, double-click the System -> lcd_ctrl_subsys component to
add it to the system.
2. Rename the lcd_ctrl_subsys block instance as lcd_ctrl.
3. Connect lcd_clk with lcd_clk from the PLL.
4. Connect lcd_i2s_clk with clk_in ofclk.
5. Export the lcd_video_sequencer_sync interface aslcd_video_sequencer_sync.
6. Export the lcd_i2s interface aslcd_i2s.
7. Connect the lcd_pixel_converter_in interface with the st_source interface from the
Energy2LCD block.

Add the JTAG to Avalon Master Bridge

1. From the Component Library, double-click the Bridges and Adaptors -> Memory
Mapped -> JTAG to Avalon Master Bridge component to add it to the system.
2. Rename the bridge as jtag_master.
3. Connect the clock to clk_in ofclk and the reset to the clk_inport of clk_reset.

Figure 25 shows the top level clock structure and connections.

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Figure 25: Top-Level Clock Structure

4. To connect the master interfaces of this block with all the slave interfaces it can access,
right-click the master interface and view the connections, as illustrated in Figure 26.
Figure 26: Connection of the Master Interface

5. Change the base address of Avalon slave interfaces as shown in Table 4. You can view all the
addresses on the Address Map tab.
Table 4: Base Address of Avalon master in Top Level
Instance Name

Interface Name

Interface Base Address

audio_in

audio_if_0_s1

0x00000000

audio_in

i2c_audio_s1

0x00000100

lcd_ctrl

lcd_i2s_config_s1

0x00000200

clock_generate

pll_pll_slave

0x00000300

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Figure 27 shows the main system connections in the System Contents tab.
Figure 27: Data Path Design at Top Level

The following tables list the exported signals and connections for the clock and reset.
Table 5: Exported Signals for Top
Instance Name

Interface Name

Exported Name

Global_reset

In_reset

reset_n

Clock_in

Clk_in

clk_in

Clock_generate

Pll_locked

clock_generate_pll_locked

Video_clk

clock_generate_video_clk

Audio_if_0_audio_export

audio_export

I2c_audio_conduit_end

i2c_audio

Data_analysis

Push_buttons_external_connection

push_buttons

Lcd_ctrl

Lcd_video_sequencer_sync

lcd_video_sequencer_sync

Lcd_i2s

lcd_i2s

Audio_in

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Table 6: Clock and Reset Signals

Clock or Reset out
Global_reset.out_reset

Clock or Reset in
clk_in.clk_in_reset
Clock_generate.reset_n

Clk_in.clk_reset

Jtag_master.clk_reset
Audio_in.config_clk_reset
Lcd_ctrl.lcd_i2s_clk_reset

Clock_generate.Audio_clk_clk_reset

Audio_in.Audio_clk_in_reset
Data_analysis.Clk_in_clk_in_reset
Energy2lcd_inst.sink_reset

Clock_generate.lcd_clk_clk_reset

Energy2LCD_inst.core_reset
Lcd_ctrl.lcd_clk_clk_in_reset

Clk_in.clk

Clock_generate.clk_in

Jtag_master.clk_in
Audio_in.config_clk
Lcd_ctrl.lcd_i2s_clk
Clock_generate.audio_clk_clk

Audio_in.audio_clk_in
Data_analysis.clk_in
Energy2LCD_inst.sink_clk

Clock_generate.lcd_clk_clk

Energy2LCD_inst.core_clk
Lcd_ctrl.lcd_clk

Generate the System

With all of the system connections complete, you are ready to generate the system. To
generate the system, follow these steps:
1. Make sure to review and correct any errors displayed in the messages box. On the
Generation tab, click Generate to create the synthesis files for this system.
2. Review the synthesis path of the system files you have created. In the Quartus II software,
click Add/Remove Files in Project to add the system.qip file into the file list.
3. In the Quartus II software, open the Qsys_lab code file, and open the system.v file created
by Qsys.
4. Review the top-level instance. Ensure that there are no missing or incorrect signal names.
Clock and reset signal names must be correct in the design for the simulation to function
correctly.
5. On the Processing menu, click Start Compilation. The compilation may require several
minutes to complete.
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6. Use the Quartus II Programmer to download the design to the NEEK.

7. Connect the audio cable between the PC and the NEEK board and play some music or
sounds from your connected PC and verify the display on the LCD screen. The accuracy of
the lab results may not be realistic. If the bars are not quite clear on the screen, you can
adjust the volume of the sounds in your machine. Alternatively, you can adjust the fresh
frequency of the data. The data value range changes as well.

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Lab 7: Use System Console to Debug the System (optional)

This lab shows you how to use System Console to debug the system as shown in Figure 28.
System Console performs low-level hardware debugging of Qsys systems. Use the System
Console to debug systems that include IP cores instantiated in your Qsys system, as well
as for initial bring-up of your printed circuit board, and for low-level testing. The LAB_7
directory of the lab_qsys.zip archive contains the supporting files for this lab. The
estimated time to complete this lab is 60 minutes.
Figure 28: System Console Block Diagram

Add System Console Components

To debug the data_analysis subsystem with System Console, follow these steps:
1. In the Quartus II software, open the LAB_7/quartus_lab.qpf project.
2. On the Tools menu, click Qsys.
3. Use the Open command on the file menu to open data_analysis_subsys.qsys

In this lab, you add two components to the system for debugging. One component
is STDataLogicTap, which consists of three Avalon interfaces: one Avalon-ST
source, one Avalon-ST sink and one Avalon-MM slave interface. An Avalon-ST sink
interface receives the data stream from the Audio interface; the maximum absolute
value in the data stream is saved in an internal register which is mapped into an
Avalon slave address space and cleared after it is read. The data stream is sent to
the FIR module through an Avalon-ST source interface. Neither the source nor sink
interface include Start of Packet (SOP) and End of Packet (EOP) signals.
The other component is STPacketLogicTap, which is similar to the STData
LogicTap component, except that the Avalon-ST interface includes SOP and EOP
signals. This component can receive data packets from the FIR and Energy module
and send them to the next instance in the design. An Avalon slave interface
connects with a JTAG to Avalon Master Bridge instance. This makes internal registers
accessible through the System Console.
The STPacketLogicTap and STDataLogicTap components could be inserted
into the Avalon-ST data path and not influence the data processing of the full
design. They can be removed when debugging is completed.

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4.
5.
6.
7.
8.

Select the exported conduit fir_in from the FIR block, and delete the exported signal.
From the FAE Certification Lab group, add the STDataLogicTap component.
Change the name of the STDataLogicTap component to data_in.
In the Export column, export the st_sink interface as fir_in.
From the FAE Certification Lab group, add two instances of the STPacketLogicTap
component.
9. Change the two instance name of one STPacketLogicTap to fir2energy and
energy_out.
10. Delete the exported energy_out conduit from the energy_0 component.
11. In the Export column, export the st_source interface of energy_out as energy_out.
12. Click the Filter button
and select Avalon-ST Interface as the filter condition. Use the
Move Up or Move Down button to adjust the location of the instances. Connect the AvalonST interfaces as shown in Figure 29.
Figure 29: System Connection of Data Analysis

13. Click the Filter button

and select Avalon-MM Interface as filter condition.
14. From the Component Library, double-click the Bridges and Adaptors -> Memory
Mapped -> JTAG to Avalon Master Bridge component to add it to the system.
15. Rename the bridge as master_0.
16. Click Move Up to move this instance to the top position as shown in figure 30.
17. Connect the master interface of master_0 to the slave interface of data_in, fir2energy,
energy_0, and energy_out as shown in Figure 30.
Figure 30: Data Analysis Design with System Console Debug Blocks

18. On the Qsys System menu, click Assign Base Addresses to remove address overlap error.
19. Make sure that the addresses in the system match those in Figure 30.
20. Click the Filter button
and select Clock and Reset Interfaces as the filter condition.
21. Connect the clock interfaces to the clk_in input of the clk block. Connect the reset_sink
and master_clk_reset interfaces to the clk_in input of clk_reset.
22. On the Qsys File menu, click Save.
23. On the File menu click Open and open system.qsys
24. Click the Generation tab and click Generate to create the synthesis files for the design.
25. In the Quartus II software, click Start Compilation on the Processing menu.
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26. After compilation is complete, use the Quartus II Programmer to download the .sof to the
NEEK board.
27. Rename the .sof to reserve it for later usage. For example, you may rename it
Qsys_lab_msb8.sof.

Debug with System Console

To use System Console to debug the system, follow these steps:
1. To open System Console, click System Console from the Tools menu.
2. To list all masters in the design, type the following command:
get_service_paths master
Figure 31 shows an example of the resulting output.
Figure 31: Example Transcript

The get_service_paths command always returns a list, even if the list has a single item.
Consequently, you must index into the list using the lindex command. In this example, the
first element of the list is master_0. Value zero of the list is the jtag_master module located
in the Qsys system top level.
3. To specify the path for the master_0 master service, type the following command if
master_0 is the first element in the list:
setjtag_master_1[lindex[get_service_pathsmaster]1]
Type the following command if master_0 is the first element in the list:

set jtag_master_1 [lindex [get_service_paths master] 0]

After the command runs, the transcript from the interactive session shown in Figure
32 appears.
Figure 32: Example Transcript

The following tables list the address map of each slave module to master_0:
Table 7: Energy_0 Address Mapping
Base Address

0x0

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Offset
Address

Access

Description

0x0 ~ 0x1f

Read Only

Mapped to internal data memory space.

Each 16-bit half word stores one energy
result of each frequency area. The energy
result is one 9-bits data. High 7-bits of half
word are fixed to 0.

0x20

R/W

The calculation length for the energy

calculation. For example if the data is
2048, Energy block accumulates 2048
samples of input as the output.

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0x22 ~ 0x3f

Reserved

Table 8: Data_in block Address Mapping

Base Address

0x40

Offset
Address
0x0

Access

Read Only

Description

The maximum absolute value in the data

stream

Table 9: fir2energy block Address Mapping

Base Address

0x80

Offset
Address
0x0

Access

Read Only

Description

The maximum absolute value in the data

stream

Table 10: energy_out block Address Mapping

Base Address

0x60

Offset
Address
0x0

Access

Read Only

Description

The maximum absolute value in the data

stream

4. To read the internal register content of data_in, type the following command:
master_read_16 $jtag_master_1 0x40 0x1

Figure 33 shows the transcript from this command.

Figure 33: Example Transcript

5. Use the UP and DOWN arrow keys on your computer to scroll through the command history.
Adjust the volume of the input audio and read back the maximum value repeated.
6. The second argument of the command in Step 4 is the base address of the internal register.
To change the address to read the contents of these registers, type the following command:
master_read_16 $jtag_master_1 0x0 0x10

Figure 34 shows the transcript from this command.

Figure 34: Example Transcript

System Console might report that all valid bits have a value of one. In the LCD
display, all histograms reach the top of the screen. This means the register has
overflowed and the current OUTPUT_MSB parameter is not suitable. You must change
the OUTPUT_MSB parameter of the energy_0 module to eliminate the overflow.

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7. Click Open on the File menu and open data_analysis_subsys.qsys

8. Double click energy_0 in the System Contents tab. The parameter editor appears.
9. Set the OUTPUT_MSB parameter to 24.
10. Click Finish to close the parameter editor.
11. Save the subsystem.
12. Click Open on the File menu and open system.qsys.
13. Click the Generation tab and click Generate to create the synthesis files for the design.
14. In the Quartus II software, click Start Compilation on the Processing menu to compile the
Quartus II project.
15. After compilation is complete, close System Console.
16. Use the Quartus II Programmer to download the generated .sof to the NEEK board.
17. On the Tools menu, click System Console.
18. Type the commands shown in Figure 35.
Figure 35: System Console Commands

System Console reports that the high-end bits of registers do not have a value of one. The
OUTPUT_MSB parameter is now an appropriate value. The display of LCD shows that the
histograms do not reach the top of the screen.
19. Type the following command to read the calculation length for the energy calculation:
master_read_16 $jtag_master_1 0x20 0x1
20. Type the following command to change the calculation length to 0x2000 (8192 in Decimal):
master_write_16 $jtag_master_1 0x20 0x2000
21. After the value is changed successfully, watch the LCD display. The histogram changes
slower than previously. Figure 36 shows the transcript from this interactive session:
Figure 36: Example Transcript

22. Close this instance of System Console.

23. Click System Console on the Tools menu to reopen system console.
24. To run the dashboard_example.tcl script file, type the following command:
sourcedashboard_example.tcl.

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Figure 37 shows the dashboard created by this script.

Figure 37: Qsys Dashboard Example

The dashboard_example.tcl file reads back values of registers listed in Tables 7-10. For
16 bands, the dashboard displays 16 bars according to the register value of each band.
The real-time register values in data_in, fir2energy, and energy_out are displayed in
real time value group. The dashboard records and displays the maximal values in the
maximal value group. Click reset maximal to reset history result and restart recording.
The dashboard displays the register values in hex format. When max_energy_out is bigger
then 480, the LED behind lights in red. This warns you that the parameter in the design is
not suitable. You can complete the following steps to learn more about how this works.
1.
2.
3.
4.

Close System Console.

Us the Quartus II Programmer to download the Qsys_lab_msb8.sof file to the NEEK.
On the Tools menu, click System Console.
Source dashboard_example.tcl System Console. Figure 38 shows the results.

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Figure 38: Qsys Dashboard Example with Overflow

Revision History
Date

Revision Number

21 October
2011

1.0

November 2011

Purpose

Initial Altera Wiki posting

Altera Corporation