library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity control_unit is
port ( op
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity 8bitcpu is
port( clk:

: in std_logic_vector(1 downto 0);

in std_logic;
rdX,ACCidX,ACCclrX,PCincrX,PCclrX,IRclrX,IRidX: out std_

logic;
opX,OPCODEX : out std_logic_vector(1 downto 0);
PCoutX : out std_logic_vector (3 downto 0);
output,dataX,IRoutX,ACCoutX,ACCinX : out std_logic_vecto
r(7 downto 0));
end cpu;
architecture cpu_arc of cpu is
component control_unit is
port ( op
: in
std_logic_vector(1 downto 0);
OPCODE
: out std_logic_vector(1 downto 0);
ACC_clr,ACC_ld,
IR_clr,IR_ld,
PC_clr,PC_incr,
rd
: out std_logic);
end component;
component alu_8bit is
port ( in_A,in_B
:in
std_logic_vector(7 downto 0);
opcode
:in
std_logic_vector(1 downto 0);
out_Y
:out
std_logic_vector(7 downto 0));
end component;
component main_memory is
port( address : in std_logic_vector(3 downto 0);
rd
: in std_logic;
data
: out std_logic_vector(7 downto 0));
end component;
component pc is
port ( clock, PCincr, PCclr
PCout
downto 0));
end component;

: in std_logic;
: out std_logic_vector(3

component IR is
port(clock, PCincr, PCclr : in std_logic;
IRin
: in std_logic_vector(7 downto 0);
IRout : out std_logic_vector(7 downto 0));
end component;
component acc is
port (clock,ACCld,ACCclr
:
in std_logic;
ACCin
: in std_logic_vector(7 downto 0);
ACCout
: out std_logic_vector(7 downto 0));

end component;
component encoder_case is
port(
din:in std_logic_vector(7 downto 0);
dout: out std_logic_vector(1 downto 0)
);
end component;
signal S1
: std_logic_vector(3 downto0); ----aDDRESS (pCOUT)
signal S6,S7,S8,S9,S10,S11,S12 : std_logic; ---ACCCLR,ACCID,IRCLR,IRID,PCCLR,PC
INCR,RD
signal S2,S3,S13,S14
: std_logic_vector(7 downto 0); -----DAT
AOUT,IROUT,ACCOUT,ACCIN
signal S4,S5
:std_logic_vector(1 downto 0);
begin
u0: control_unit
port map(op =>S4 ,OPCODE=>S5,ACC_clr=>S6,ACC_ld=>S7,IR_c
lr=>S9,PC_clr=>S10,PC_incr=>S11);
u1: alu_8bit
port map(in_A=>S13,in_B=>S3,opcode=>S5,out_Y=>S14);
u2: main_memory
port map(address => S1,rd => S12,data => S2);
u3: pc
port map(clock=>clk,PCclr=>S10,PCincr=>S11,PCout
=>S1);
u4: IR
port map(clock=>clk, IRld=>S9, IRclr=>S8,IRin=>S
2,IRout=>S3);
u5: acc
port map(ACCin=>S14,clock=>clk,ACCclr=>S6,ACCld=
>S7,ACCout=>S13);
u6: encoder_case
port map(din=>S3,dout=>S4);
output<=S13;
rdX<= S12;
ACCidX<= S7;
ACCidX<= S6;
PCincrX<= S11;
PCclrX<= S10;
IRclrX<= S8;
IRidX<= S9;
opX<= S4;
OPCODEX <= S5;
PCoutX<= S1;
ACCinX<= S14;
dataX<= S2;
IRoutX<= S3;
ACCoutX<= S13;
end cpu_arc;
------------------------accumulator--------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity acc is
port(clock,ACCld,ACCclr : in std_logic;
ACCin : in std_logic_vector(7 downto 0);
ACCout : out std_logic_vector(7 downto 0);
end acc;
architecture w of acc is

signal tmp : std_logic_vector(7 downto0);

begin
process( clock, ACCld,ACCclr)
begin
if (ACClr= '0') then
if (clock'event and clock ='1') then
if (ACCld = '1') then
tmp<= ACCin;
else
end if,
end if,
else
tmp<= "00000000";
end if;
end process;
ACCout<= tmp;
end w;
------------------------alu_8bit-------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity alu_8bit is
port ( in_A, in_B :in std_logic_vector (7 downto 0);
opcode : in std_logic_vector (1 downto 0);
out_Y : out std_logic_vector (7 downto 0);
end alu_8bit;
architecture beh of alu_8bit is
signal tmp : std_logic_vector(7 downto0);
begin
process (opcode)
begin
case(opcode)is
when ("00")=>
tmp<= in_A + in_B;
when ("01")=>
tmp<= in_A - in_B;
when ("10")=>
tmp<= in_A and in_B;
when ("11")=>
tmp<= in_A or in_B;
end case;
end process;
out_Y<= tmp(7 downto 0);
end beh;
----------------------------------control_unit----------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

use ieee.std_logic_arith.all;
entity control_unit is
port ( op
OPCODE
ACC_clr,ACC_ld,
IR_clr,IR_ld,
PC_clr,PC_incr,
rd
end control_unit;
architecture beh of control_unit is
begin
process( op)
begin
if op="00" then
OPCODE<="00";
ACC_clr<='0';
ACC_ld='1';
IR_clr<='0';
IR_ld<='1';
PC_clr<='0';
PC_incr<='1';
rd<='1';
elsif op="01" then
OPCODE<="00";
ACC_clr<='0';
ACC_ld='1';
IR_clr<='0';
IR_ld<='1';
PC_clr<='0';
PC_incr<='1';
rd<='1';
elsif op="10" then
OPCODE<="10";
ACC_clr<='0';
ACC_ld<='1';
IR_clr<='0';
IR_ld<='1';
PC_clr<='0';
PC_incr<='1';
rd<='1';
elsif op="11" then
OPCODE<="11";
ACC_clr<='0';
ACC_ld<='1';
IR_clr<='0';
IR_ld<='1';
PC_clr<='0';
PC_incr<='1';
rd<='1';
end if;

: in std_logic_vector(1 downto 0);

: out std_logic_vector(1 downto 0);

: out std_logic);

end process;
end beh;
---------------------encoder_case-----------------------library ieee;
use ieee.std_logic_1164.all;
entity encoder_case is
port(
din:in std_logic_vector(7 downto0);
dout: out std_logic_vector(1 downto 0)
);
end encoder_case;
architecture encoder_case of encoder_case is
begin
process(din)
begin
case din is
when"11101111"=>dout<="00";
when"00100101"=>dout<="01";
when"10111011"=>dout<="10";
when"10110111"=>dout<="11";
when others=>dout<=null;
end case;
end process encoder;
end encoder_case_arc;

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity IR is
port(clock,IRld,IRclr : in std_logic;
IRin
: in std_logic_vector(7 downto 0);
IRout
: out std_logic_vector(7downto 0);
end IR;
architecture w of IR is
signal tmp : std_logic_vector(7 downto 0);
begin
process( clock, IRld,IRclr)
begin
if(IRclr='0')then
if (clock'event and clock ='1')then
if (IRld ='1')then
tmp<=IRin;
else
end if;
end if;
else
tmp<= "00000000";
end if;

end process;
IRout<= tmp;
end w;

library ieee;
use ieee.std_logic_1164.all;
entity main_memory is
port( address : in integer range 0 to 15;
rd
: in std_logic;
data
: out std_logic_vector(7 downto 0);
end main_memory;
architecture beh of main_memory is
signal sig_q : std_logic_vector(7 downto 0);
type rom_array is array(0 to 15)of std_logic_vector(7 downto 0);
constant rom: rom_array:=( "11101111",
"00100101",
"10111011",
"10110111",
"01110101",
"11010111",
"11011111",
"10100101",
"11111111",
"11110111",
"11011011",
"11011011",
"11011011",
"11011011",
"11011011",
"11011011",
"11011011" );
begin
process(rd)
begin
if rd = '1' then
sig_q<= rom (address);
else
sig_q<= sig_q;
end if;
end process;
data<= sig_q;
end beh;
---------------------------pc-----------------------------------------library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity pc is
port( clock, PCincr, PCclr : in std_logic;
PCout
0));
end pc;

: out std_logic_vector(3 downto

architecture beh of pc is
signal cnt : std_logic_vector(3 downto 0);
begin
process(clock,PCincr,PCclr)
begin
if PCclr = '1' then
cnt <= "0000";
elsif (clock 'event and clock='1') then
if PCincr = '1' then
cnt <= cnt + "1";