MIPS reference card

add rd, rs, rt

sub rd, rs, rt
addi rt, rs, imm
addu rd, rs, rt
subu rd, rs, rt
addiu rt, rs, imm
mult rs, rt
div rs, rt
multu rs, rt
divu rs, rt
mfhi rd
mflo rd
and rd, rs, rt
rd, rs, rt
or
nor rd, rs, rt
xor rd, rs, rt
andi rt, rs, imm
ori rt, rs, imm
xori rt, rs, imm
sll rd, rt, sh
srl rd, rt, sh
sra rd, rt, sh
sllv rd, rt, rs
srlv rd, rt, rs
srav rd, rt, rs
slt rd, rs, rt
sltu rd, rs, rt
slti rt, rs, imm
sltiu rt, rs, imm
addr
j
jal addr
rs
jr
jalr rs
beq rt, rs, imm
bne rt, rs, imm
syscall
lui rt, imm
rt, imm(rs)
lb
lbu rt, imm(rs)
rt, imm(rs)
lh
lhu rt, imm(rs)
rt, imm(rs)
lw
rt, imm(rs)
sb
rt, imm(rs)
sh
rt, imm(rs)
sw
rt, imm(rs)
ll
rt, imm(rs)
sc

bge rx,
bgt rx,
ble rx,
blt rx,
la rx,
li rx,
move rx,
nop

Add
Subtract
Add Imm.
Add Unsigned
Subtract Unsigned
Add Imm. Unsigned
Multiply
Divide
Multiply Unsigned
Divide Unsigned
Move From Hi
Move From Lo
And
Or
Nor
eXclusive Or
And Imm.
Or Imm.
eXclusive Or Imm.
Shift Left Logical
Shift Right Logical
Shift Right Arithmetic
Shift Left Logical Variable
Shift Right Logical Variable
Shift Right Arithmetic Variable
Set if Less Than
Set if Less Than Unsigned
Set if Less Than Imm.
Set if Less Than Imm. Unsigned
Jump
Jump And Link
Jump Register
Jump And Link Register
Branch if Equal
Branch if Not Equal
System Call
Load Upper Imm.
Load Byte
Load Byte Unsigned
Load Half
Load Half Unsigned
Load Word
Store Byte
Store Half
Store Word
Load Linked
Store Conditional

pseudo-instructions
Branch if Greater or Equal
ry, imm
Branch if Greater Than
ry, imm
Branch if Less or Equal
ry, imm
Branch if Less Than
label
Load Address
imm
Load Immediate
ry
Move register
No Operation
ry, imm

rd
rd
rt
rd

=
=
=
=

rs
rs
rs
rs

+
+
+

rt
rt
imm
rt

rd = rs - rt
rt = rs + imm
{hi, lo} = rs * rt
lo = rs / rt; hi = rs % rt
{hi,
lo =
rd =
rd =

lo} = rs * rt
rs / rt; hi = rs % rt
hi
lo

rd
rd
rd
rd

rs &
rs |
(rs
rs

=
=
=
=

rt
rt
| rt)
rt

rt = rs & imm0
rt = rs | imm0
rt = rs imm0
rd
rd
rd
rd
rd
rd

=
=
=
=
=
=

rt
rt
rt
rt
rt
rt

<< sh
>>> sh
>> sh
<< rs
>>> rs
>> rs

rd = rs < rt ? 1 : 0
rd = rs < rt ? 1 : 0
rt = rs < imm ? 1 : 0
rt = rs < imm ? 1 : 0
PC = PC&0xF0000000 | (addr0 << 2)
$ra = PC + 8; PC = PC&0xF0000000 | (addr0 << 2)

PC = rs
$ra = PC + 8; PC = rs
if (rs == rt) PC += 4 + (imm << 2)
if (rs != rt) PC += 4 + (imm << 2)
c0_cause = 8 << 2; c0_epc = PC; PC = 0x80000080

rt
rt
rt
rt

=
=
=
=

imm << 16
SignExt(M1 [rs + imm ])
M1 [rs + imm ] & 0xFF
SignExt(M2 [rs + imm ])

rt = M2 [rs + imm ] & 0xFFFF

rt = M4 [rs + imm ]
M1 [rs + imm ] = rt
M2 [rs + imm ] = rt
M4 [rs + imm ] = rt
rt = M4 [rs + imm ]
M4 [rs + imm ] = rt; rt = atomic ? 1 : 0

R
I
J

R 0 / 20
R 0 / 22
I 8
R 0 / 21
R 0 / 23
I 9
R 0 / 18
R 0 / 1a
R 0 / 19
R 0 / 1b
R 0 / 10
R 0 / 12
R 0 / 24
R 0 / 25
R 0 / 27
R 0 / 26
I c
I d
I e
R0/0
R0/2
R0/3
R0/4
R0/6
R0/7
R 0 / 2a
R 0 / 2b
I a
I b
J2
J3
R0/8
R0/9
I 4
I 5
R0/c
I f
I 20
I 24
I 21
I 25
I 23
I 28
I 29
I 2b
I 30
I 38

6 bits

5 bits

5 bits

5 bits

5 bits

6 bits

op

rs

rt

rd

sh

func

6 bits

5 bits

5 bits

16 bits

op

rs

rt

imm

6 bits

26 bits

op

addr

registers
$0
$1
$2$3

$zero
$at
$v0$v1

$4$7
$8$15
$16$23
$24$25
$26$27
$28

$a0$a3
$t0$t7
$s0$s7
$t8$t9
$k0$k1
$gp

$29
$30
$31
hi
lo
PC

$sp
$fp
$ra

co $13 c0_cause
co $14 c0_epc
syscall codes
for MARS/SPIM
1 print integer
2 print float
3 print double
4 print string
5 read integer
6 read float
7 read double
8 read string
9 sbrk/alloc. mem.
10 exit
11 print character
12 read character
13 open file
14 read file
15 write to file
16 close file
exception causes
0 interrupt
1 TLB protection
2 TLB miss L/F
3 TLB miss S
4 bad address L/F
5 bad address S
6 bus error F
7 bus error L/S
8 syscall
9 break
a reserved instr.
b coproc. unusable
c arith. overflow
F: fetch instr.
L: load data
S: store data